JPS5826673B2 - variable capacity device - Google Patents
variable capacity deviceInfo
- Publication number
- JPS5826673B2 JPS5826673B2 JP4819876A JP4819876A JPS5826673B2 JP S5826673 B2 JPS5826673 B2 JP S5826673B2 JP 4819876 A JP4819876 A JP 4819876A JP 4819876 A JP4819876 A JP 4819876A JP S5826673 B2 JPS5826673 B2 JP S5826673B2
- Authority
- JP
- Japan
- Prior art keywords
- conductivity type
- region
- variable capacitance
- substrate
- regions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 16
- 239000003990 capacitor Substances 0.000 claims description 8
- 230000000903 blocking effect Effects 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は可変容量装置、特に複数個の可変容量ダイオー
ドを一枚の半導体基板内に形成した可変容量装置に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a variable capacitance device, and particularly to a variable capacitance device in which a plurality of variable capacitance diodes are formed within a single semiconductor substrate.
可変容量素子はラジオやテレビのチューナ部分の電子化
に不可欠なものであり、例えばスーパヘテロダイン方式
のラジオであればアンテナ回路、高周波増巾回路、並び
に局発回路の3ケ所に可変容量素子が必要である。Variable capacitance elements are essential for the electronic tuner part of radios and televisions. For example, in the case of a superheterodyne radio, variable capacitance elements are required in three places: the antenna circuit, the high frequency amplification circuit, and the local oscillator circuit. It is.
このような点から該各回路用の3個の素子を一枚の半導
体基板内に形成した所謂集積回路化したものが開発され
ている。From this point of view, a so-called integrated circuit in which three elements for each circuit are formed within a single semiconductor substrate has been developed.
第1図にその断面図を、第2図にその等価回路図を示す
。FIG. 1 shows its sectional view, and FIG. 2 shows its equivalent circuit diagram.
1はN型のシリコン基板、2,2,2はP型頭域、3は
表面保護膜、4,4.4は各P型頭域2,2,2に設け
られたアノード電極、5は基板1に設けられた共通カソ
ード電極、6は可変容量素子である。1 is an N-type silicon substrate, 2, 2, 2 is a P-type head region, 3 is a surface protective film, 4, 4.4 is an anode electrode provided in each P-type head region 2, 2, 2, and 5 is an anode electrode provided in each P-type head region 2, 2, 2. A common cathode electrode 6 provided on the substrate 1 is a variable capacitance element.
斯る構成のものは素子の小型が図れると同時に同じ条件
下で形成されるので、特性の揃った素子が得られる大き
な特徴がある。A device having such a configuration has the great feature that it is possible to reduce the size of the device, and at the same time, it is possible to obtain devices with uniform characteristics because they are formed under the same conditions.
ところが斯る構成では各ダイオード6のカソード側が共
通となっている為に同調コイルを接続してタンク回路を
形成するには第3図の接続方法に依らなければダイオー
ド6にバイアスを掛ける事は出来ない。However, in such a configuration, since the cathode side of each diode 6 is common, it is not possible to apply a bias to the diode 6 unless the connection method shown in Fig. 3 is used to connect the tuning coil and form a tank circuit. do not have.
この第3図の接続状態の等何回路を示すと第4図のよう
になり、この図から明らかな如く、タンク回路に並列に
バイアス抵抗Rが入り、〔Q〕を低下させる事となる。An equivalent circuit with the connection state shown in FIG. 3 is shown in FIG. 4, and as is clear from this figure, a bias resistor R is inserted in parallel with the tank circuit to reduce [Q].
尚、この第3図、第4図に於いてCは可変容量素子6の
容量値、C1は直流阻止用のコンデンサで〔・C>C1
)の関係がある。In addition, in FIGS. 3 and 4, C is the capacitance value of the variable capacitance element 6, and C1 is a capacitor for DC blocking [・C>C1
).
ここで(Q)について考察を加えると、Qは、Q=WC
/g=1/gWL
g=1/R尚、Wは同調周波数、
の関係があり、〔Q〕を大きくする為には〔R)を大き
くすれば良い事は理解されるがダイオード6のリーク電
流を考慮するとこの(R)の値を無暗に大きくする事は
出来ず、通常の場合100にΩ程度が用いられている。Now, if we consider (Q), Q is Q=WC
/g=1/gWL g=1/R Note that W is the tuning frequency, and it is understood that in order to increase [Q], it is sufficient to increase [R], but the leakage of diode 6 Considering the current, the value of (R) cannot be increased arbitrarily, and in the usual case, a value of about 100Ω is used.
本発明はこのような問題点を改善すべく為されたもので
あって、バイアス抵抗〔R〕の影響を無視し得ると共に
、直流阻止用のコンデンサをも内蔵した可変容量装置を
提案する。The present invention has been made to improve these problems, and proposes a variable capacitance device that can ignore the influence of the bias resistor [R] and also has a built-in capacitor for DC blocking.
第5図は本発明装置の構成を示す断面図であって、10
はN型のシリコン基板、11.11.11は該基板10
内に形成された比較的広い面積のP型頭域、12,12
,12はこの各P型頭域11゜11.11内に設けられ
たN型領域で、この各領域12,12,12はP型頭域
11.11.11に比してその面積は格段に小さく選ば
れている。FIG. 5 is a cross-sectional view showing the configuration of the device of the present invention, with 10
is an N-type silicon substrate, 11.11.11 is the substrate 10
P-shaped head area with a relatively large area formed within, 12, 12
, 12 are N-type regions provided within each P-type head region 11°11.11, and the area of each region 12, 12, 12 is much larger than that of the P-type head region 11.11.11. are selected to be small.
13.13,13はN型領域12,12,12に設りら
れたカソード電極、14,14,14はP型頭域11.
11.11に設りられたアノード電極、15はN型の基
板10に設けられた共通電極、16は表面保護膜で、斯
る構成の装置の等価回路は第6図に示されている。13. 13, 13 are the cathode electrodes provided in the N-type regions 12, 12, 12, and 14, 14, 14 are the P-type head regions 11.
An anode electrode provided at 11 and 11, a common electrode provided at 15 and a surface protective film 16, and an equivalent circuit of a device having such a configuration is shown in FIG.
即ちN型領域12.1212とP型頭域11,11,1
1との間に位置するPN接合が可変容量ダイオード17
,17,17に該当し、またP型頭域11.11.11
とN型基板10との間のPN接合が直流阻止用のコンデ
ンサ1B、18,1Bに該当している。That is, N type region 12.1212 and P type head region 11, 11, 1
The PN junction located between the variable capacitance diode 17 and
, 17, 17, and P-type head area 11.11.11
The PN junction between the capacitor and the N-type substrate 10 corresponds to the DC blocking capacitors 1B, 18, and 1B.
この等何回路で示される回路構成であれば、同調コイル
とタンク回路を構成するに際してバイアス抵抗(R)が
タンク回路の(Q)を低下させない第6図に示される回
路を採る事が出来る。With the circuit configuration shown in any of these circuits, it is possible to adopt the circuit shown in FIG. 6 in which the bias resistor (R) does not reduce the (Q) of the tank circuit when configuring the tuning coil and tank circuit.
この第6図に示される回路に依れば、バイアス抵抗(R
)の値は任意に選ぶ事が出来るにも拘らず、〔Q〕の低
下は全くなく、その結果受信機の特性、即ち実用感度、
SN比、■F妨害比、イメージ妨害比等いずれの点に於
いても良い結果が得られる。According to the circuit shown in FIG. 6, the bias resistor (R
Although the value of
Good results can be obtained in terms of SN ratio, F interference ratio, image interference ratio, etc.
本発明は以上の説明から明らかな如く、一導電型半導体
基板内に複数個の逆導電型領域を、また該各領域内に複
数個の一導電型領域を設け、一導電型領域と逆導電型領
域とのPN接合を可変容量素子として用い、逆導電型領
域と基板とのPN接合を直流阻止用のコンデンサとして
用いている。As is clear from the above description, the present invention provides a plurality of regions of opposite conductivity type in a semiconductor substrate of one conductivity type, and a plurality of regions of one conductivity type within each region, and has a conductivity opposite to that of the one conductivity type region. The PN junction between the type region and the substrate is used as a variable capacitance element, and the PN junction between the opposite conductivity type region and the substrate is used as a DC blocking capacitor.
従って各可変容量素子のアノード、カソード各電極が独
立して取り出す事が出来るので、バイアス抵抗の影響を
受けない高い(Q、lの共振回路を作る事が出来ると共
に、直流阻止用のコンデンサも内蔵しているので、外付
は部品の数が減少し、製造の際の手数も省略出来、トー
タルコストの低減化が図れ、更に全ての素子が同じ基板
内に形成されているので、特性の揃った可変容量装置を
得る事が出来る。Therefore, since the anode and cathode electrodes of each variable capacitance element can be taken out independently, it is possible to create a high (Q, l) resonant circuit that is not affected by the bias resistance, and also has a built-in DC blocking capacitor. As a result, the number of external parts is reduced, labor during manufacturing can be omitted, and total cost can be reduced.Furthermore, since all elements are formed on the same substrate, characteristics are uniform. A variable capacitance device can be obtained.
第1図は従来の可変容量装置の断面図、第2図はその等
価回路図、第3図はタンク回路図、第4図はその等価回
路図、第5図は本発明可変容量素子の断面図、第6図は
その等価回路図、第7図は本発明装置を用いたタンク回
路図であって、10は基板、11は逆導電型領域、12
は一導電型領域、13はカソード電極、14はアノード
電極、17は可変容量素子、18は直流阻止用コンデン
サ、を夫々示している。Fig. 1 is a cross-sectional view of a conventional variable capacitance device, Fig. 2 is its equivalent circuit diagram, Fig. 3 is a tank circuit diagram, Fig. 4 is its equivalent circuit diagram, and Fig. 5 is a cross-section of the variable capacitance element of the present invention. 6 is an equivalent circuit diagram thereof, and FIG. 7 is a tank circuit diagram using the device of the present invention, in which 10 is a substrate, 11 is an opposite conductivity type region, and 12 is a tank circuit diagram using the device of the present invention.
13 indicates a one-conductivity type region, 13 a cathode electrode, 14 an anode electrode, 17 a variable capacitance element, and 18 a DC blocking capacitor, respectively.
Claims (1)
逆導電型領域、該各逆導電型領域内に設けられた一導電
型領域と、から成り、各−導電型領域、各逆導電型領域
、並びに基板に夫々外部端子を設け、各−導電型領域と
各逆導電型領域との間のPN接合を可変容量素子として
用い、各逆導電型領域と基板との間のPN接合を直流阻
止用コンデンサとして用いる事を特徴とした可変容量装
置。1 Consists of a semiconductor substrate of one conductivity type, a plurality of regions of opposite conductivity type formed on the substrate, and regions of one conductivity type provided in each of the regions of opposite conductivity type, each region of conductivity type, each region of opposite conductivity type. External terminals are provided on the mold region and the substrate, respectively, and the PN junction between each negative conductivity type region and each opposite conductivity type region is used as a variable capacitance element, and the PN junction between each opposite conductivity type region and the substrate is used as a variable capacitance element. A variable capacitance device characterized by its use as a DC blocking capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4819876A JPS5826673B2 (en) | 1976-04-23 | 1976-04-23 | variable capacity device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4819876A JPS5826673B2 (en) | 1976-04-23 | 1976-04-23 | variable capacity device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS52129384A JPS52129384A (en) | 1977-10-29 |
| JPS5826673B2 true JPS5826673B2 (en) | 1983-06-04 |
Family
ID=12796674
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4819876A Expired JPS5826673B2 (en) | 1976-04-23 | 1976-04-23 | variable capacity device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5826673B2 (en) |
-
1976
- 1976-04-23 JP JP4819876A patent/JPS5826673B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS52129384A (en) | 1977-10-29 |
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