JPS5826836B2 - Manufacturing method of electronic circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a thin, high-density packaging technology for electronic circuits, and particularly to a method for easily forming two-layer wiring.

Conventionally, a chip component such as a semiconductor element is bonded to one main surface of an insulating film, and a tapered through hole is provided from the other main surface of the film to a portion corresponding to the electrode part of the chip component. A mounting body with a structure in which conductor wiring is applied to the wafer has been proposed.

Conventionally, when forming two-layer wiring in an electronic circuit device having this structure, another insulating film is further coated on the other main surface of the above-mentioned film, and through holes are formed in this other insulating resin film. A method is used in which the conductor wiring is connected to a new wiring on another insulating resin film.

That is, conventionally, in this type of electronic circuit package, the following method has been used to form a two-layer wiring structure and bring the electrodes of the chip component into contact with the upper layer wiring pattern.

First, a chip component is fixed to one main surface of a first layer film having a predetermined first through hole, and a first conductive wiring pattern is formed on the other main surface of the first layer film as described above. The first conductor wiring pattern and the electrode of the chip component are connected through the first through hole.

At this point, one package with the chip portion attached is completed.

After this, a thin resin is applied to the entire surface of the other main surface of the first layer of film to form a second layer of insulating film, and a second layer of insulation film is formed on the second layer of film to reach the first conductor wiring pattern. 2 through-holes are formed, and a second conductor wiring pattern is selectively connected to the first conductor wiring pattern via the second through-hole on the second layer of the film.

In such a structure, another 11th and 2nd wiring pattern is connected to the 1st
can be formed on the film and the second film,
It becomes possible to form many wiring lines, and even higher density packaging becomes possible.

However, the problems with the above-mentioned method are as follows: (1) Since there are relatively many steps after the device for chip parts, etc., there is a high possibility that semi-finished products with high added value will be defective.

In other words, a semi-finished product with many electronic components attached to the first layer film is further coated with a resin film, through-holes are formed,
Since the second wiring pattern is formed, half-finished semi-finished products are often rejected.

(2) It was difficult to apply the insulating resin film thinly and uniformly on the first insulating film.

■ It was necessary to form fine contact through holes twice, which had a high possibility of lowering yield.

In consideration of such problems, the present invention provides a method for realizing a rational multilayer wiring structure in a high-density electronic circuit package.

1 to 5 show a method of manufacturing an electronic circuit package according to an embodiment of the present invention.

First, as shown in FIG. 1, a first insulating resin film 1,
A first layer wiring pattern 3 is formed on 2.

Film 1 is a film substrate made of polyimide, polyester, etc., and 2 is an adhesive layer coated with EEP or epoxy resin.

The thickness of each is 10 μm to 50 μm for 1 and several μm for 2.
It is about 10 μm from m to 10 μm.

Depending on the fineness of the wiring pattern 3, a printing method, a vapor deposition method using a metal mask, or a method using a photoetching method is applied.

Next, as shown in FIG. 2, a second resin film 40) is bonded to the surface of the first resin film 1 on which the wiring pattern 3 is formed.

The second resin film 4 may also be the same as the first resin film 1, and an adhesive layer 6 is formed on one main surface of the film 4 as well as the first, and this layer 6 may be the same as the first resin film 1.
Films 1 and 4 are bonded together via 6.

The size of the window portion 5 is slightly larger than the electronic component chip described later, and is determined by considering the positional accuracy when bonding the two films 1.4.

The window portion 5 can be formed using a mechanical method, a plasma method, or a chemical etching method.

It is desirable that the window 5 has a slight taper as shown in the figure.

Next, as shown in FIG. 3, contact through holes 7 and 8 are simultaneously formed in predetermined portions of the films 1 and 4.

In other words, in this process, film 1 is
, 4 are formed with through holes 7 and 8 at the same time.

The through holes 8 provided in the second film 4 are temporarily formed in the second film 4.
This is for electrically connecting the wiring pattern formed on the surface of the first film 1 to the wiring pattern 3 provided on the surface of the first film 1.

The through holes 7 provided in the first film 1 are for electrically connecting the electrodes of the electronic component chip and the wiring pattern on the second film 4.

The formation of these through holes 7 and 8 is realized by photolithography and chemical etching, metal mask and plasma etching, or a combination thereof.

After this, a semiconductor element 9 such as a semiconductor integrated circuit and other electronic chips (not shown) are attached to the film 1 using an adhesive layer 2.
Glue through.

At this time, the through hole 8 and the electrode of the element 9 are aligned (
Figure 4).

Then, as shown in FIG. 5, a second conductor wiring pattern 18 made of Cu/Cr or the like is selectively formed on the other main surface of the films 1 and 4.

Through this step, the electrodes of the element 9 and part of the wiring pattern of the first layer are connected via the second layer wiring pattern 18.

Note that many first-layer wiring patterns (not shown) are formed on the film 1, and elements 9 are also formed on the film 4.
Naturally, many wirings other than this pattern can be formed simultaneously with the pattern 10 connected to the electrode.

As described above, in the present invention, all the through-holes for contacts can be formed before chip components are mounted, so there is no need to mount expensive chip components on a film that has failed in through-hole formation, reducing losses. can.

In other words, it is sufficient to bond a good element 10 to a good film body in which a through hole is formed, and a defect at the time of forming a through hole does not affect the overall defect, as in the conventional case.

Therefore, the present invention greatly contributes to improving the yield and reliability in manufacturing a package with a multilayer wiring structure in which electronic components are mounted at high density.

[Brief explanation of the drawing]

1 to 5 are sectional views showing the manufacturing process of an electronic circuit package according to an embodiment of the present invention. 1.4...Polyimide film, 2,6...
...FEP layer, 3...First layer wiring pattern, 5...Window section, 7, 8...Through hole, 9
... Semiconductor element, 10 ... Second layer wiring pattern.

Claims (1)

[Claims] 1. A step of forming a wiring pattern on the surface of the first resin film, a step of adhering a second resin film having a through window portion to the surface of the first film, and a chip component of the first resin film. a step of forming a contact hole in a predetermined portion of the wiring pattern of the second resin film, and aligning the electrode of the chip component with the contact hole; a step of adhesively fixing the chip component to the first and second
shaping the wiring on the surface of the resin film and simultaneously electrically connecting the wiring on the surface of the second film and the chip component electrode or the wiring pattern on the surface of the first film through the contact hole. A method of manufacturing an electronic circuit device, characterized by comprising: