JPS5827532B2 - System operation control device for data transmission system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention connects a plurality of ports, in which a plurality of terminals are connected via a common bus, with a transmission line in a linear, circular, or net-like manner, and transmits data between arbitrary terminals. The present invention relates to a system operation control device that facilitates system expansion, maintenance, etc. in a data transmission system capable of performing data transmission.

In recent years, data highway systems that utilize time-division multiplex transmission have emerged with the aim of reducing the price and installation costs of transmission cables, and are being adopted in some areas, such as in plant control.

The outline of such a data highway system is as shown in Fig. 1, for example, a central control station CPU such as an electronic computer.
1. The CPU 2 and the port relay processing devices P1 to P5, which accommodate multiple terminals, are connected in a loop so that data can be transmitted between the central control station and the terminals or between the terminals. Since transmission is carried out using lines as the core, there is a strong demand for ease of system expansion and maintenance compared to other conventional transmission systems.

For this reason, for example, when expanding the system, a port is installed at the expansion point so that this can be done online, and after connecting the terminal to be expanded to this port and completing the power supply etc. connection, check whether the operation is normal. The method used is to confirm this and then connect this port to the existing data line.

Furthermore, during system maintenance, it is possible to test the operation of all terminals online at any port without having to go to a port installed in a remote location.

Therefore, in the past, it has been possible to expand and maintain a system relatively easily from a hardware perspective, but when expanding or maintaining a system, it is usually necessary to perform a system diagnosis using software operations. In that case, due to a programming error or the like, an incorrect command could be issued to a normally operating terminal, which could have a serious impact on the system, such as system failure.

The reason for this is that in conventional data transmission systems, when a terminal is accessed by mistake during system diagnosis, there is no mechanism anywhere in the system to prohibit the access operation.

As shown in FIG. 2, the conventional port P1 in the data transmission system shown in FIG. a device coupling section 2, a communication control device 3 that transfers data with other ports via a transmission line 1ine, and a data bus 4a and a control bus 4b used for transferring information between these three.

and a bus control section 5 that performs bus control.

In the same figure, 11 is a processor coupling unit control circuit;
12 is a sending frame register for temporarily setting information from the CPU 1; 13 is an receiving frame register for temporarily setting information to be sent to the CPUI; G 12 a , G 1
2 b s G 13 a and G 13 b are the sending frame register 12 or the receiving frame register 1, respectively.
3 is an input/output gate circuit, 14 is a transfer request flip-flop, 15 is a decoder, 16 is an interface control circuit with the central control station, 51 is a bus control circuit, and 52 is an instruction for temporarily setting the instruction word in the transmission frame. word register, 53
54 is a data word register for temporarily setting a data word in a transmission frame; 54 is a command word reading circuit; 52a;

52b, 53a, and 53b are instruction word registers 52, respectively.
Alternatively, it is an input/output gate circuit for the data word register 53.

Now, for example, data from the central control station CPU1 is sent to the terminal T1.
To explain the operation of each part in the case of writing to 1,
First, a command word consisting of data sent from the central control station CPU1 and information such as its destination is sent to the input gate circuit G.
It is set in the sending frame register 12 by the SET signal of the interface control circuit via the interface control circuit 12a.

The sending frame register 12 and receiving frame register 13 are 12a, 12b and 13a, 13b, respectively.
This is because the bus width of the data bus 4a is narrow, so one transmission frame is divided into two transmissions; if the bus width is wide, the transmission frame can be sent out at once. Only one stage of reception and transmission frame registration is required.

As soon as the processor coupling unit control circuit 11 detects by the signal SET that data has been set in the sending frame register, it sets the transfer request flip-flop 14, and uses the output as P1' to issue a command from the bus control unit 5. The bus control circuit 51 of the waiting bus control unit 5 controls the use of the bus by scanning the addresses of each processing device connected to the data bus 4a, and this address scanning instructs the processor coupling unit 1. When the decoder 15 of the processor coupling unit 1 determines that the processor coupling unit 1 is operating, it applies the output +1111 to the two-processor coupling unit control circuit 11 and the gate circuit G16.

Therefore, at this timing, the output of the gate circuit G16 becomes 1'', and this output becomes the transfer request signal RQ and is applied to the bus control circuit 51 via the control bus 4b.

When the bus control circuit 51 receives the transfer request signal RQ from the processor coupling section 1, it stops the address scanning, makes the data bus 4a1 and the control bus 4b exclusive to the processor coupling section 1, and at the same time transfers the command read signal R1 to the control bus 4b. The data is sent to the processor coupling unit 1 via.

The processor coupling unit control circuit 11 receives the instruction word read signal R1.
When the instruction word is received, the gate signal GRI is sent to the output gate circuit G12b, and the instruction word is sent to the data bus 4 in the transmission frame set in the sending frame register.
The data is sent to the bus control unit 5 via a.

Since the bus control circuit 51 also applies the instruction word read signal R1 to the input gate circuit 52a of the instruction word register 52, the instruction word sent from the processor coupling section 1 is set in the instruction word register 52.

Similarly, at the next timing, the bus control circuit 51 generates a data word read signal R2, and as a result, the data set in the sending frame register 12 is transferred to the bus control unit 5.
is set in the data word register 53 of .

Next, the bus control circuit 51 decodes the command word in the command word register 52 with the reading circuit 54, and when it is determined that the content is a data write command to the terminal T11, the bus control circuit 51 starts the device coupling section 2 at the next timing. The instruction word write signal W1 is sent to the terminal T11 via the terminal T11, and the instruction word write signal W1 is also applied to the output gate circuit 52b to open it, so that the instruction word set in the instruction word register 52 is ,
The terminal T11 via the data bus 4a and the device coupling section 2
will be written in.

Similarly, the bus-based circuit 51 receives the data word write signal W2.
and writes the data word set in the data word register 53 to the terminal T11.

In the above, data from the central control station CPU1 is transmitted to the terminal T11.
The operation of each part has been explained for the case where data is written to the central control station CPU1 and the central control station CP from the terminal T11.
Data transmission from the UI to the terminals of other relay processing devices is performed in the same way via the communication control device 3.

As described above, in the conventional relay processing device, for example, in order to test the terminal Tll, the central control station CPU1
If the destination station address of the transmission frame sent to 11 is incorrectly set as the terminal TIN address, there is no mechanism anywhere in the system to prohibit access to that transmission frame, so incorrect data will be written to the terminal TIN. It turns out.

The present invention improves the conventional drawbacks as mentioned above,
The purpose of this is to ensure that even if there is a program error or manual operation error during system diagnosis, it will not affect terminals that are operating normally, making system expansion and maintenance easier, and ensuring a highly reliable system. It is something that will be realized.

Examples will be described in detail below.

FIG. 3 shows an example of the format of a transmission frame used in the present invention, where F is a flap for frame synchronization, ADR is an address part containing address information of the other terminal to access, etc., and C0NT is a control information such as reading or writing. The control section included, DAT is a data word consisting of data information, and Fe2 is a frame check fence. For example, if the address section ADR and control section C0NT are composed of 16 bits, the transmission frame is in normal mode. mode designation bit (1 bit) to specify whether the terminal is connected to a remote terminal or diagnostic mode, and address bits (4 bits) of the boat where the other terminal is accommodated.
, address bits (4 bits) of the other terminal in the boat, and command bits (7 bits), etc. Therefore, in this case, the data transmission system has a maximum of 16 boats, and 1 Up to 16 terminals can be connected to a single boat.

FIG. 4 is a block diagram of a bus control section according to an embodiment of the present invention, where 6 is a bus control section, 61 is a mode registration register,
62 is a selector, 061 to G62 are AND gates, EO
R is an exclusive OR circuit, and the same symbols as in FIG. 2 indicate the same parts.

The mode registration register 61 is used to register in advance whether each terminal accommodated in its own port is in normal mode or diagnostic mode.For example, when a certain terminal is in normal mode,
In the diagnostic mode, O'' is written in the bit corresponding to the address number of the terminal in the mode registration register 6.

Writing of mode setting information to the mode registration register 61 is performed from the central control station via the data bus 4a as follows.

When the reading circuit 54 decodes that the information sent to the cellar 1 in the command word register 52 is a write command to the mode registration register 61, the control circuit 51 sets the write gate signal WTG to '1', and the data word register The mode registration information output from 53 is transferred to data bus 4a.

It is set in the mode registration register via AND gate G61.

Further, if it is desired to check the contents of the mode registration register 61, the contents of the mode registration register 61 can be read by applying a read gate signal RDG to the ant game 1-062.

Now, as in the explanation of the conventional example, the central control station C in FIG.
The operation of the bus control unit shown in FIG. 4 will be described below in the case where data is written from PU1 to terminal T11.

First, in response to the instruction word read signal R1 from the bus control circuit 51, an instruction word consisting of an address section and a control section including mode designation information, destination terminal address, etc. as shown in FIG. 3 is sent from the processor coupling section to the instruction register. It is set to 52.

Similarly, at the next timing, a data word is set in the data word register 53 by the data word read signal R2.

The mode registration register 61 contains mode information of all terminals accommodated in the board 1-.

Therefore, in order to select only the mode setting information of the terminal currently being accessed from among these, only the address information of the other terminal is added from the command word register 52 to the selector 62, and thereby the target terminal is selected from the parallel output of the mode registration register 61. Only mode setting information is selected.

The output of the selector 62 is applied to one input terminal of the exclusive OR circuit EOR, and the mode designation information is added to the other input terminal from the instruction word register 52 in which the instruction word is set. The exclusive OR of both is calculated by the logical OR circuit EOR.

Therefore, if the two signals do not match, the output of the exclusive OR circuit FOR will be 1'', otherwise it will be 'O''.

The output of the exclusive OR circuit EOR is applied to the bus control circuit 51, and the bus control circuit 51
Output from +! When it is 1++, it does not proceed to the next state, and the command word and data word write signals Wl and W2 to be sent to the terminal T11 are not sent.

Therefore, when the mode designation information in the transmission frame and the mode setting information of the terminal T11 set in advance in the mode registration register 61 are different, the data is transferred to the terminal T1.
It will not be written to 1.

Further, when the output of the exclusive OR circuit EOR is "0", the bus control circuit 51 sends out the data write signals W1 and W2 as in the conventional case, so the contents of the command word register 52 and data word register 53 are transferred to the terminal. The data will be sent to T11 and the data will be written.

In this way, the bus control unit 6 detects for each transmission frame whether the mode setting information set in advance for each terminal matches the mode designation information in the transmission frame, and if they do not match, the transmission frame Since the configuration is such that only normal mode data is written to the normal mode terminal, diagnostic mode data is not written to the normal mode terminal.

FIG. 5 is a block diagram of a bus control circuit according to another embodiment of the present invention, in which 7 is a bus control section, 71 is a mode information extraction circuit, and the same reference numerals as in FIG. 2 indicate the same parts.

FIG. 6 shows an example of the configuration of the interface section of each terminal when the bus control section is configured as shown in FIG. 82 is an output register for setting write information, 83 is an input register to which read information is set, 84 is a mode setting circuit, and 081 to G83 are AND cases.

Bus control circuit 51 generates command and data word read signals R1 and R2 as before, and reads the command and data words into command word register 52 and data word register 53 via data bus 4a.

At this time, the mode information extraction circuit 71 uses the instruction word register 52.
Only mode designation information is extracted from the command words set in , and this mode designation information is sent to the bus control circuit 51.

The bus control circuit 51 sends command word and data word write signals W1 and W2 to the destination terminal decoded by the reading circuit 54, but in synchronization with the sending of these signals, the mode designation from the mode information extraction circuit 71 The information is sent to the target terminal via the control bus 4b.

In the interface section of the terminal, the bus control circuit 5
The mode setting information mio sent from 1 and the mode setting information mio previously set in the mode setting circuit 84 by an external switch etc. are compared in the mode-number setting circuit 81, and the mode-number setting circuit 81 When both signals match, AND gate G81. The configuration is such that a gate signal is sent to G82, and no gate signal is sent otherwise.

Therefore, when the mode setting information mio and the mode designation information mb match, when the command word and data word write signals W1, W2 and address information are applied from the bus control circuit 51 to the AND gate G81, the ant gate G81 The output will be 01'' and the data will be set in the output register 82 and written to the terminal.

On the other hand, if both signals do not match, the ant gate G81
The output becomes 0"', the output register 82 is not set, and no data is written.

In this embodiment, the operating mode of each terminal is set by the mode setting circuit 84, and this mode setting signal and the mode designation signal sent from the bus control circuit 51 are transmitted every transmission frame. Since the data is written according to the matching conditions, if the mode setting signal of the terminal in normal operation is set to normal mode during system diagnosis, the transmission frame of the diagnostic mode may be incorrectly transmitted. It is never written to the terminal.

As explained above, the present invention provides a system operation control device for a data transmission system in which a plurality of boats connected to a plurality of terminals via a common bus are connected in a line, ring, or net shape.
a setting circuit that receives mode designation information specifying whether the transmission frame is in a normal mode or a diagnostic mode in a transmission frame, and sets an operation mode of the terminal in a bus control unit that controls each terminal or the common bus; , means for detecting a match between the mode setting information of the setting circuit and the mode designation information each time the transmission frame is sent out, and validating the transmission frame only when they match; By setting a normally operating terminal to the normal mode, there will be no possibility that a diagnostic mode transmission frame will be written in error.

Therefore, expansion and maintenance of the system is easy, and a highly reliable system can be realized.

In addition, in the present invention, if the mode designation information in the transmission frame and the mode setting information on the hardware side are made into multiple modes of 2 bits or more, and the mode is assigned to each central processing unit, communication between the terminal and the central processing unit can be improved. It becomes possible to make correspondences, and when a plurality of central processing units are installed on a data highway, it is possible to configure a data transmission system completely free from interference from other central processing units.

[Brief explanation of drawings]

Fig. 1 is a schematic diagram of a data transmission system, Fig. 2 is a block diagram of a conventional relay processing device, Fig. 3 is a configuration example of a transmission frame used in the present invention, and Figs. 4 and 5 are in accordance with the present invention. FIG. 6 is a block diagram of the interface of each terminal when the bus control section is configured as shown in FIG. 5. CPUI, CPU2 is a central processing unit, P1 to P5 are relay processing devices, T11 to T5N are terminals, 1 is a processor coupling unit, 2 is a device coupling unit, 3 is a communication control unit, 4a is a data bus, 4b is a control bus, 56.7 is the bus control unit, 5
1 is a bus control circuit, 52 is a command word register, 53 is a data word register, 54 is a reading circuit, 61 is a mode registration register, 62 is a selector, 63 is an address register, 71
81 is a mode extraction circuit, 81 is a mode-several output circuit, and 84 is a mode setting circuit.

Claims (1)

[Claims] 1. In a system operation control device of a data transmission system in which a plurality of relay processing devices each having a plurality of terminals connected through a common bus are connected in a linear, circular, or net shape, the system operation control device determines whether the transmission frame is in the normal mode or not during the transmission frame. a setting circuit that provides mode designation information that specifies whether the mode is a diagnostic mode, and sets the operation mode of the terminal in each terminal or a bus control unit that controls the common bus; 1. A system operation control device for a data transmission system, comprising means for detecting a match between mode setting information and the mode designation information, and validating the transmission frame only when they match.