JPS5827660B2 - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS5827660B2 JPS5827660B2 JP56032615A JP3261581A JPS5827660B2 JP S5827660 B2 JPS5827660 B2 JP S5827660B2 JP 56032615 A JP56032615 A JP 56032615A JP 3261581 A JP3261581 A JP 3261581A JP S5827660 B2 JPS5827660 B2 JP S5827660B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring layer
- bonding pad
- base
- semiconductor
- wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W46/00—Marks applied to devices, e.g. for alignment or identification
- H10W46/601—Marks applied to devices, e.g. for alignment or identification for use after dicing
- H10W46/603—Formed on wafers or substrates before dicing and remaining on chips after dicing
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5524—Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/921—Structures or relative sizes of bond pads
- H10W72/922—Bond pads being integral with underlying chip-level interconnections
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/932—Plan-view shape, i.e. in top view
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の電極取り出し構造に係り、主とし
てリニアIC等において、高抵抗拡散抵抗等の素子とア
ルミニウム配線とのコンタクト部に異常なコンタクトア
ロイが生ずるのを防止し、よって上記コンタクト部等の
各端子の静電破壊強度を高めることを目的とする。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electrode lead-out structure of a semiconductor device, and is mainly used to prevent abnormal contact alloy from occurring at a contact portion between an element such as a high-resistance diffused resistor and an aluminum wiring in a linear IC or the like. Therefore, the purpose is to increase the electrostatic breakdown strength of each terminal such as the contact portion.
リニアIC等において、各端子特にポンディングパッド
と拡散抵抗とのコンタクト部において静電破壊強度不良
が発生することがある。In linear ICs and the like, electrostatic breakdown strength failures may occur at each terminal, particularly at the contact portion between a bonding pad and a diffused resistor.
かかる原因を追求したところかかる破壊は拡散層の深さ
が1μ以下と薄い部分に上記コンタクトが形成されてい
るような場合に生じやすく、またアルミニウムが上記拡
散抵抗を形成した領域(あるいはシリコン基板)中に浸
透して異常なコンタクトアロイが生ずるからであるとい
うことが判明した。Investigating the cause of this problem, we found that such damage tends to occur when the contact is formed in a thin part of the diffusion layer with a depth of 1 μm or less, and that aluminum is likely to occur in the area where the diffusion resistor is formed (or in the silicon substrate). It was found that this is because the contact alloy penetrates into the inside and causes an abnormal contact alloy.
この場合、上記アルミニウムの浸透現象は、ペレット付
け、外部リード線のボンディングあるいは封止等の各処
理工程時の熱により促進される。In this case, the aluminum penetration phenomenon is accelerated by heat during each processing step such as pellet attachment, external lead wire bonding, or sealing.
更に上記アルミニウムの浸透現象を解析したところ、該
現象は、上記ポンディングパッドから上記拡散抵抗のコ
ンタクト穴(すなわち、上記拡散抵抗に対するコンタク
トを得るために半導体基本上に形成されている絶縁膜に
あけられた穴)までのアルミニウム配線の距離が短いほ
ど生じやすいことが判明した。Further analysis of the aluminum penetration phenomenon revealed that the phenomenon is caused by the contact hole of the diffused resistor from the bonding pad (i.e., a hole is opened in the insulating film formed on the semiconductor base to obtain a contact to the diffused resistor). It has been found that the shorter the distance of the aluminum wiring to the hole (with holes), the more likely it is to occur.
そこで、上記ポンディングパッドとコンタクト穴間の距
離(両者間を最短距離で結ぶ線の長さ)を大きくするこ
とにより、その間のアルミニウム配線長を大きくして上
記浸透現象を防止することができると考えられる。Therefore, by increasing the distance between the bonding pad and the contact hole (the length of the line connecting the two at the shortest distance), it is possible to increase the length of the aluminum wiring between them and prevent the above penetration phenomenon. Conceivable.
しかしこの場合ペレットサイズが大きくなりコスト高に
なると共にパターン設計に自由度を欠くおそれがある。However, in this case, the pellet size becomes large, which increases the cost, and there is a fear that there is a lack of freedom in pattern design.
本発明は上記問題点を考慮して上記従来の欠点を除去し
たものであり、以下図面と共にその1実施例につき説明
する。The present invention takes the above-mentioned problems into consideration and eliminates the above-mentioned conventional drawbacks, and one embodiment thereof will be described below with reference to the drawings.
図は本発明になる電極取り出し構造の1実施例の平面図
を示す。The figure shows a plan view of one embodiment of the electrode extraction structure according to the present invention.
図中、1はポンディングパッドで、リニアICのSiペ
レット2にスクライブ領域3の近くにアルミニウム層に
より図のようにほぼ方形を或して形成されている。In the figure, reference numeral 1 denotes a bonding pad, which is formed on the Si pellet 2 of the linear IC near the scribe area 3 by an aluminum layer in a substantially rectangular shape as shown in the figure.
4は拡散抵抗で、上記ペレット2中に所定の不純物を選
択的に拡散することにより前述したように1μ以下と薄
く形成されている。Reference numeral 4 denotes a diffused resistor, which is formed as thin as 1 μm or less by selectively diffusing a predetermined impurity into the pellet 2, as described above.
この拡散抵抗4のコンタクト穴4aと上記ポンディング
パッド1との距離lは、従来と同程度である。The distance l between the contact hole 4a of the diffused resistor 4 and the bonding pad 1 is approximately the same as that of the conventional one.
5は上記ポンディングパッド1と拡散抵抗4とを結ぶア
ルミニウム配線で、くし形状(ポンディングパッド1の
一辺に沿って平行な部分と、その部分に直交する部分と
を有する形状)に迂回した形状とされている。Reference numeral 5 denotes an aluminum wiring connecting the bonding pad 1 and the diffused resistor 4, which is detoured into a comb shape (a shape having a part parallel to one side of the bonding pad 1 and a part perpendicular to the part). It is said that
従ってこのアルミニウム配線5の長さは、上記ポンディ
ングパッド1とコンタクト穴4aとの距離を従来と同程
度の長さlとしているにもかかわらず、該長さlよりは
犬なる値を有している。Therefore, although the distance between the bonding pad 1 and the contact hole 4a is set to the same length l as in the conventional case, the length of the aluminum wiring 5 has a value that is smaller than the length l. ing.
なお上記アルミニウム配線5の幅はコンタクト部におけ
るアルミニウムの幅よりも狭くして前記浸透現象をより
効果的に防止しうる様形戎されている。The width of the aluminum wiring 5 is narrower than the width of the aluminum in the contact portion, so that the above-mentioned penetration phenomenon can be more effectively prevented.
特に、図面から明らかなように、ポンディングパッド1
と接続部(コンタクト穴)4aとの間の配線層5はその
ポンディングパッド1の辺に沿う第1配線層部分(ポン
ディングパッド1の辺に沿って平行に配置されている部
分)とそのポンディングパッド1から遠ざかる第2配線
層部分(上記平行配置部分に対して直交して配置されて
いる部分)とより収り、かつ上記第1配線層部分は上記
第2配線層部分よりも長く形成されている。In particular, as is clear from the drawing, the pounding pad 1
The wiring layer 5 between the and the connecting portion (contact hole) 4a includes a first wiring layer portion along the side of the bonding pad 1 (a portion arranged parallel to the side of the bonding pad 1) and a first wiring layer portion along the side of the bonding pad 1. The first wiring layer portion is longer than the second wiring layer portion, and the second wiring layer portion is longer than the second wiring layer portion. It is formed.
したがって、上記ポンディングパッド1とコンタクト穴
間の距離(両者間を最短距離で結ぶ線の長さ)lが短く
ても第1配線層部分の存在によってポンディングパッド
から半導体領域までの実質的な距離を充分大きくするこ
とができる。Therefore, even if the distance l between the bonding pad 1 and the contact hole (the length of the line connecting the two at the shortest distance) is short, due to the presence of the first wiring layer portion, the distance from the bonding pad to the semiconductor region is The distance can be made sufficiently large.
このため、ポンディングパッドの材料が半導体領域へ浸
透するのを確実に防止し得ることができる。Therefore, it is possible to reliably prevent the material of the bonding pad from penetrating into the semiconductor region.
また、かかる配線層5の構造は、前述したように拡散層
の深さが1.μ以下と薄い場合において、パターン設計
の自由度を欠くことなく静電破壊強度を高めることがで
きる。Further, in the structure of the wiring layer 5, the depth of the diffusion layer is 1.5 mm, as described above. When the thickness is less than μ, the electrostatic breakdown strength can be increased without sacrificing freedom in pattern design.
そして、さらに上記した配線層5の構造は、図面から明
らかなようにポンディングパッドと接続部との間を最短
距離で結ぶ線上に他の配線層が存在していない場合に有
効であり、配線層の高密度化を計ることができる。Further, as is clear from the drawing, the structure of the wiring layer 5 described above is effective when no other wiring layer exists on the line connecting the bonding pad and the connection part at the shortest distance. It is possible to increase the density of layers.
なお、上記アルミニウム配線5はくし形状に限定される
ことなく、要するに上記の如く迂回させる形状とするこ
とによりその長さを犬にすれば良く、種々の形状に形成
しうろことは勿論である。Note that the aluminum wiring 5 is not limited to the comb shape, but may be formed into a detour shape as described above, so that the length thereof can be shortened, and it goes without saying that it can be formed in various shapes.
上述の如く、本発明になる半導体装置の電極取り出し構
造によれば、リニアIC等において、ポンディングパッ
ドと拡散抵抗等の素子とを結ぶアルミニウム配線を長く
しているため、従来の如き異常なコンタクトアロイの発
生を防止でき、従ってこれが原因して生ずる上記拡散抵
抗等の素子の静電破壊強度不良を有効に防止し得、又上
記アルミニウム配線は図面に示すように上記ポンディン
グパッドとコンタクト穴との所定面積内で他の配線を存
在させないで迂回させた形状としているため、上記アル
ミニウム配線が長くなったにもかかわらず上記ポンディ
ングパッドとコンタクト穴との距離は従来と同程度にし
得、従ってパターン設計等も自由に行なうことができる
等の特長を有するものである。As described above, according to the electrode lead-out structure of a semiconductor device according to the present invention, the aluminum wiring connecting the bonding pad and the element such as the diffused resistor in a linear IC or the like is made long, so that there is no abnormal contact as in the conventional case. It is possible to prevent the formation of alloy, and therefore it is possible to effectively prevent electrostatic breakdown strength defects of elements such as the above-mentioned diffused resistor caused by this, and the above-mentioned aluminum wiring is connected to the above-mentioned bonding pad and contact hole as shown in the drawing. Since the shape is such that no other wiring exists within the predetermined area of the contact hole, the distance between the bonding pad and the contact hole can be kept at the same level as before, even though the aluminum wiring has become longer. It has the advantage that pattern design etc. can be done freely.
図面は本発明になる半導体装置の電極取り出し構造の1
実施例の平面図である。
1・・・・・・ポンディングパッド、2・・・・・・ペ
レット、3・・・・・・スクライブ領域、4・・・・・
・拡散抵抗、4a・・・・・・コンタクト穴、5・・・
・・・アルミニウム配線、l・・・・・・ポンディング
パッドとコンタクト穴との距離。The drawing shows one of the electrode extraction structures of the semiconductor device according to the present invention.
FIG. 3 is a plan view of the embodiment. 1...Ponding pad, 2...Pellet, 3...Scribe area, 4...
・Diffused resistance, 4a...Contact hole, 5...
...Aluminum wiring, l...Distance between the bonding pad and the contact hole.
Claims (1)
領域に接続する接続部を有し上記基本上に延在した配線
層と、上記基本上平面において上記領域より離間し、か
つ上記配線層に接続されたポンディングパッドとを有す
る半導体装置において、上記ポンディングパッドと接続
部との間の配線層は上記基本上平面において上記ポンデ
ィングパッドに沿う第1配線層部分と上記ポンディング
パッドから遠ざかる第2配線層部分とより成り、かつ上
記第1配線層部分は上記第2配線層部分よりも長く形成
されていることを特徴とする半導体装置。 2 半導体基本内に形成された半導体素子領域と、その
領域に接続する接続部を有し、上記基本上に延在した配
線層と、上記基本上平面において上記領域より離間し、
かつ上記配線層に接続されたポンディングパッドとを有
する半導体装置において、上記ポンディングパッドと接
続部との間の配線層は上記基本上平面において上記ポン
ディングパッドに沿う第1配線層部分と上記ポンディン
グパッドから遠ざかる第2配線層部分とより戒り、上記
第1配線層部分は上記第2配線層部分よりも長く形成さ
れ、かつ、上記半導体領域の深さは1μ以下であること
を特徴とする半導体装置。 3 半導体基本内に形成された半導本素子領域と、その
領域に接続する接続部を有し上記基本上に延在した配線
層と、上記基本上平面において上記領域より離間し、か
つ上記配線層に接続されたポンディングパッドとを有す
る半導体装置において、上記ポンディングパッドと接続
部との間の配線層は上記基体上平面において上記ポンデ
ィングパッドに沿う第1配線層部分と上記ポンディング
パッドから遠ざかる第2配線層部分とより成り、上記第
1配線層部分は上記第2配線層部分よりも長く形成され
、かつ、上記ポンディングパッドと接続部との間を最短
距離で結ぶ線上には上記配線層以外の配線層が存在して
いないことを特徴とする半導体装置。[Scope of Claims] 1. A semiconductor element region formed within a semiconductor base, a wiring layer having a connecting portion connected to the region and extending on the base, and a wiring layer spaced apart from the region in the upper plane of the base. , and a bonding pad connected to the wiring layer, wherein the wiring layer between the bonding pad and the connection portion has a first wiring layer portion along the bonding pad in the basic upper plane. A semiconductor device comprising a second wiring layer portion extending away from the bonding pad, and wherein the first wiring layer portion is formed longer than the second wiring layer portion. 2. A semiconductor element region formed in a semiconductor base, a wiring layer having a connection portion connected to the region and extending on the base, and spaced apart from the region in the upper plane of the base,
and a bonding pad connected to the wiring layer, in which the wiring layer between the bonding pad and the connection portion has a first wiring layer portion along the bonding pad in the basic upper plane and a bonding pad connected to the wiring layer. The first wiring layer portion is formed longer than the second wiring layer portion, and the depth of the semiconductor region is 1 μm or less. semiconductor device. 3. A semiconductor main element region formed within a semiconductor base, a wiring layer having a connecting portion connected to the region and extending over the base, and a wiring layer spaced apart from the above region in the upper plane of the base and the above wiring. In a semiconductor device having a bonding pad connected to a layer, a wiring layer between the bonding pad and the connection portion has a first wiring layer portion along the bonding pad on the plane above the substrate and a bonding pad connected to the bonding pad. a second wiring layer portion that is farther away from the bonding pad; A semiconductor device characterized in that there is no wiring layer other than the above wiring layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56032615A JPS5827660B2 (en) | 1981-03-09 | 1981-03-09 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56032615A JPS5827660B2 (en) | 1981-03-09 | 1981-03-09 | semiconductor equipment |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7992373A Division JPS5720708B2 (en) | 1973-07-17 | 1973-07-17 |
Related Child Applications (4)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59063302A Division JPS6043662B2 (en) | 1984-04-02 | 1984-04-02 | semiconductor equipment |
| JP59063301A Division JPS6043661B2 (en) | 1984-04-02 | 1984-04-02 | semiconductor equipment |
| JP59063303A Division JPS59188148A (en) | 1984-04-02 | 1984-04-02 | Semiconductor device |
| JP59063304A Division JPS59188149A (en) | 1984-04-02 | 1984-04-02 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56138943A JPS56138943A (en) | 1981-10-29 |
| JPS5827660B2 true JPS5827660B2 (en) | 1983-06-10 |
Family
ID=12363754
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56032615A Expired JPS5827660B2 (en) | 1981-03-09 | 1981-03-09 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5827660B2 (en) |
-
1981
- 1981-03-09 JP JP56032615A patent/JPS5827660B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56138943A (en) | 1981-10-29 |
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