JPS5827670B2 - semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device, and more particularly to a so-called one-transistor memory cell structure configured with one transistor per one bit memory cell.

A RAM (random access memory) device using a one-transistor memory cell with a small number of constituent elements per bit is used as a highly integrated, large-capacity semiconductor memory.

The memory cell is composed of a capacitive element as an information storage section and a gate transistor that controls writing to or reading from the capacitive element, but since these elements are manufactured in a so-called planar structure, the area efficiency is good. Not, but
Therefore, the memory capacity that can be integrated on a fixed chip area is limited.

Furthermore, it is necessary to increase the capacitance of the information storage capacitor section to reduce the storage time, but increasing the capacitance by making the dielectric layer thinner tends to cause pinholes and other problems, resulting in a lack of reliability. There are drawbacks, and increasing the capacity area leads to a reduction in the degree of integration.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a one-transistor memory cell structure capable of improving the degree of integration and increasing the capacity of an information storage section.

The present invention will be explained in detail below with reference to the drawings.

FIG. 1 is a sectional view showing the order of manufacturing steps for manufacturing a device according to an embodiment of the present invention.

A P-type semiconductor substrate 1 is prepared, and an N-type low-resistance impurity region 2 is selectively diffused over the entire surface of the substrate as shown in A.

This diffusion region 2 is used as a bit line of a memory circuit.

Next, as shown in B, an N-type semiconductor layer is formed on the upper surface of the substrate 1 by, for example, epitaxial growth, and a silicon oxide film is formed on the upper surface at a predetermined portion facing the impurity region 2 as a bit line provided earlier. 4 and silicon nitride film 5 are selectively deposited in this order.

The thickness of the epitaxial layer 3 in this case is 1 to 1.5μ,
About 500 people for silicon oxide film 4, about 1 person for silicon nitride film
It is preferable to set the number to 500 people.

Then, the epitaxial layer 3 is selectively etched using the silicon nitride film 5 as an etching mask to obtain the structure shown in C.

In this state, as shown in D, in order to convert the portion of the epitaxial layer 3 thinned by etching into an oxide film 6 to obtain a mesa-shaped region 3a, the epitaxial layer is oxidized using the nitride film 5 as an oxidation-resistant mask. The film 6 is made to be approximately equal to the upper surface of the mesa-shaped region 3a, and so-called LOCO8 technology is used.

After removing the uppermost nitride film 5, a P-type doped region 7 is formed in the mesa-shaped region 3a by ionizing, for example, boron under predetermined conditions and using a so-called ion implantation technique. Area is upper layer 8 and lower layer 9
The structure shown in E is such that the two are separated from each other.

After that, as shown in F, for example, aluminum 10 is coated on the entire surface.
The aluminum film 10 is used as an etching mask to etch the oxide film 6 as shown in G.

In this case, etching is performed by taking advantage of the fact that there is no aluminum film directly under the overhang portion of the oxide film 4 caused by the oxidation step in E.

Then, the oxide film 4 and the aluminum film 10 are removed, and a silicon oxide film 11 as a gate film is formed on the entire surface of the mesa-shaped region by a well-known method.

A silicon nitride film 12 is selectively deposited on the silicon oxide film 11a on the upper surface of the mesa-shaped region as shown in H, and further, for example, polysilicon 13 is selectively formed thereon.

Then, an insulating film 14 is provided to surround this polysilicon 13, and finally, as shown in FIG. 2, a wiring layer 15 of aluminum or the like is deposited on the entire surface and patterned to obtain the memory cell structure of the present invention. can.

In this case, the aluminum layer 15 serves as the control electrode and also serves as the word line of the memory.

In such a configuration, the part of the P-type doped isolation region 7 in contact with the gate film 11 operates as a channel region, and the upper part 8 of the mesa-shaped region separated by the isolation region 7 and its upper surface The silicon oxide film 11a, the silicon nitride film 12 thereon, and the polysilicon 1 on the top surface thereof
3 constitutes an information storage capacity section.

That is, by making the silicon oxide film 11a as thin as 20 to 50 nm thick, tunnel transition of carriers is made possible, and the so-called charge trap, which is the center of carrier capture, is mainly made of a different dielectric layer.
The so-called well-known MNO8 structure exists at the interface between the silicon nitride film 12 and the silicon nitride film 12.

In the above structure, if the polysilicon layer 13 is connected to, for example, the reference messenger v8s and used as one electrode of the capacitive part, the equivalent circuit of FIG. 2 will be as shown in FIG. 4.

A transistor memory cell consisting of a gate transistor T1 and a capacitor C1 is obtained.

Therefore, by selectively applying a write or read control signal to the word line, an inversion layer is formed in the channel of the isolation region 7, and the gate transistor T1 is turned on.

As a result, information corresponding to the bit line is written into the storage capacitor C1 via this transistor T1, and information written in the capacitor C1 is read out to the bit line via the transistor.

In particular, since the capacitor C1 has a laminated structure of a silicon oxide film and a silicon nitride film, and many charge traps occur mainly at the interface, there is an advantage that the specific capacitance is small compared to a single dielectric layer structure. There is.

FIG. 3 is a sectional view of another embodiment structure of the present invention.
Parts equivalent to those in the figures are designated by the same reference numerals.

In this example, the structure of the dielectric layer is a silicon oxide film 11a, a silicon nitride film 12, and a silicon oxide film 14a.
This uses three insulating films stacked in this order.

In this case as well, many traps are formed between the lower silicon oxide film 11a and the silicon nitride film 12, and furthermore between the upper silicon oxide film 14a and the silicon nitride film 12, resulting in an increase in capacitance. becomes possible.

In the above description, the conductivity type of the semiconductor is specified, but the semiconductor is not limited to this, and a reverse conductivity type may be used, and the above structure may be obtained by other manufacturing methods.

Furthermore, although a silicon oxide film and a silicon nitride film were used as the dielectric layer to form the MNO8 structure, a dielectric laminated structure consisting of at least two different types of dielectric layers and forming charge traps at the interface between them is also possible. For example, MAO
It is also possible to have a configuration of 8 (metal, alumina, oxide film, silicon).

According to the present invention, since the upper part of the mesa-shaped region is a capacitor part and the vertical direction of the mesa-shaped region is a transistor part, the area is significantly reduced compared to a conventional planar structure, and thus a large-capacity memory device can be used. becomes possible.

In addition, by configuring the capacitor section as a different type of dielectric layer and having traps at the interface thereof, the capacitance can be increased and the storage time can be extended.

Furthermore, by using the above-mentioned LOCO8 technology, it is possible to flatten the surface of the device, and high speed can be expected due to the reduction in parasitic capacitance.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the order of manufacturing steps for obtaining the device of the present invention, FIG. 2 is a cross-sectional view showing one embodiment of the present invention, and FIG. 3 is a cross-sectional view of another embodiment of the present invention. Figure 4 is similar to Figures 2 and 3.
FIG. 3 is an equivalent circuit diagram of the second device. Explanation of symbols of main parts, 1...Semiconductor substrate, 3
a... Mesa-shaped area, 7... Separation area,
13... Capacitive electrode layer, 11, 14...
Silicon oxide film, 12...Silicon nitride film, 1
5...Control electrode and word line.

Claims (1)

[Scope of Claims] 1. A semiconductor mesa-shaped region of a predetermined conductivity type provided on a semiconductor substrate;
a semiconductor isolation region of opposite conductivity type provided in layers so as to be separated from each other; a control electrode provided via an insulating film so as to cover an exposed surface of the isolation region on a side surface of the mesa-shaped region; At least two dielectric layers of different types deposited on the upper surface of the mesa-shaped region and forming charge traps at the interface thereof; and an electrode layer formed on the upper surface of the dielectric layer. A semiconductor memory device comprising: a semiconductor memory device configured to selectively apply a predetermined control signal to the control electrode to control writing and reading of information into at least the trap via the isolation region. 2. The semiconductor memory device according to claim 1, wherein the dielectric layer is made of a silicon oxide film and a silicon nitride film. 3. The semiconductor memory device according to claim 1, wherein the dielectric layer is formed by laminating a first silicon oxide film, a silicon nitride film, and a second silicon oxide film in this order.