JPS5827714B2 - Jikanjikugosahoseisouchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a time axis error correction device that can effectively correct the time axis error of an information signal (synthesized information signal) having a time axis error, such as a reproduction signal of a magnetic recording and reproducing device. Regarding.

A composite information signal (for example, a composite video signal) consisting of a conventional information signal and a synchronization signal and having a time axis error is supplied to a sampling circuit and sampled using a write clock pulse corresponding to the time axis error of the composite information signal, This sampled composite information signal is sequentially switched and supplied to each storage unit of a storage device (main storage device) consisting of a plurality of storage units, and the writing is stored using a write clock pulse. A time axis error correcting device has been proposed in which the storage contents stored in a unit are sequentially read out using a read clock pulse to obtain a composite information signal with time axis errors corrected.

In such a time axis error correction device, the present invention eliminates the need to provide a special storage device with four axes in the storage capacity of the main memory device, so that when there is a dropout in a synthesized information signal having a time axis error, that portion can be corrected. The purpose of this project is to propose a method that can obtain a high-quality time-base-corrected composite information signal despite the occurrence of dropouts by replacing each unit-length signal with a dropout-free signal that approximates it. It is.

In the present invention, a composite information signal having a time axis error is supplied to a sampling circuit, sampled using a write clock pulse corresponding to the time axis error, and the sampled composite information signal is stored in the main memory. A time axis error that is written and stored using a write clock pulse, and the stored contents written in the main memory are sequentially read out using a read clock pulse to obtain a composite information signal whose time axis error is corrected. The correction device is provided with a dropout storage device that stores all the presence or absence of dropout of the unit length signal of the combined signal having a time axis error, and the main storage device is stored based on the stored contents of the dropout storage device. It is possible to replace a unit-length signal with a dropout among the memory contents stored in multiple units in a unit-length signal with a unit-length signal without a dropout stored in the main memory that is currently being read as an output. Similarly, a circulation loop including a control gate circuit is formed between the input and output sides of the main memory device.

The overall configuration of an example of the time axis error correction device of the present invention will be described below with reference to FIG.

In this example, a reproduction signal reproduced by a rotating magnetic head device of a magnetic recording/reproducing device having a rotating magnetic head device, that is, a modulated composite color video signal, is demodulated to obtain an original composite color video signal, and the composite color video signal is demodulated to obtain the original composite color video signal. This is a case where the time axis error of the signal is corrected.

T denotes a magnetic tape, which is guided and run diagonally around the tape guide drum of the rotating magnetic head device so that, for example, approximately 1800 windings are wound around the corners.

1 is a pair of rotating magnetic heads (the button is shown as one magnetic head in the figure) arranged at an angle of 180°,
In this case, it operates as a reproducing magnetic head.

The reproduced signal from the magnetic field H is supplied to a high frequency amplifier 2 and amplified, and then supplied to a demodulator 3 where it is demodulated, and a composite color video signal is obtained at its output.

In this example, the reproduced signal reproduced by the magnetic head is a mixed output of a frequency-modulated luminance signal and a low-frequency-converted carrier chrominance signal. Frequency demodulation of the frequency modulated luminance signal and reconversion of the low frequency converted carrier color signal to the original carrier color signal,
Both secondary signals are mixed to obtain an original composite color video signal having a frequency interleaved relationship.

This obtained composite color video signal is sent to the buffer amplifier 4.
The signal is supplied to a sample and hold circuit 5 through which it is sampled and held, and its output is supplied to a buffer multiplier 6.

DC feedback is applied from the intensifier 6 to the intensifier 4, so that the intensifier 6 can obtain a DC-regenerated sampled and synthesized color video signal.

The output of the amplifier 6 is then supplied to the main memory 8 through the AD converter 7 and written therein.

The sample and hold circuit 5 is supplied with a write clock pulse as a summing pulse, which varies in accordance with the time axis variation of the composite color video signal obtained from the demodulator 3, to be supplied to the storage device 8.

This is a circuit that generates a 15-bit write clock pulse, and the frequency of this clock pulse is 7 with a parallel wave number of 15 and 75.
It is selected to be approximately an odd multiple of the main half frequency so as to have a frequency interleaving relationship with KHz.

Furthermore, since the time axis error of the composite color video signal is detected as the time axis error of its burst signal, the frequency of this clock pulse is equal to the color subcarrier frequency 3.58 ME
(Selected as an integer multiple of z.

Therefore, in this example, the frequency of this write clock pulse is selected to be 10.74 MHz so as to satisfy the equality condition.

The composite color video signal from the amplifier 4 is supplied to a burst separation circuit 13 and a synchronization separation circuit 14 to separate the burst signal and horizontal and vertical synchronization signals, respectively, and these signals are supplied to a write clock pulse generation circuit 15. , where a write clock pulse as described above is generated based on these signals.

The phase of this write clock pulse is corrected so that the pulse with the negative frequency matches the phase of the beginning of each burst signal obtained every horizontal period, and the phase of the write clock pulse is corrected so that the pulse with the negative frequency coincides with the beginning part of the burst signal obtained every horizontal period, and at The period between is the frequency 1 mentioned above.
The pulse is maintained at 0.74 MHz.

This write clock pulse is then applied to the sample and hold circuit 5. The signal is supplied to the A-D converter 7 and the main storage device 8.

The above-mentioned A/D converter 7 is a circuit that converts the sampled composite color video signal output from the amplifier 6 into, for example, an 8-bit 2-command signal.

The main storage device 8 consists of a plurality of sets (three or more sets are preferable), in this example four sets of storage units 26 to 29, and the output from the A-D converter 7 is switched to the secondary storage units 26 to 29. The stored contents are written and stored using the above-mentioned write clock pulse, and the stored contents are written using a read clock pulse that has the same frequency as the write clock pulse and is created taking into account the time axis fluctuation. It is designed to be read out.

Each of the storage units 26 to 29 stores the 8-bit binary encoded sampled composite color video signal in units of lines, except for part (or all) of the horizontal blanking section.

That is, as shown in FIG. 2, for example, within the horizontal blanking interval BPh of the composite color video signal, the horizontal synchronizing signal sh
(IH-α) time in the interval excluding the α time (for example, 4 μs) between one point t, (t i /, t 2// ) and one point t2 (t2', t i') on the back porch is stored in each storage unit 26 to 29 line by line.

In the same figure, Se is a video signal and sb is a burst signal.

Each storage unit 26 to 29 is a digital memory such as a shift register, a random access memory, or an analog memory such as a capacitor memory, CCD, or BBD.
In this case, the A-D converter 7 is unnecessary).

FIG. 3 shows the writing and reading states for each of the storage units 26 to 29, and each time interval (2).

In step 2......■, writing WR and reading RD are performed sequentially as shown in the figure, and one line of the sampled composite color video signal is written to one set of each storage unit 26 to 29. 1H-4 minutes are written and stored.

For example, when writing is being performed in the storage unit 26, reading is being performed from the storage unit 28 at the same time, so that every other storage unit is cyclically directed to each of the storage units 26 to 29, one of which is in the writing state at the same time. , the other is in a read state.

In this main storage device 8, if there is a dropout in the reproduced signal from the rotary magnetic head 1 for each line, the sampled composite color video signal of that line, which has been written and stored in a certain storage unit, is transferred to another line. This is replaced with a sampled composite color video signal, which will be discussed later.

When writing and storing the IH portion of one line of the sampled composite color video signal in each storage unit 26 to 29, at the above-mentioned write clock pulse frequency of 10. In this example, IH-α (α-4μs) of one line must be stored.
Since the minutes are written and memorized, each memory corner 26 to 29
It is sufficient to write and store data for address 640, and stop writing during time α.

18 supplies write clock pulses and read clock pulses to the main memory device 8, and each memory unit 26 to 2.
This is a control circuit for controlling the replacement of written contents when there is a dropout in the selectivity for writing and reading of 9.

The output of the control circuit 18 is supplied to the drive circuit 17, whereby the main memory device 8 is controlled as described above.

16 supplies each output of the write clock pulse generation circuit 15 and the synchronization separation circuit 14, extracts one pulse of the write clock pulses having a specific phase relationship such as a composite color video signal, and uses this as the write start pulse. This is a pulse extraction circuit that supplies the control circuit 18.

Reference numeral 20 denotes a read clock pulse generation circuit, which is controlled by a synchronization signal generation circuit (another reference synchronization signal generation circuit), and determines horizontal and vertical synchronization signals, local subcarrier signals, and the read start point in the main storage device 8. A local subcarrier signal is supplied from the circuit (circuit that generates a read start pulse, etc.) 21, and a velocity error signal (a velocity error memory described later) is supplied based on the time axis error detected by the burst signal of the composite color video signal. Device 2
4) to generate a 10.74 MHz read clock pulse.

23 is a velocity error hold circuit that holds the velocity error signal detected for each IH from the write clock pulse generation circuit 15 for IH-α time of one line; the output of this circuit 23 and the output from the control circuit 18 is supplied to the velocity-error hold circuit 24.

The velocity-error storage device 24 has four sets of analog storage units (for example, capacitor memories) corresponding to the number of storage units in the main storage device 8, respectively.
Velocity errors in the stored contents of the respective storage units 26-29 are stored, and the stored outputs are supplied to the read clock pulse generation circuit 20 as described above.

When a certain storage unit of the main storage device 8 is being read, this storage device 24 corresponding to that storage unit
10.74 M storage units are simultaneously read out, and the velocity-error signal thereof is supplied to the read clock pulse generation circuit 20.
A read clock pulse is generated by phase modulating the Hz clock signal and is supplied to the control circuit 18.

In this case, the window (time axis variation correction range) in one line is I2+α, as can be seen from FIG.

This is a dropout detection device that detects whether or not there is a dropout in the reproduced signal from the 12rIi rotating magnetic head 1 for each line of the composite color video signal and outputs it as a digital signal.

Reference numeral 19' denotes a dropout storage device, which has four sets of storage units corresponding to the number of sets of storage units in the main storage device 8. It stores whether or not there is a dropout in the storage contents of each storage unit, and the detection output of the dropout detection circuit 12 and the control output of the control circuit 18 described above are supplied to this, and the output of this storage device 19 is Control circuit 1
8.

Then, in the control circuit 18, if there is a dropout in the sampled composite color video signal of a certain line written in the storage unit of the main storage device 8, the dropout in the other storage unit is detected prior to reading. If the button is pressed to replace the sampled and synthesized color video signal of another line with similar signal content and there is no dropout, and the button is pressed at the time of readout, the signal without dropout can be read out from each storage unit of the main storage device 8. That's what I do.

Now, the read output of the main memory device 8 is the buffer memory device 9.
supplied to

This buffer storage device 9 is for controlling the timing of supplying data to the DA converter 10, and is controlled from the 8-bit 1st address memory.

The output from this buffer storage device 9 is sent to a D-A converter 10.
and is converted into a sampled analog signal.

Similarly, both the buffer storage device 9 and the DA converter 10 are controlled by a read clock pulse from a read clock pulse generating circuit 20.

Then, by supplying the output of the D-A converter 10 to the processor 11, the signal missing part that was not written and stored in the main storage device 8 for each line of the composite color video signal is transferred to the synchronization signal generation circuit 21. This is supplemented by horizontal and vertical synchronization and burst signals.

In this way, a composite color video signal with time axis errors corrected is obtained at the output terminal 22.

Next, with reference to FIG. 4 and subsequent figures, the specific configuration of a part of the time axis error correction device shown in FIG. 1 will be explained together with its operation. and explain.

C1 is supplied with a write clock pulse from the write clock pulse generation circuit 15 and a write start pulse from the pulse extraction circuit 16 synchronized with this clock pulse, and after this start pulse arrives, it counts clock pulses from the count value O. This is a counter that starts counting and stops counting when the count reaches 640.

Also, this counter c1 is at high voltage +l Hl+ during counting.
, and outputs a low voltage Q L I+ when stopped.

The output of this counter C1 is supplied to the drive circuit 17 as a write command signal.

That is, when the output of the counter C1 is a high voltage "H", writing to the main memory device 8 is being performed.

Ml is a monostable multivibrator (hereinafter simply referred to as monomulti), which generates a pulse when the output of the counter C1 changes from a high voltage "H'" to a low voltage +4 L I+, that is, when writing is completed. , and supplies its output to counter C2.

C2 is a 2-bit counter that counts the pulses generated by the monomulti M, and outputs the counting result as a 2-bit binary code W.

The output of the counter C2 is supplied to the 1 drive circuit 17 as a signal specifying the number ADD-W of the storage unit to be written, and the storage unit to be written to is determined by the difference.

Fl is a flip-flop circuit with a dropout.

, it is set by the output of the dropout detection device 12 and reset by the output of the monomulti M2 triggered by the falling edge of the output pulse of the monomulti M1.

The contents of this flip-flop circuit F1 are stored in the main memory 8.
Immediately after writing to, switches 5t-15° 5W-18, 5W-19 are activated for a predetermined period (
(approximately 1 μs) By switching to the terminal a side, the output pulse of the monomulti M1 causes the output pulse of the monomulti M1 to write to the storage unit of the dropout storage device 19 having the same number as the storage unit that completed the instruction writing of the main storage device 8. .

C3 is supplied with a read clock pulse from the read clock pulse generation circuit 20 and a read start pulse from the synchronization signal generation circuit 21' synchronized with this clock pulse, and after the start pulse arrives, it starts counting and calculates the counted value. It is a counter that stops counting when it reaches 640,
High voltage ++H” during counting, low voltage tj L 1 when stopped
Outputs 1.

This output is supplied to the drive circuit 17 as a read command signal.

In other words, the output of counter C3 is a high voltage! 1 When the signal is HI+, reading from the main storage device 8 is being performed.

M5 is a monomulti, and the output of counter C3 is high voltage t.
When the voltage changes from l HI+ to low voltage 41 L 11, that is, when reading is completed, a pulse is generated and the counter C4
is supplied to.

This is a 2-bit counter that counts the pulses generated by the C4 harmonic multi-M, and outputs the counting result as a 2-bit binary code R.

CMP-2 is a digital comparator, to which the outputs W and R of the counters C2 and C4 mentioned above are supplied, and when the writing is completed, the button is pressed and both outputs W and R are compared. In order to prevent the following two states from occurring: 1) and 2) (reading is being performed in the same storage unit of the main memory 8) and a W in R+ (the next storage unit to be read is in the process of being written), the counter is set by the comparison output. c4 is controlled.

A, and A2 are 2-bit adders, and when the output R of counter C4 is applied to them, they add +1 and -1, respectively.
are added to obtain the respective addition outputs R+1°R-1.

CMP-1 is a digital comparator, and the output W of counter C2
and the output R1 of adder A2 are supplied and compared, and if they match, a high voltage tl H'' is output, and if they do not match, a low voltage +1 L I+ is output.

F2 is a comparator CM immediately after completion of reading from the storage unit of the main storage device 8 by the output pulse of the monomulti M5.
This is a flip-flop circuit that stores the state of the comparison output of P-1.

The output of flip-flop circuit F2 is high voltage ff”H’
`` indicates the possibility that new data will be written to the storage unit that has just been read while the next storage unit of the main storage device 8 is being read.

When writing is performed on the flip-flop circuit F2, since C4 is also counting J pulses, the number of the storage unit of the main storage device 8 where writing has been completed becomes R1.

That is, since writing and reading from one storage unit must not be performed at the same time, the switch 5W17 is switched to the fixed contact a side.

When the flip-flop circuit F2 is at a low voltage +4 LI+, this switch 5W-17 is switched to the fixed contact side.

In this way, with switch 5W-17, adder A. Each output R+1 of A2. Either R-1 is selected.

The output of this switch 5W17 is assumed to be K. Mono multi M
The output pulse of No. 5 is supplied to the monomulti M6 and delayed for a predetermined time, thereby triggering the monomulti M7.

During this time, the output of monomulti M8 is low voltage +1 LI
+, thereby the switch 5W22 is switched to the fixed contact a side, and the output R of the counter C4 is read out (R at this time is the number of the storage unit of the main storage device 8 that should normally be read out).

The output R of this counter C4 is stored in the dropout storage device 1.
9 to read out whether the storage unit numbered R in the main memory 8 contains a dropout or not, and the result is supplied to the flip-flop circuit F3 and stored as the output pulse of the monomulti M7. .

When the storage in the flip-flop circuit F3 is completed, the output pulse of the monomulti M7 changes the monomulti M8 to 1.
IJ is turned on, thereby switching switch 5W-22 to the fixed contact side.

The output of the switch 5W-22 is also supplied to the dropout storage device 19, which reads out whether or not the storage unit numbered K in the main storage device 8 includes a dropout, and uses the pulse of the monomulti M1o to read out the result. It is stored in flip-flop circuit F4.

Is the output of flip-flop circuit F3 low voltage? L L I
+, that is, when there is no dropout in the storage unit numbered R, switch 5W-20, switch 5W-
21 is switched to the fixed contact a side, R is selected as the storage unit number ADI)-R to be read, and K is selected as the storage unit candidate number ADD-OW to be rewritten.

On the other hand, flip-flop circuit F2. F3. The output of F4 is supplied to the logic circuit LG, and the flip-flop circuit F
If the output of F2 is high voltage IT HI+ and at the same time the output of flip-flop circuit F4 is high voltage, logic circuit LG
outputs a high voltage +THI+ and supplies a command signal to the drive circuit 17 to rewrite the storage unit numbered K with the output of the storage unit numbered R, but the flip-flop circuits F2. At least one of the outputs of F4 is low voltage +1 L I
When it is +, rewriting is prohibited.

When the output of the flip-flop circuit F3 is a high voltage un++, that is, when there is a dropout in the storage unit numbered R, the switches 5W-20 and 5W21 are switched to the fixed contact side, and the storage unit numbered as the storage unit to be read is switched to the fixed contact side. K is selected, and the storage unit numbered R is selected as the storage unit candidate number ADD-0W to be rewritten.

Then, the logic circuit LG instructs the drive circuit 1γ to rewrite the contents of the storage unit numbered R with the contents of the storage unit numbered K only when the output of the flip-flop circuit F2゜F4 is simultaneously at a low voltage IT L I+. do.

Then, when any one of the outputs of the flip-flop circuits F2 and F4 is at a high voltage ++HII, a command is given to the drive circuit 17 to prohibit rewriting.

In this way, when reading from each storage unit of the main storage device 8 is completed, the next number to be read is determined based on the relative positional relationship between the number of the storage unit currently being written and the number of the storage unit that has just been read. In addition to R's storage unit,
A storage unit that selects the previous or next storage unit (storage unit numbered R-1 or R+), collates the contents of the corresponding dropout storage device 19, and reads out the next storage unit from the selected two storage units. Determine the number ADDR and also select other storage units as necessary.
Dropout is compensated for by pressing the button with the contents of the storage unit numbered ADD-R.

Also, when the output of the logic circuit LG is a high voltage ++H'',
Switch 5W-16 is made, and during this time switch 5W
Since -15, SW-, 18, and 5W-19 are switched to the fixed contact side, the memory unit of l-" o tube-out storage device 19 corresponding to the number ADD-OW obtained by switch 5W-20 I am writing the contents of the file using the output of MonoMulti M4.

In addition, since the monomulti M4 is triggered by the read start pulse, the writing of the dropout storage device 19.
This is performed immediately after starting to rewrite the storage unit numbered ADD-OW.

FIG. 5 shows waveforms at various parts of the control circuit 18 described above, and the operation of the control circuit 18 shown in FIG. 4 will be further explained.

FIG. 5A shows the waveform of the composite color video signal, and the same figure shows the waveform of the write start pulse.

This start pulse starts counter C1,
The counter C1 outputs a waveform as shown in FIG.

This output is a write command signal.

The figure shows the output pulses of the monomulti M1, and these output pulses are counted by the counter C2, and the waveform of the output W is shown in the figure E.

Figure F shows an example of the waveform of the output of the dropout detection device 2.

This dropout detection output is the flip-flop circuit F.
1 and temporarily stored, and written to the dropout detection device 19 by the output pulse of the monomulti M1 (D in FIG. 5), this flip-flop circuit F1 is set by the output of the monomulti M2. .

The waveform of the output of this flip-flop circuit F1 is shown in Figure G.
Shown below.

Figure R shows the waveform of the contents of the storage unit of the dropout storage device 19 in which the output of the flip-flop circuit F1 is written.

Furthermore, H in the same figure shows the waveform of the readout star pulse, FIG. 1 shows the waveform of the readout command signal which is the output of the counter C3, and J in the same figure
The waveform of the output of monomulti M5 is shown in K of the same figure.
, that is, the waveform of number R is shown.

The same figure shows the waveform of the output of the monomulti M7, and from this output, the output of the dropout storage device 19 corresponding to number R is read out and stored in the flip-flop circuit F3.

Figure P shows the waveform of the output of the flip-flop circuit F3.

Figure M shows the waveform of the output of the monomulti M8, and this output switches the switch 5W-2 to switch the readout storage unit of the dropout storage device 19 to the numbered one, and the dropout record 'I' is then changed. The output of the device 19 is read into the flip-flop circuit F4 using the output pulse of the monomulti M1o.

N in the same figure shows the output waveform of the monomulti M1o, and Q in the same figure
2 shows the output waveform of flip-flop circuit F4.

Next, the dropout storage device 19 will be explained with reference to FIG.

57, 58, 59 and 60, the dropout detection device 1 corresponds to each storage unit 26 to 29 of the main storage device 8.
2 is a storage unit (consisting of flip-flop circuits) that stores each dropout based on the output from 2.

The second storage units 26 to 29 are numbered O to 3, and the storage units 57 to 60 are correspondingly numbered O to 3.
Attach.

The write pulse from the control circuit 18 is sent to the gate circuits 63 to 6.
6 to each storage unit 57 to 60, and also supplies a signal specifying the write number from the control circuit 18 to a decoder 61 for decoding, and controls each gate circuit 63 to 66 with the decoded output. I try to do that.

The output of each storage unit 57 to 60 is controlled by a switch Sw'.
o, sw'-1, sw--2, and 8W'-3, and the output thereof is supplied to the control circuit 18.

A signal specifying the storage unit to be read from the control circuit 18 is supplied to the decoder 62 and decoded, and the decoded output controls the switches sw'-o to sw'3.

Next, referring to FIG. 7, main memory device 8 and drive circuit 17
Let's take a look back and explain.

Reference numerals 26 to 29 are four sets of storage units constituting the main storage shown in FIG.

30, 31, and 32 are 2-bit decoders, respectively, which convert signals from the control circuit 18 specifying numbers ADD-W, ADD-R, and ADDOW of storage units to be written, read, and rewritten into numbers 0 to 3, respectively. are doing.

The decoder 30 receives signals 0 and 1 specifying the number ADD-W.
, 2.3, and at each output switch 5t-1,
Switch 5W-2, 5W-3, and 5W-4 to the fixed terminal a side.

According to this number ADDW, the output from the AD converter 7 is distributed to any of the storage units 26 to 29 numbered 0 to 3.

Further, the output of this decoder 36 is a write command signal from the control circuit 18, which divides the write clock pulse gated by the gate circuit 3γ into one of the gate circuits 33 to 36, and outputs it to the OR circuit 38 to 41 to the storage unit of the number ADD-W to be written, and the writing and storage are performed.

Similarly, the decoder 31 is supplied with a signal specifying the number ADD-R, and converts this into an output of 0.1, 2°3 [-1] Makes the switches SWi to 5Wi2 with each output.

That is, in accordance with the signal specifying the number ADD-R, one of the storage units 26 to 29 is connected to the output terminal, that is, to the buffer storage device 9, and each output of the decoder 31 is connected to the gate circuit via the OR circuits 46 to 49. 42 to 45 as a gate signal, and the read clock pulse controlled by the read command signal in the gate circuit 54 is further passed through the OR circuits 38 to 41 to the above number ADD.
-R is used to read out the contents of the selected storage unit by this read clock pulse to the storage unit, and the contents are returned to the input side and circulated to hold the contents.

Also, the signal specifying the number ADD-OW is also output to the decoder 32 as 0. However, when the output of the logic circuit LG of the control circuit 18 is a low voltage +1LD, that is, when rewriting is prohibited, the gate circuits 50 to
Its output is blocked at 53.

When the output of logic circuit LG is high voltage +1 HIT,
That is, when rewriting is commanded, the output of the decoder 32 is sent to the switches 5W-5 to 5W via the gate circuits 50 to 53.
-8, and switches only the switch connected to the storage unit specified by the signal specifying the number ADDOW to the fixed terminal a side.

At the same time, the gate circuits 42 to 4 send a read clock pulse controlled by a read command signal to the memory unit.
5 and further supplied to the storage unit via OR circuits 38-41.

At this time, the read output is supplied to the 3C storage unit designated by this number ADD-OW by lightly operating the switches 5W-S to 5W-8, and this is written in accordance with the read tarock pulse.

FIG. 8 shows waveforms of various parts of the circuit of FIG. 7 during recording.

That is, FIG. 8A shows the waveform of the composite color video signal, and FIG. 8B shows the waveform of the Vc write command signal.

CF of the same figure shows the waveforms of the output terminals numbered 0, 1, and 2.3 of the decoder 30, respectively.

Figures G to H in the same figure show the waveforms of the outputs of the gate circuits 33 to 36.

Further, FIG. 9 shows waveforms of various parts of the circuit of FIG. 7, and the operation of the circuit of FIG. 7 will be further explained.

9A to 9D show the waveforms of the output of the decoder 302, and FIG. 9E shows the write command signal.

If a dropout occurs between B and C at this time, then the contents of the storage unit 27 with number 1 include 1 dropout.

F in the same figure shows the waveform of the read command signal, G-■ in the same figure shows the waveform of each output of the decoder 31, and J-M in the same figure shows the waveform of each output of the decoder 32.

N in the figure shows the waveform of the output of the logic circuit LG.

The states of the clock pulses supplied to the respective clock pulse input terminals of the memory units 26 to 29 numbered O to 3 by the signals representing the respective waveforms in A to N of the figure are all shown in the figure 0 to RK.

The contents between time AB are read between time a and b.

Since there is a dropout between time B and C, time b
-c, the storage unit 26 with number O is read out once again to output the contents between time A and B, and at the same time, this is written into the storage unit 27 with number 1.

The contents between time CD are read out during time C-4.

The same operation continues below. In this way, the l-'' o tube-out between time B and C is erased and does not appear in the output.

Next, regarding the write clock pulse generation circuit 15, the 10th
This will be explained with reference to the figures.

84 is 2 of the color subcarrier signal frequency 3.58 MHz.
This is a voltage-controlled variable oscillator that oscillates at a frequency N times higher (for example, N3).

This oscillation output is supplied to a 455.times.N counter 80, which extracts and outputs one pulse for each 455.times.N input clock.

On the other hand, the reproduced horizontal synchronization signal from the synchronization separation circuit 14 triggers the monomulti 75 at its timing edge, and the content of the counter 80 at that point is sent to the launch circuit 7 by its pulse output.
7, and the digital comparator 16 determines whether the phase difference between the output pulse of the counter 80 and the reproduced horizontal synchronizing signal is within a predetermined range.

When the voltage is within a predetermined range, the comparator 76 outputs a high voltage +
1 H41 is output, the switch 82 is closed, and the switch 79 is opened via the inverter circuit 78.

In this state, the horizontal synchronizing signal is delayed by the monomulti 73 by the time necessary to operate the switches 5W-79° and 5W-82, converted into a narrow pulse by the monomulti 74, and supplied to the phase detector 81.

The phase detector 81 detects the phase difference between the output pulse of the counter 80 and the output pulse of the monomulti 74, and supplies the detected phase difference to the holding circuit 83 through the switch 82.

A holding circuit 83 continues to hold the previous detection error signal before the next new detection error signal is input.

Since the output of the holding circuit 83 controls the oscillation frequency of the oscillator 84, the signal of a constant frequency continues to be oscillated until the phase detector 81 performs the next phase detection.

Furthermore, when there is jumping such as skew in the composite color video signal, the amount of jumping exceeds a certain number.

Then, the output of the comparator 76 is opened at the low voltage 41L 116 terminal 5Wi2.

This prevents the operation of the oscillator 84 from being disturbed even if the phase comparator 81 outputs an abnormally large output due to jumping.

Further, the output of the comparator 76 makes the switch γ9, and the counter 80 is reset by the output of the monomulti 74.

In this way, if the next horizontal synchronizing signal does not include jumping, the next output pulse of the counter 80 and the next output pulse of the monomulti 74 will almost match, and the oscillator 8
The oscillation loop for 4 returns to normal operation.

During this time, the holding circuit 83 keeps the output constant, so the oscillation frequency of the oscillator 84 is kept constant.

In this way, the oscillation loop composed of the circuit 8oT-sl-82-8344-80 will not be disturbed even if there is skew or jumping.

In this way, the oscillation output, which is stable even against input disturbances, is frequency-downgraded by the flip-flop circuit 85 to a phase shifter 86.
is supplied to

86 is for controlling the phase of the color subcarrier signal obtained by lowering the output of the circuit 85 to a frequency of 1/N (-1) to match the phase of the burst signal output from the burst separation circuit 13. It is a phase shifter.

The output of this phase shifter 86 is used as a write clock pulse by the control circuit 18, sample and hold circuit 5. A-D converter 7
etc. will be supplied.

87 sets the output of the phase shifter 86 to 1. /N (=-) is an N-ary counter, and 88 is the counter 87.
This is a phase comparator that compares the phase of the output of the burst signal and the burst signal.

The output of the phase comparator 88 is read out as a velocity error and controls the phase shifter 86.

90 is a circuit for detecting a specific portion of the burst signal; 91 is a monomultiplier that generates a pulse for reading the phase difference of the specific portion into the velocity-error hold circuit 23; and 92
For example, after the velocity error is read into the velocity error hold circuit 23, the monomultiply determines the period for controlling the phase shifter 86, and the switch 89 is closed during this period to form a closed loop with the circuits 8617-881916. The phases of the burst signal and the output of the counter 87 are made to match.

Next, when the switch 89 is opened, the phase shifter 86 maintains the phase shift amount at that time until the switch 89 is closed.

This write pulse generating circuit 15 has the same phase in the burst signal portion, that is, it follows jitter quickly, and constitutes an oscillator with a very stable oscillation frequency, and also detects velocity errors. .

Next, regarding FIG. 11, velocity-error storage device 24
12, and its operation will be explained with reference to FIG.

FIG. 12A shows the waveform of the composite color video signal, A-D
indicates the time point at which the burst signal is generated, and B in the figure shows the waveform of the write command signal, in which the composite color video signal is written into the storage unit of the main memory 8 only during the period of the high voltage uH11.

C-F in the same figure show the storage unit to which the data is written.

G in the figure shows an example of the output of the phase comparator 88 in FIG.

H in the figure shows the output of the velocity-error hold circuit 23 for the burst signal in G in the figure.

Here, considering that the output of the phase comparator 88 in FIG. 10 should be zero immediately after the burst signal at time A, the waveform output as shown in FIG. Correspondingly, the phase error detected at time B is considered to have occurred between time AB as shown in FIG.

That is, although the storage unit number ADD-W1 is shown at time B when the velocity error is detected, it can be seen that this error should belong to the storage unit number O.

In other words, the detected error is the previous number A D D-W
must be stored correspondingly.

Now, 95 in FIG. 11 is an adder which adds -1 to W of the current storage unit number ADD-W to obtain W-1, according to the above-mentioned principle.

97, the output of the adder 95 is supplied to the switch 10.
This is a decoder that selects only one from 0 to 103 and obtains an output for making.

Note that the switches 96 and 116 are always switched to the fixed contact side.

The velocity error held by the hold circuit 23 is supplied to the buffer amplifier 99 via the switch 116, and is then passed through a selected one of the switches 100 to 103 to the memory connected to that switch. is stored in one of the capacitors 104 to 107.

Buffer amplifiers 108 to 111 have sufficiently high input impedance.

On the other hand, when the number ADD-R is determined by the control circuit 18,
This is sent to the decoder 98, and its output is sent to the switch 11.
2 to 115 are controlled to read the velocity error included in the contents of the storage unit corresponding to number ADD-R, and this is supplied to the read clock pulse generation circuit 20.

If this happens, the control circuit 18 can compensate for the dropout by rewriting the contents of another storage unit at the same time as reading.
, the output signal of the logic circuit LG becomes high voltage +1 Hl+, the switch 117 is made, the monomulti 118 is triggered by the read start pulse from the synchronization signal generation circuit 21, and the monomulti 118 is set to a predetermined value. A pulse with a pulse width is generated.

With this pulse, the switch 96 is temporarily switched to the fixed contact a side, the decoder 97 selects the capacitors 104 to 107, which are analog memories corresponding to the number ADD-OW, and makes any of the switches 100 to 103 connected thereto.

Further, the output of the monomulti 118 is simultaneously switched to the fixed contact a side so that the error being read out at that time is written into the capacitor which is the selected analog memory mentioned above.

This is specified by the number ADD-OW to ensure that velocity errors are compensated for even when rewritten data is read.

The read clock pulse generation circuit 20 will be described with reference to FIG.

The velocity error output from the velocity error storage device 24 is supplied to the sawtooth wave generation circuit 120.

This circuit 120 is designed so that the slope of the output waveform is proportional to the input waveform.

Further, the read command signal is inverted by an inverter circuit 121 and reset, that is, the output of the circuit 120 is held at zero when the record/unique unit is not read.

A reference color subcarrier signal is supplied as an original signal from the synchronization signal generation circuit 21, and this serves as a power source for the phase modulator 122, which undergoes phase modulation with the sawtooth wave output from the circuit 120.

The modulated output is given a duty by monomulti 123.
The waveform is shaped to have a frequency of 50, and the band-pass waveform generator 124 extracts only the Nth harmonic that is desired to be used as a readout clock pulse.

In the example, N:=3 and a signal of 10.74 MHz is extracted.

゛The output of the i-wave device 124 is sufficiently amplified by the amplifier 125 and converted into a rectangular wave by the waveform shaping circuit 126.

In this way, the readout clock pulses subjected to addition modulation by the velocity error are directly supplied to the main memory device 8 via the control circuit 18.2 and the drive circuit 17. A composite color video signal with velocity error compensation is obtained from the main memory 8 by supplying it to the A converter 10 .

- Each storage unit of the main storage device 8 mentioned above is approximately one line, but in this case, when an NTSC combined color video signal is generated, the frequency of the Mizuko synchronization signal and the color subcarrier signal is Processing that takes interleaving relationships into consideration becomes necessary.

Therefore, it is also possible to double the storage capacity of each storage unit and store approximately two lines in one storage unit.

In this case, d2, the storage capacity of each storage unit is 1280
640 addresses from the write start pulse, temporarily stop writing -L, continue writing for 640 addresses from the next start pulse, and set counters C2 and C4 to 3 bits as shown in Figure 4. By operating the storage unit using the upper two bits, it is possible to compensate for dropouts using data two lines before or after, without considering frequency interleaving relationships.

According to the above-mentioned time axis error compensation 11 of the present invention, the device includes a do 1 dropout storage device for storing the presence or absence of a dropout of a unit length signal of a composite information signal having a time axis error. Out of the 67 stored contents in the main memory, medium-length signals with dropouts are stored in the main memory based on the stored contents in the storage location.
Kanayama f) and 1-7 can be read out [main 1 in 7; Since we have formed a circulation loop that includes a control loop between the memory devices on the crowd row side, it is possible to maintain the time axis without having to provide a special memory device whose storage capacity is comparable to that of the main memory device. If there is a dropout in the synthesized information signal that has an error, that part is replaced with a signal without dropout that approximates it to a unit-length signal, and high-quality time axis correction can be performed despite the occurrence of dropout. Accordingly, it is possible to obtain a time axis error correction device that can obtain a synthesized information signal.

In the present invention, since dropout compensation is performed on the unit length signal outer can of the composite information signal, a dropout storage device is provided for this unit length signal outer can.

Therefore, it is also possible to replace the outside of the unit-length signal with dropout of the combined information signal with the outside of the unit-length signal, which is limited to one horizontal period before, or one horizontal period apart.

Furthermore, even if it is inconvenient if a pixel from one horizontal period ago is mixed in, dropout compensation can be easily performed, and it is suitable for processing color television signals of the SECAM system and NTSC system, for example.

Furthermore, a shift register type memory can be used as the dropout storage device.

The presence or absence of dropouts of unit-length signals stored in the dropout storage device may be determined for each line or multiple lines stored in one of the storage units constituting the main storage device, or for each line of that storage unit. The data may be stored for one or more lines, regardless of the storage capacity.

The composite information signal to be written and stored in the main memory may not be partially omitted, but may be the entirety.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the same, FIG. 3 is a conceptual diagram, and FIG.
The figure is a block diagram showing the brushstrokes in Figure 1, Figure 5 is a waveform diagram for explanation, Figure 6 is a block diagram showing another part of Figure 1, and Figure 7 is the diagram shown in Figure 1. Figures 8 and 9 are block diagrams showing other parts of the history of the system, waveform diagrams that provide an ingenious explanation, and Figure 10 is a block diagram showing still other parts of Figure 1. FIG. 11 is a block diagram showing still another part of FIG. 1, FIG. 12 is a waveform diagram for explaining the same, and FIG.
This figure is a block diagram showing still another part of FIG. 1. 8 is a main storage device, and 19 is a dropout storage device.

Claims (1)

[Claims] 1. A synthesized information signal having a time axis error is supplied to a sampling circuit, sampled using a write clock pulse corresponding to the time axis error, and the sampled synthesized information signal is stored in the main storage device using the write clock pulse. A time axis error correcting device which uses a main storage device to write and store data, and sequentially reads out the stored contents written in the main memory using a clock pulse to obtain a composite information signal in which a time axis error is corrected. A dropout storage device is provided for storing a detection output of the presence or absence of dropout for each unit length signal of the composite information signal having the time axis error, and the main storage is stored based on the storage contents of the dropout storage device. To replace a unit-length signal with a dropout among the memory contents stored in a plurality of units in the device with a unit-length signal without a dropout written in the main storage device that is being read as a full output. A time axis error correction device characterized in that a circulation loop including a control circuit is formed between the main memory device on the output side so as to enable the correction.