JPS5828745B2 - semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a semiconductor memory device that can easily configure a large capacity semiconductor memory device with high density.

Conventionally, as a semiconductor memory device, as shown in FIGS. 1A and 1B, for example, a circular P-type source (or drain) region 3 disposed in an N-type semiconductor substrate 1 from the main surface 2 side,
An annular P-type drain (or source) region 4 arranged in the substrate 1 so as to surround the region 3 from the main surface 2 side, and a region between the regions 3 and 4 on the main surface 2 of the substrate 1. A MIS field effect transistor configuration has been proposed, which has an annular gate electrode 6 disposed in a region with an insulating layer 5 interposed therebetween.

In such a semiconductor memory device, a voltage is applied between the regions 3 and 4 and the substrate 1 in the opposite direction to the PN junction between them, and the voltage is applied inside the substrate 1 as indicated by reference numeral 7 in FIG. 1B. If a pulse voltage with the electrode 6 side being positive is applied between the substrate 1 and the electrode 6 in a state where a depletion layer is formed in which the depletion layers extending from the regions 3 and 4 are connected, the main surface 2 of the substrate 1 is applied. The distribution of energy E with respect to the distance Z on L2 taken in the direction perpendicular to the main surface from the position below the electrode 3 is obtained as shown by curve 8 in FIG. Since majority carriers accumulate on the surface on the surface 2 side, a pulse voltage is applied between the substrate 1 and the electrode 3 while applying a voltage to form the depletion layer 7 described above between the regions 3 and 4 and the substrate 1. By accumulating majority carriers on the surface of the substrate 1 under the electrode 6, binary information "1" can be written.

Furthermore, after the binary information "1" is written, when the scheduled discharge time elapses, the majority carriers accumulated on the surface of the region under the electrode 6 of the substrate 1 disappear naturally, so that the binary information is written. 11"
disappears naturally and binary information “O” is written, but before the binary information “1” disappears, area 3
and 4, if a power supply is connected through the load so that a current flows in the region between regions 3 and 4 of the substrate 1, the amount of majority carriers accumulated on the surface of the region below the electrode 6 of the substrate 1 is connected to the load. Since a current flows according to the current value, before the written binary information "1" disappears, a power supply is connected between regions 3 and 4 through a load, and the load is connected to the region under the electrode 6 of the substrate 10. By passing a current according to the amount of accumulated majority carriers, binary information is
1" can be read out, and the binary information "0" is generated because the current does not flow through the load when the binary information "1" is read even if a power supply is connected between regions 3 and 4 through the load. This can be read out.

Therefore, according to the configuration of the conventional semiconductor memory device described above in FIG. Therefore, when a large capacity semiconductor memory device is constructed by arranging a large number of such memory devices in a matrix, it is difficult to increase the density of the device.

Therefore, the present invention aims to propose a novel semiconductor memory device free from such drawbacks, which will become clear from the detailed description below.

3A, B, and C show a first embodiment of the present invention, and corresponding parts to those in FIG. 1 are denoted by the same reference numerals. P-type source (or drain) region 3 and drain (or source) region 4 arranged in parallel from the 2 side, and a region on the region between the regions 3 and 4 of the substrate 1 on the main surface 2 of the substrate 1. A region facing both ends in the Y-Y direction, which is different from the X-X direction, connecting the gate electrode 6 disposed through the insulating layer 5 and the regions 3 and 4 of the gate electrode 6 on the main surface 2 of the substrate 1. Other gate electrodes 10 arranged respectively in
and 11, it has one MIS field effect transistor configuration, and other gate electrodes 10 and 11 are arranged at both ends of the gate electrode.

The above is the configuration of the first embodiment of the present invention. According to this configuration, a voltage in the opposite direction is applied between the regions 3 and 4 and the substrate 1 to the PN junction between them. Then, the electrode 6 side is made positive between the electrode 6 and the substrate 1, with the depletion layer extending from regions 3 and 4 connected to each other as shown by reference numerals 13 in FIGS. 3B and 4 being formed in the substrate 1. By applying a pulse voltage that is smaller than the voltage between the electrode 6 and the substrate 1 between each of the electrodes 10 and 11 and the substrate 1, the electrodes on the main surface 2 of the substrate 1 can be applied. 3 Distance 2 on line Lz taken in the direction perpendicular to principal surface 2 from the lower position
The distribution of energy EC is obtained as shown by curve 14 in FIG.
- The distribution of the energy distribution Ec' with respect to the distance y on the Y line is obtained as shown by the curve 15 in FIG. It is.

Therefore, the above-mentioned depletion layer 1 between regions 3 and 4 and the substrate 1
electrodes 6.10 and 1 with a voltage applied forming 4;
1 and the substrate 1 to accumulate majority carriers on the surface of the substrate 1 under the electrode 6, binary information "1" can be written. be.

Moreover, after the binary information "1" is written in this manner, when the scheduled discharge time elapses, the majority carriers accumulated on the surface of the area under the electrode 6 of the substrate 1 disappear naturally, and the binary information is written. '1
" disappears naturally, and binary information rOJ is written.

Furthermore, before the above-mentioned binary information "1" is written and disappears, the area 3 and 4 of the substrate 1 is written between the areas 3 and 4.
If a power source is connected through the load so that a current flows in the area between them, a current flows through the load with a current value corresponding to the amount of majority carriers accumulated on the surface of the area under the electrode 6 of the substrate 1. .

Therefore, before the written binary information "1" disappears, a power supply is connected between areas 3 and 4 through the load, and the board 1 is connected to the load.
Binary information "1" can be read by passing a current corresponding to the amount of majority carriers accumulated in the area under the electrode 6.

Note that the binary information "0" can be read because the current does not flow through the load when the binary information "1" is read even if a power supply is connected between areas 3 and 4 through the load. It is.

Therefore, according to the configuration of the first embodiment of the present invention described above in FIG. This simple structure functions as a storage device, and areas 3 and 4 are configured such that area 3 is surrounded by area 4, as in the case of the conventional device described above in FIG. Therefore, when a large capacity semiconductor memory device is constructed by arranging many of the structures according to the embodiments of the present invention in a matrix, it is necessary to It has the feature that it can be more easily densified than if multiple devices were used in Figure 1.

FIGS. 5A, B, and C show a second embodiment of the present invention, and corresponding parts to those in FIG. The structure is similar to that shown in FIG. 3, except that the gate electrode 6 partially overlaps each of the gate electrodes 10 and 11 with an insulating layer 20 in between.

The above is the configuration of the second embodiment of the present invention. According to this configuration, the detailed explanation is omitted, but it is similar to the case of the first embodiment of the present invention shown in FIG. In addition to exhibiting the function as a memory device, the gate electrode 6 is partially formed with each of the gate electrodes 10 and 11, so that the overall device is different from that of the first embodiment of the present invention. It has the feature of being more compact.

6A, B, and C show a third embodiment of the present invention, and the same reference numerals are given to corresponding parts as in FIG. 5, and detailed explanation thereof is omitted, but the same as described above in FIG. In the structure, N is arranged from the main surface 2 side in the region between regions 3 and 4 of the substrate 1.
It has the same structure as the case shown in FIG. 5 except that it has a half-shaped semiconductor layer 21.

However, in this case, if the semiconductor layer 21 is placed under the gate electrode 6 in the substrate 1, it is not necessary to extend it between the electrodes 10 and 11 as shown in the figure, and it may be extended between the regions 3 and 4. It is.

The above is the configuration of the third embodiment of the present invention. According to this configuration, although detailed explanation is omitted, it has the same features as the embodiment of the present invention shown in FIG. In addition to functioning as a memory device, the presence of the semiconductor layer 21 allows the pulse voltage applied between the electrode 6 and the substrate 1 to be reduced in the case of the second embodiment shown in FIG.

FIG. 7A, B and Cl show a fourth embodiment of the present invention,
Parts corresponding to those in FIG. 6 are given the same reference numerals and detailed explanation thereof is omitted, but in the configuration described above in FIG. It has the same structure as the case shown in FIG. 6 except that it has a P-type semiconductor layer 22 arranged at a position separated from the surface side by a required distance.

However, in this case, if the semiconductor layer 22 is placed under the gate electrode 6 in the substrate 1, there is no need to extend it between the electrodes 10 and 11 as shown in the figure, and there is no need to extend it between the regions 3 and 4. Furthermore, there is no extension connected to the semiconductor layer 21.

The above is the configuration of the fourth embodiment of the present invention, and this configuration has the same features as the embodiment of the present invention shown in FIG. 6, although detailed description thereof will be omitted. In addition to exhibiting the function of a storage device, the presence of the semiconductor layer 22 allows current to easily flow through the regions 3 and 4 when reading binary information written therein, and thus effectively reading binary information. In addition, since the semiconductor layer 21 and the region under the semiconductor layer 21 of the substrate 10 are separated by the semiconductor layer 22, the voltage applied between the substrate 1 and each of the regions 10 and 11 is as shown in FIG. It has characteristics that can be made smaller than in the case of .

The above description has only shown a few embodiments of the present invention, and for example, in the structure described above in FIG.
The structure may be the same as that shown in FIG. 7, except that 1 can be omitted, and various other modifications may be made without departing from the spirit of the invention.

[Brief explanation of the drawing]

1A and 1B are a line plan view and a cross-sectional view showing a conventional semiconductor memory device, FIG. 2 is an energy distribution curve diagram for explaining the device, and FIGS. 3A, B, and C are according to the present invention, respectively. A linear plan view showing a first example of a semiconductor memory device,
4 is an energy distribution curve diagram for explaining the same; FIGS. 5A, B, and C are plan views showing a second embodiment of the semiconductor memory device according to the present invention;
A cross-sectional view and a vertical cross-sectional view, and FIGS. 6A, B, and C are a line plan view, a cross-sectional view, and a vertical cross-sectional view showing the third embodiment of the present invention, and FIGS. 7A, B, and C are a main view. A linear plan view, a cross-sectional view, and a vertical cross-sectional view showing a fourth embodiment of the invention are shown, respectively. In the figure, 1 is a semiconductor substrate, 2 is a main surface, 3 is a source (or drain) region, 4 is a drain (or source) region, 5 is an insulating layer, 6, 10 and 11 are gate electrodes, 13 is a depletion layer,
21 and 22 indicate semiconductor layers, respectively.

Claims (1)

[Claims] 1. A source region and a drain region having a second conductivity type different from the first conductivity type, which are arranged in parallel from the main surface side in a semiconductor substrate having a first conductivity type. and a first gate electrode disposed on the main surface of the semiconductor substrate on the region between the source region and the drain region of the semiconductor substrate with an insulating layer interposed therebetween; A semiconductor memory device comprising second and third gate electrodes disposed in opposing regions, respectively, at both ends of the first gate electrode in a direction different from the direction connecting the source region and the drain region. 2 A source region and a drain region having a second conductivity type different from the first conductivity type, which are arranged in parallel from the main surface side in the semiconductor substrate having the first conductivity type, and a source region and a drain region having a second conductivity type different from the first conductivity type; a first gate electrode disposed on a region between the source region and the drain region of the semiconductor substrate on a main surface with an insulating layer interposed therebetween; and a first gate electrode on the main surface of the semiconductor substrate. second and third gate electrodes disposed in regions facing each other in a direction different from the direction connecting the source region and drain region of the semiconductor substrate, and a region between the source region and the drain region of the semiconductor substrate; A semiconductor memory device comprising: a first semiconductor layer having the tenth conductivity type and having an impurity concentration higher than that of the semiconductor substrate, disposed from the main surface side. 3 A source region and a drain region having a second conductivity type different from the first conductivity type and arranged in parallel from the main surface side in the semiconductor substrate having the first conductivity type, and a source region and a drain region having a second conductivity type different from the first conductivity type, and a first gate electrode disposed on a region between the source region and the drain region of the semiconductor substrate on a main surface with an insulating layer interposed therebetween; and a first gate electrode on the main surface of the semiconductor substrate. second and third gate electrodes disposed in regions facing each other in a direction different from the direction connecting the source region and drain region of the semiconductor substrate, and a region between the source region and the drain region of the semiconductor substrate; and a second semiconductor layer having the second conductivity type arranged at a position separated from the main surface by a predetermined distance. 4 A source region and a drain region having a second conductivity type different from the first conductivity type and arranged in parallel from the main surface side in the semiconductor substrate having the first conductivity type; a first gate electrode disposed on a region between the source region and the drain region of the semiconductor substrate on a main surface with an insulating layer interposed therebetween; and a first gate electrode on the main surface of the semiconductor substrate. second and third gate electrodes disposed in regions facing each other in a direction different from the direction connecting the source region and drain region of the semiconductor substrate, and a region between the source region and the drain region of the semiconductor substrate; a first semiconductor layer having the first conductivity type and having an impurity concentration higher than that of the semiconductor substrate, disposed from the main surface side;
and a second semiconductor layer having the second conductivity type disposed in a region between the source region and the drain region of the semiconductor substrate at a predetermined distance from the main surface side. Semiconductor storage device.