JPS5828783B2 - phase detector - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement of a phase detector for PLL.

As is well known, the PLL is basically composed of a phase detector PD, a low-pass filter LPF, a voltage controlled oscillator VCO, etc. as shown in FIG. The phase difference of the feedback signal ■ is expressed as PD, L
By applying negative feedback to the entire PF and vCO system, the function is always kept at zero (lock-in).

A circuit shown in FIG. 2 is generally employed as such a phase detector for PLL.

The operation of this circuit is to input a reference signal to the input terminal R, and
A feedback signal is input to the terminal.

The two output terminals U and D are normally in the “1”H state,
One of the two becomes O"L for a time equal to the phase error between the two.

For example, when the reference signal is ahead of the feedback signal in phase, the output terminal U becomes "0" L for a time equal to the phase difference.

Moreover, in the opposite case, D becomes "0"'L.

By the way, there are two detection modes for the phase error by using one of the two manual forces as a reference.

This will be explained below using the operation waveform diagram (time chart) of each part shown in FIG.

In FIG. 3, R...P5 indicates the signal waveform of each part in FIG.
Mode 1 is a mode in which input R is set to (L) level and indicates that input R is ahead of input V only from time t3 to t4.
shall be.

On the other hand, mode 2 is a mode in which the output signal is at the (L) level only between time t4 and time t7, and the input R lags behind the input (2) only between time t4 and t7.

First, mode 1 will be explained.

At time to, flip-flop (hereinafter referred to as FF) FF6
．． 7 is also reset, and both outputs U and D are set to (2) level.

Now, focusing on the input R, when R reaches the m level at time t1, both inputs to the gate 1 become the (H) level, and the output O becomes the CL) level.

When 0 becomes (L) level, FF6 is set and this output O
to wholesale level.

Next, at time t3, when this human power R reaches the CL) level, O is set to the (A) level.

Therefore, the input of gate 2 is 0. Both O are at m level,
Set output U to (L) level.

On the other hand, if we focus on the human power V, at time t2, when it reaches (H level), we set it to (L) level, set FF7, and set O to (H level).
) level.

Next, at time t4, this human power ■ becomes D level jXs
■ Become.

Both O20s are set to (I() level).

At this time t4, since both 0 and 0 are at H level, all four inputs of gate 3 are at (2) level, so O is (
(g) level.

This resets FFs 6 and 7, and immediately changes O20 from the (H) level to the (I) level. , 3, and 4 are all at (H) level.

That is, focusing on the output U, a detection operation is performed in which the (L) level is output only between times t3 and 14, and the input R is ahead of the input V by the period between times t3 and t4.

The above is the operation in mode 1.

Next, mode 2 will be explained.

At time to, FF7 is set and O is at level 2), while F
F6 is in the reset state and O is at (to) level.

In such a state, the output U becomes level ((2)) because O is L.

On the other hand, looking at the output, input ■ is at (L) level, so O is at (8) level, and FF7 is set and O is at (H) level.
) level, and the input to gate 4 is at (H) level, so the output is at (L) level.

This state is shown by the dotted line in FIG.

At time t1, input R becomes m level, and O becomes (L
) level, set FF6, and set O to (H) level.

At time t2:, the input ■ becomes the wholesale level.

However, because the output D is at the CL) level, Q) becomes the (H) level, which is a problem.

Next, at time t3, input R becomes CL) level, and O
from the CL) level to the (H) level.

At this time, O20, 6, and
level, reset both FF6 and 7, and 02()
to (D level).

Therefore, one of the inputs (game)2, 3°4 is connected to (I
, ) level, both outputs U and D are set to (H) level.

At this point, the input v is (rubel, so Kate 5
Both inputs go to (H) level, (→ goes to (L) level, FF7 is set, and O goes to (H) level.

That is, if we focus on FF7, it once enters the reset state at time t3, but is immediately set again.

Next, at time t4, when the input ■ becomes (L) level, O is changed to ().
(To set the level, both inputs @tQ of gate 4 are at (H) level and the output is at (L) level.

This state is the same as at time to.

Therefore, the same operation as described above occurs at time t 5 t t
5? t 7, and the resulting output is shown in Figure 3.
As shown by the dotted line, the level between times t4 and t7 is output.

This indicates that the input R is higher than the input ■ from time t4 to t7.

That is, the operation in mode 2 is performed. Then, as a condition for performing mode 2, at time to, both input R and V are (L)
As described above, only FF7 is in the set state and FF6 is in the reset state.

Similarly, even when the human power R and V are at (L) level, only FF6 is set, and FF7 is reset, there is a mode 2 in which detection is performed at an angle of 180° or more.

That is, the conditions for generating mode 2 are that the input R,
This occurs when V is at the (L) level and either one of the FFs 6 and 7 is in the cassette or the other is in the reset state.

In this way, the detection mode (mode 1) assumes that the quantity reference signal R from time t3 to t4 is ahead of the feedback signal ■ (mode 1), and the case where the reference signal R from time t4 to t7 is delayed in phase from the feedback signal ■. There is a detection mode (mode 2) to

The former (mode 1) detects the phase difference between R and ■ below 180°, and the latter (mode 2) detects the phase difference above 1800°.

Therefore, PLL using a phase detector with such a function
For example, when applied to drive a resonance tracking circuit system RC that requires varying the operating frequency in accordance with the resonance frequency of the load (output) as shown in Fig. 4, the input signal R of the PD
On the other hand, the feedback signal V has both wave numbers until lock-in,
Cannot vary independently with respect to phase error.

This will be explained using FIG. 4.

First, in FIG. 4, INV is a transistor inverter and switching transistor Q1. Q2 and its base drive circuit BK, output transformer TI, RLC series resonant load R
CT is a current transformer for detecting load (RO) current.

H8 is a waveform shaping circuit that converts the output sine wave of the CT into a sine wave by detecting that the sine wave crosses zero.

Here, current ■ is changed to transistor Q by signal ■ from PLL.
1. If the load voltage ■ generated in the output transformer T1 when Q2 is alternately turned ON and 0FFL is the current flowing through the resonant load (RO), the input signal ■ of the PLL and the above output voltage ■ are the same timing signal, and, It can be said that the human power signal R and the load current I are the same timing signal.

Also, in the relationship between the load (output) voltage ■ and the load current ■, if the resonant frequency of the resonant load (RO) is rRO and the frequency of V is fV, then if fV and fRO are equal, the load voltage ■ and the load current I The phase error of is zero, and fV is fRO
If fV is higher than fRO, then ■ will be in phase lagging behind ■, and conversely, if fV is lower than fRO, I will be in phase leading than ■.

And the phase difference between the load voltage (■) and load current (■) is maximum ±90
0, that is, within 180°.

This also indicates that the phase difference between the input signal R of the PLL and the feedback signal (2) is within ±90° at maximum.

However, as mentioned above, in the conventional phase detector PD, there are a detection mode (mode 1) with a phase error within 180° and a detection mode (mode 2) with a phase error of 1800 degrees or more, so in such a resonance tracking circuit system, the above mode is 2 is detected, the PLL outputs the input signal R and the feedback signal ■
The phase error not only does not become zero (lock-in) but also increases and becomes uncontrollable.

In view of the above points, the present invention provides a PL suitable for controlling a resonance tracking circuit system, which eliminates the above-mentioned drawbacks at once by prohibiting detection of mode 2 and always detecting only mode 1.
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention provides a phase detector for L, and will be described in detail below with reference to the drawings.

FIG. 5 is a circuit diagram showing one embodiment of the present invention.

In FIG. 5, COP is a comparison circuit for the input signals R and V based on the rising edge of one of the two human input signals R and V, and is a flip-flop 6 (hereinafter referred to as F F' 6).

) is formed from the (L) level to the (H) level at the trigger terminal T.
) When a rising signal to level 20 arrives, the data at the input of FF6 is read and the result is output to O20.

LC is a logic circuit that takes the logic of the output signal O2O of the comparison circuit COP and the input signals R and V, and in the gate 10, R is "L".
゛.

j4 L to D only when ■ is “H” and P6 is “H”
”, and at gate 11, R is “H”i and V is “L”
, P7 outputs "L" to U only when P7 is "H".

It is composed of such games) 10 and 11.

The phase detector PD of the present invention is configured above.

Next, the operation will be explained using the waveform diagram of each part shown in FIG.

First, assuming that the input signals R and ■ have the relationships shown in FIG. 6 a, b, c, and d, in FIGS. The phase is advanced, and conversely, in Figure cd, if the input signal (2) is at (H) level at the rise of the input signal R, this indicates that the phase of R is delayed.

Therefore, in steady state, the output terminals U and D are at (H) level, that is, "
The operation will be described assuming that the output signal O of the FF6 is at the (I() level) and the output signal O of the FF6 is at the (L) level.

First, at time to, the input signal R rises, and since the input signal V at this time is at the (L) level, the FF6 is triggered at the rising edge and outputs the output signal (the stored contents of the input signal ■, that is, the signal at the (L) level). The output signal of O is ■
Flip to level.

Therefore, the gate input of AND gate 11 is
(H) 7 v (L) level and sends a (L) level signal to output U.

At this time, the gate input of the AND gate 10 is @(L),
R (H), VCL) and sends out a (H) level signal at the output.

Also, when the input signal 2 reaches the (4) level at time t1, the gate inputs 0 (H) and R of the ant gate 11
(H).

V is published and becomes a bell, and the output U becomes (n level).

(FIG. 6e) On the other hand, the output of the AND gate 10 still maintains the (H) level because the gate input is O and R (H2) (2).

Therefore, for example, when the operation is started at time t2/, in the conventional example, an error of 180 degrees or more is detected (mode 2) at the output terminal from time t3 to t6, but in the present invention, at time t2' FF6 is not triggered during the period from t5 to t5, and is triggered (set) at the rising edge of the input signal R at time t4, so that an error less than 1800 can always be detected (mode 1).

On the other hand, input signals R and ■ have the relationship shown in FIG. 6 C2d, and when the operation starts at time to, F
Since the output O of F6 holds the stored contents of the input signal (2), that is, the (H) level, the output signal P7 is held at the (L) level.

And the gate input of the ant gate 10 is R(H),
Q ri 吋).

At the V(H) level, the output is at the (I() level, and the ant gate 11 is P7(Ll, R(E-1), V
At (E() level, the output U is at (marked level).

This state continues until time t3, and at time t3, the input signal ■ becomes (8 or when R becomes (L) level, the gate input cover RCL of the AND gate 10), v(H),
Sends out a 0 (H) level toner output D2 (L) level signal.

On the other hand, the output U of the gate 11 is still at the (n level).

Then, at time t4, when the input signal R becomes (H) level, the output level becomes () level.

(FIG. 6f) Therefore, it is detected that the input signal ■ is ahead of R in phase.

In the above embodiment, an example was explained in which one FF was used in the comparator circuit COP and the rising edge of one of the input signals was used as a reference, but as shown in FIG. The comparison signal may be sent based on the rising edge of the input signal, or the falling edge of one or both of the input signals may be used.

As is clear from the above explanation, according to the present invention, generation of a phase error signal of 1800 or more is prohibited (stopped) in the phase detector for PLL, and detection of less than 1800 is always performed. It has great practical effects, such as being suitable for driving an inverter circuit in a tracking system.

[Brief explanation of drawings]

Figure 1 is a basic configuration diagram of a PLL, Figures 2 and 3 are a conventional phase detector and its operational waveform diagrams, Figure 4 is a side view of the resonance tracking circuit, and Figures 5 and 6 are the invention of the present invention. FIG. 7 is a circuit diagram of an embodiment of the phase detector and a diagram of operation waveforms (time charts) of each part thereof, and FIG. 7 is a diagram of another embodiment of the present invention. In the figure, PI) is a phase detector, L2, 3, 4゜5 is a Nant gate circuit, R is a reference input signal, ■ is a feedback input signal, U and D are output signals, 6 and 7 are flip-flop circuits,
COP is a comparison circuit, Lc is a logic circuit, 10 and 11 are AND gate circuits, ■ is a load voltage, and ■ is a load current.

Claims (1)

[Claims] 1. In a PLL phase detector configured to detect a phase error between two human-powered signals with the same period from one of the two output signals, when one of the two human-powered signals rises or falls, the other one detects the level of the input signal, and performs logic between the detected signal and the two human input signals, thereby prohibiting detection of a phase error larger than 180° in each of the two human input signals, and only detecting a phase error of less than 180°. A phase detector characterized by: