JPS5851693B2 - phase detector - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement of a phase detector for PLL.

As is well known, a PLL basically consists of a phase detector (PD), a low pass filter (LPF), a voltage controlled oscillator (VCO), etc. as shown in FIG.
The phase difference between the two human input signals D, ie, the reference signal R and the feedback signal ■, is the PD.

It has a function to always maintain zero (lock-in) by applying negative feedback to the entire LPF and VCO system.

A circuit shown in FIG. 2 is generally employed as such a phase detector for PLL.

The operation of this circuit is to input a reference signal to the input terminal R, and
A feedback signal is input to the terminal.

The two output terminals U and D are normally in the state of "1" (goods), and one of them becomes "0" for a time equal to the phase error between the two outputs.
″(becomes υ.

For example, when the reference signal leads the feedback signal in phase, the output terminal U becomes "O" (L) for a time equal to the phase difference.

In the opposite case, D becomes "0" (Ll).

By the way, there are two detection modes for the phase error by using one of the two manual forces as a reference.

This will be explained below using the operation waveform diagram (time chart) of each part shown in FIG.

In FIG. 3, R...P5 indicates the signal waveform of each part in FIG. 2. First, between time t3 and t4 in FIG.
I, ) level, and mode 1 indicates that the input R is ahead of the input ■ only from time t3 to t4.

On the other hand, mode 2 is a mode in which the output signal is at the (L) level only between time t4 and time t7, and the input R lags behind the input (2) only between time t4 and t7.

First, mode 1 will be explained.

At time to, flip-flop (hereinafter referred to as FF) FF6
, 7 are reset together, and the outputs U and D are both at the (goods) level.

Now, focusing on the input R, when R becomes 0 level at time t1, both inputs of gate 1 become 0 level, and the output O
becomes (I,) level.

(When 9 becomes (L) level, FF6 is set and this output ■ becomes (c) level.

Next, at time t3, this human power R reaches (G) level)
(C) level.

Therefore, the inputs () and 2 of the gate 2 are both at the m level, and the output U is at the (L) level.

On the other hand, if we focus on human power ■, when it reaches 0 level at time t2, the chestnut is set to (D level, FF7 is set, and () is set to 0 level.

Next, at time t4, when this human power ■ reaches the (L) level, C is set to (2).

Then both Genshizuka and @ are brought to level 0. At this time t4, since both ψ) and [phase] are at H level, all four inputs of gate 3 are at 0 level, so O is set at (D level).

This resets FF6 and 7, and immediately brings the chestnut from level 0 to level (υ).

Therefore, in order to set at least one of the inputs of gates 2, 3, and 4 to the normal level, all outputs of gate 2.3.4 become 0 level.

In other words, if we focus on the output (c), only from time t3 to t4 (g level is output, and input R changes from input ■ to time t3
A detection operation with an advanced phase is performed for a period from t4 to t4.

The above is the operation in mode 1.

Next, mode 2 will be explained.

At time to, FF7 is set and Q9 is at the (2) level, while FF6 is in the reset state (9 is the peak) level.

In such a state, the output U becomes 0 level because ■ is L.

On the other hand, looking at the output, the input ■ is at the (L) level, so Φ is at the (2) level, and when FF7 is set, ψ) is at the □□□ level, and the input of gate 4 is at the (2) level. Since it is at the (goods) level, the output is at the (L) level.

This state is shown by the dotted line in FIG.

At time t1, input R becomes 0 level, and ■ becomes (L
) level, set FF6, and set O to (b) level.

At time t2, the input ■ becomes the (c) level.

However, since the output is at the (L) level, the output remains at the 0 level.

Next, at time t3, the input R becomes the (L) level, and (
) from the (I,) level to the 0 level.

At this time, ○L0.0.0 both go to (C) level, all inputs to gate 3 go to 0 level, ■ goes to (L) level, FF6.7 is reset, and ■ and () go to (L) level.
) level.

Therefore, since any one of the inputs of gates 2, 3, and 4 is set to (L) level, outputs U and D are both set to 0 level.

At this point, input ■ is at ()-level, so both inputs of gate 5 are at (c) level, and G) is at (L) level.
) level, sets FF7 to the set state, and sets Q) to the old level.

That is, if we focus on FF7, it once enters the reset state at time t3, but is immediately set again.

Next, at time t4, the input V becomes (L) level, and (
2) In order to make the input level of gate 4 (C) (both 0 level and the output level (υ level).

This state is the same as at time to.

Therefore, the same operation as described above occurs at time t5+t6
．． ↓7, and as a result, the output is from time t4 to t7 (the υ level is output as shown by the dotted line in FIG. 3).

This indicates that the input R is higher than the input ■ from time t4 to t7.

That is, the operation in mode 2 is performed.

Then, as a condition for performing mode 2, input R at time to.
2) Both are at the (L) level, and only FF7 is in the set state and FF6 is in the reset state.

Similarly, there is a mode 2 in which detection of 180° or more is performed even when the inputs R and V are at low levels, only FF6 is set, and FF7 is reset.

That is, the conditions for generating mode 2 are that the input R,
This occurs when V is at the (L) level and either one of FF6.7 is set or the other is in the reset state.

In this way, the detection mode (mode 1) assumes that the quantity reference signal R from time t3 to t4 is ahead of the feedback signal ■ (mode 1), and the quantity reference signal R from time t4 to t7 is delayed in phase from the feedback signal ■. There is a detection mode (mode 2) in which

The former (mode 1) detects the phase difference between R and ■ below 180°, and the latter (mode 2) detects the phase difference above 180°.

Therefore, PLL using a phase detector with such a function
For example, when applied to drive a resonance tracking circuit system RC that requires varying the operating frequency in accordance with the resonance frequency of the load (output) as shown in Fig. 4, the input signal R of the PD
On the other hand, the feedback signal ■ has both wave numbers until lock-in,
Cannot vary independently with respect to phase error.

This will be explained using FIG. 4. First, in FIG. 4, INV is a transistor inverter and switching transistor Q1. Consists of Q2 and its base drive circuit BK, output transformer T1, RLC series resonant load RO, etc.
Further, CT is a current transformer for detecting load (RO) current.

H8 is a waveform shaping circuit that detects when the sine wave output from the CT crosses zero and converts it into a square wave.

Now, the transistor Q is changed by the signal V from the PLL.
1. Output drance T when Q2 is turned ON and OFF alternately
If the load voltage generated in 1 and ■ are the currents flowing through the resonant load (RO), then the PLL input signal ■ and the above output voltage are the same timing signal, and the human power signal R and the load current ■ are also the same timing signal. You can say that.

Also, in the relationship between the load (output) voltage and the load current i, the resonant frequency of the resonant load (RO) is fRo, ? Let fV be the frequency of
If fV is higher than fRQ, i will be in phase lagging behind V, and conversely, if fV is lower than fRQ, ■ will be in phase leading than ■.

The phase difference between the load voltage V and the load current i is ±90 at maximum.
0, that is, within 180°.

This also indicates that the phase difference between the input signal R of the PLL and the feedback signal (2) is within ±90° at maximum.

However, as mentioned above, in the conventional phase detector PD, there are a detection mode (mode 1) with a phase error within 180° and a detection mode (mode 2) with a phase error of 1800 degrees or more, so in such a resonance tracking circuit system, the above mode is 2 is detected, the PLL outputs the input signal R and the feedback signal ■
The phase error not only does not become zero (lock-in) but also increases and becomes uncontrollable.

In view of the above points, the present invention provides a PL suitable for controlling a resonance tracking circuit system, which eliminates the above-mentioned drawbacks at once by prohibiting detection of mode 2 and always detecting only mode 1.
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention provides a phase detector for L, and will be described in detail below with reference to the drawings.

FIG. 5 is a circuit diagram showing an embodiment of the present invention, and the same reference numerals as in the conventional example indicate equivalent parts.

In the figure, 1 to 5 are NAND (NOT, AND) gate circuits, and the gate circuits 1 and 5 are single-handed signals (R or
) and -output signals (U or D) as gate inputs form a pair of Nant gate circuits (first NAD), and 2 and 4 are later-described flip-flop circuits (hereinafter referred to as FF).

) A pair of Nant gate circuits (second NAD) are formed which have the output signal O or O of 6 or 7 and the output signal [phase] or [phase] of the Nant gate circuit 1 or 5 as gate inputs.

3 is a Nant gate circuit (3rd NAD) which receives the above-mentioned signals [phase] to [phase] as gate input; 6.7 is a pair of FFs whose reset terminals R are commonly connected; and a set terminal S is connected to the above-mentioned Nant gate circuit. LFF connected to the output side of 1 or 5
6.7 are set when the signal (low or ψ) is at the (seasonal level).

Next, R8T is a reset circuit that uses input signals R and ■ as gate inputs.
) A NOTORN0T in which the gate circuit 8, the output signal [phase] of the gate circuit, and the output signal 0 of the third NAD gate circuit 3 are used as gate inputs, and the output signal O is connected to the common reset terminal of the FFs 6 and 7. The gate circuit 9 applies a signal O of the (L) level to the reset terminal R when either of the former output signals (S or 2) is at the D level to hold the FFs 6.7 in the reset state.

The phase detector PD of the present invention is configured above.

Next, the operation will be explained using the time chart shown in FIG.

First, in FIG. 5, when FF 6 and FF 7 are reset, the output signal O2 [phase] is at (T) level.

Also FF6. The set terminal S of No. 7 sets and closes FFs 6 and 7 upon the arrival of the n L n level signal, and the above signal 0.
Set 0 to 0 level.

It is assumed that the Nant gates 1 to 5 send out an output signal of (L) when all gate inputs are (c).

Also, in Nando Not Game 18, gate human power R and V are both (
When , the output signal O is set to (L) level, and when either the gate input [phase] or [phase] is (L), the output signal O is set to (seasonal level).

Here, the phases of input signals R and ■ are as shown in FIG. 6a. Assuming the relationship shown in b, the output signals of gates 8 and 9 [phase]
, ■ can be illustrated as shown in FIG. 6C and d.

That is, when the output O of gate 9 is at (L) level, FF6,
7 and enters the initial state, the period O from time t1 to t2 becomes (L), and FF6 and FF7 are reset. When the input signal R reaches the (goods) level at time t2, FF6 is set, and the above-mentioned Perform mode 1 phase error detection.

By the way, the conventional detector has a mode 2 in which the output is set to the (1,) level between time t1 and t4 in Fig. 6, indicating that the input R is higher than the input ■ from time t1 to t4. As mentioned in the explanation of mode 2 in the conventional circuit example, the conditions for mode 2 are when both inputs R and V are at the (L) level, and when one of FFs 6 and 7 is in the set state. Occur.

However, in the circuit of the present invention, both inputs R and V are (L
) level, FFs 6 and 7 are reset, which deviates from the conditions of mode 2, and only phase detection within 180° of mode 1 is performed.

Also, due to noise during operation, FF67 is turned off at time t4.
enters the reset state, FF7 enters the set state at time t4+△t4, and even if the above-mentioned mode 2 detection operation starts, FF7 returns to the reset state during the period from time t5 to t6, so from time t6 Set FF6 again and enter mode 1
can be detected.

In addition, in Fig. 5, gate 8°9 is used to reset FF6.7 when both R and ■ are at L9 level, but it is detected that both R and ■ are at Ln level. As a method of resetting FF6 and 7 using the output, in Figure 5, FF6 and 7 are FFs that have only set and reset functions.
However, by using a flip-flop such as a D type or JK type that has one trigger terminal for FF67, and adding an output that detects the n L n level of both R and ■ to the trigger one terminal, FF6 There is a way to reset .7.

In addition, by using the fall or rise of the output that detects that both R and ■ are at the "L" level, FF6 and
From this embodiment, it is easy to infer how to reset the output, input the rise, fall, level, etc. of this output to a monomulti, and use the output to reset the FF6.7.

As is clear from the above explanation, according to the present invention, generation of a phase error signal of 180° or more is prohibited (stopped) in the PLL phase detector, and detection of less than 180° is always performed. It has great practical effects, such as being suitable for driving an inverter circuit of a resonance tracking system.

[Brief explanation of drawings]

Figure 1 is a basic configuration diagram of a PLL, Figures 2 and 3 are a conventional phase detector and its operational waveform diagrams, Figure 4 is a side view of the resonance tracking circuit, and Figures 5 and 6 are the invention of the present invention. FIG. 2 is an embodiment circuit diagram of a phase detector and an operation waveform (time chart) diagram of each part thereof. In the figure, PD is a phase detector, 1, 2, 3° 4.5 is a Nant gate circuit, R is a reference input signal, ■ is a feedback input signal, U and D are output signals, 6 and 7 are flip-flop circuits, Below R8 is the reset circuit, 8 is NOT AND NOT
9 is a gate circuit, 9 is a N0TORNOT gate circuit, 9 is a load voltage, and i is a load current.

Claims (1)

[Claims] A PLL configured to detect a phase error in a human input signal and output the phase difference from one of two output terminals.
In a phase detector for
a pair of flip-flop circuits whose gate circuits (first) and reset terminals are commonly connected, and whose set terminals are respectively connected to the output (side) of the Nant gate circuit; and the Nant gate circuit (first) and the flip-flop A pair of Nant's gate circuits (second) which use respective output signals of the circuits as gates (inputs), and a reset circuit whose respective output signals of the Nant's gate circuit (first) and the flip-flop circuit serve as gates (inputs), and whose outputs are used as gates (inputs). When the Nant gate circuit (third) that sends out the signal and the human input signal are both low level (L),
or a reset circuit connected to reset the flip-flop in either state when the output signal of the Nant gate circuit (third) is at a low level (L), the phase of each of the two output signals being greater than 180°; A NAND NOT (NOT) system uses 22 human input signals as a gate input to a phase detector, which is characterized by prohibiting error detection and only detecting angles less than 180°.
AND N0T) gate circuit, the output signal of the gate circuit, and the output signal of the Nant gate circuit (third) as gates (inputs).
2. The phase detector according to claim 1, further comprising a reset circuit having a N0T) gate and its output signal connected to a reset terminal of a flip-flop.