JPS5829025B2 - Data transfer control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transfer control circuit having a CRC control circuit that performs a cyclic redundancy check of transmitted and received data during data transmission.

Data transmission is I-l-1DLc (Hi) 1 level
DataLink Control) procedure, synchronization basic transmission procedure (SYN synchronization procedure), etc.
A parity check is also performed as a simple method.

In the case of HDLC, the signal format is fixed to flag F1 address A1 control C, data D1 to Dn1 check bits FC8I, Fe12, flag F,
Control is easy because all blocks A, C, etc. between the flags can be treated as data and CRC can be performed, and the usual method is to provide a CRC calculation register and control this using a program. The above method is sufficient and there is no problem of putting too much burden on the program.

However, in the SYN synchronization procedure, the signal format is SY
N, SYN, STX, D1~DieSYN, D
j to Dn, ETX, BCC, and BCC, and in addition to the normal synchronization character SYN, for example, 5TX (Star
Control characters such as t of Text) are also CRC
Since the data is processed first, if the CRC is controlled by hardware alone, data must be identified on the hardware side, making the circuit complex.

For this reason, conventionally, CRC control was not performed on the hardware side, and all control was performed by a program.

However, since CRC calculations are usually performed bit-serial using exclusive OR, controlling such calculations places a heavy burden on the program.

The present invention aims to reduce the burden on a program when performing CRC on a signal in a format in which blocks not considered as data such as SYN synchronization procedures are interspersed.
Its characteristic feature is that it has a processing unit and an adapter connected to the line, and the adapter transfers data between the processing unit and the line, and also transfers predetermined data among the data transferred. In a data transfer control circuit that performs calculations to create a check code for the data, the adapter has a data register in which the transferred data is stored, and a data register that performs the calculations on the stored data. a calculation means and a control bit set by the processing unit;
The adapter is provided with a control register that indicates whether or not the calculation means is activated, and the adapter performs an inspection when the data register (the internal control register of the data to be transferred to the line to be stored or the processing unit is sent) is sent. The point is to have the code calculated.

This will be explained in detail below with reference to the drawings.

FIG. 1 shows a part of a normal data transmission system, in which 3 is a common bus connected to a central processing unit 2, a main memory 4,
, line control channel 5, etc. are connected.

A plurality of lines 6 are connected to the main channel 5 via a bus 7 and a line adapter 1.

An integrated circuit for transmission control is placed at the connection part of the line adapter 1 with the line 6, and the inventor has developed this integrated circuit (LSI) with various functions.

This LSI is capable of controlling transmission of the SYN synchronization procedure in addition to the HDLC procedure, and has the configuration shown in FIG.

Although not limited to, the present invention is applicable to CRC of some LSI.
Suitable for use in control.

FIG. 3 shows an embodiment of the present invention, and corresponds to a part of the LSI shown in FIG.

Write data WD from the LA bus 7 in FIG. 1 is written in parallel to the write data register 10 selected by the register address RA, and then transferred to the CRC calculation register 11 and P/S register 12 on the transmitting side. .

The write data WD that has entered the P/S (parallel series conversion) register 12 is sequentially output from the register in a serial format and sent out through the line 16.

The write data WD is written in a serial format to the CRC calculation register, where the CRC calculation is performed, but as mentioned above, within one frame signal there are blocks to be subjected to this calculation (l block is, for example, 1 bar, Since there are blocks (consisting of 8 bits) and blocks that are not subject to calculations, it is necessary to distinguish between these blocks, which complicates the program.

Therefore, in the present invention, in addition to the CRC calculation register, a register 15 for control (SCCNT) is provided, and each time data or a character other than data is written to the write data register 10, it is determined whether the character is data or not. 5C information indicating whether it is a character
Write to CNT register 154.

This writing is also performed using the register address line 13 and write data line 14.

The 5CCNT register 15 has 2 bits, and when the contents are in the left column of Table 1, the corresponding instruction in the right column is given to the CRC calculation register 11.

In the above table, × in classification number (1) indicates that any binary number 0.1 may be used.

The CRC calculation register 11 creates a CRC for the SYN synchronization procedure according to the contents of the 5CCNT register 15.
This will be explained with reference to the time chart of FIG.

Figure 4a shows the data format of the SYN synchronization procedure, where two consecutive synchronization characters SYN are placed at the beginning of the frame, followed by STX, then data D1 to D4, synchronization characters SYN, etc. ...Data Dn and ETX (End of Text) follow.

The gb indicates writing to the write data register 10, and data from the second SYN to ETX is written by the program, and is sent out via the P/S register 12 and line 16 as described above.

Figure C shows the contents to be written to the 5CCNT register 15 using classification numbers (0), (1), and (2), Figure d shows the timing at which data can be sent (cent or receive buffer empty), and Figure e shows the timing at which data can be sent (cent or receive buffer empty). Shows the processing of the program.

The CRC calculation register 11 stores the write data SY in FIG. 4a.
Since only the data portion DI +D2 +......Dn of N, SYN, ......ETX is subject to calculation, the 5CCNT register 15 is as shown in Fig. 4C.
Second 5YN (5YN indicating start of frame) as in
; is specified by the classification number (0) to "not add", and ST
For X, "initialization" is instructed using the classification number (2).

Initialization means presetting the CRC calculation register 11 to all O's or all 1's.

When the data D1 is written to the write data register 10 at the timing shown in FIG. 4, the content to be written to the 5CCNT register 15 is the classification number (1), and the CRC calculation register 11 is instructed to "add".

Data D2 is subsequently written to register 10 in the same manner.
．． D3......Dn is added (SYN as a clock is not written to the register 11), and the final data Dn (Dn is the final means that two addresses ADD1 and ADD2 are added to the register 10). Let me have it,
When writing data D - D, A1
[1-1 The address signal should be ADD 1, and when writing data Dn, the address signal should be ADD 2 (this can be identified).

Of course, when the addition of ETX is completed, the calculation result BCC is sent to the P/S register 12.

The P/S register 12 thus converts the output 5YN-ETX of the register 10 and the calculation results BCC and B'CC of the CRC calculation register 11 into the serial format shown in FIG.

The same thing is done independently on the receiving side.

That is, the received data from the receiving line 17 in FIG.
After being converted into parallel data in the register 18, the data is transferred to the read data register 19.

The format of the read data RD written to the register 19 is also the same as that shown in FIG. Receiving side RCC
No instructions can be given to the NT register 20.

The RCCNT register 20 also has 2 bits, and when its contents are in the left column of Table 2, the corresponding instruction in the right column is given to the CRC calculation register 21 for checking.

In the above table, classification numbers (0) to (2) are the same as those on the sending side, but the classification number (3) "Notification of check results" is unique to the receiving side, and is the CRC calculation register 21 for all data. When the addition is completed, the reception control circuit 22 sends the calculation result ANS to the program to resend the notification signal (in the case of an error), request the next signal transmission (in the case of error 4., (in the case of error), etc.).

In addition, the P/S register 12 and S/S register in FIG.
The P register 18 is the line S-P conversion control unit 3 in FIG.
(Includes 5CCNT registers 15 and RC
CNT register 20 is defined as a control bit of line control register 31 in FIG.

The write data register 10 and the read data register 19 correspond to the transmit data register 32 and the receive register 33 in FIG. 2, respectively, and the CRC calculation register 21 on the receiving side corresponds to the CRC check circuit 34 in FIG.

Register address RA is the decoded output of decoder 35.

Also, notifications (interrupts) to the program are made by the interrupt control circuit 3.
This is done by the output IRQ of 6.

According to the above-described cyclic redundancy check control circuit of the present invention, the CRC calculation and its control are performed by hardware for both transmission and reception.

Therefore, since the program only needs to carry out simple control that gives the instructions in Tables 1 and 2, there is an advantage that the burden of CRC in the SYN synchronization procedure is significantly reduced.

Furthermore, even in the case of the HDLC procedure, all that is required is to set the bit to be calculated, and whether it is a SYN synchronization procedure or
A highly versatile device that can be used regardless of the DLC procedure is realized.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram showing an example of a terminal device, FIG. 2 is a block diagram of an LSI used as the line adapter in FIG. 1, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. 4 is a time chart of CRC creation. In the figure, 1 is a line adapter, 15.20 is a CRC control register, and 11.21 is a CRC calculation register.

Claims (1)

[Claims] 1. It has a processing unit and an adapter connected to the line, and the adapter transfers data between the processing unit and the line, and calculates predetermined data from the transferred data. In a data transfer control circuit that creates a test code, the adapter has a data register in which the data to be transferred is stored, a calculation means for performing the calculation, and a data register to store the data to be transferred. The adapter is provided with a control register in which a control bit is set by the data register to indicate whether or not the arithmetic means is activated. A data transfer control circuit that is characterized by causing an inspection code to be calculated when set.