JPS5829536B2 - I/O Interface Control Method - Google Patents

Description

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to a channel and an I10 interface control method for an I10 input/output device.

In general, in the case of a read operation (see Figure 2), when the read data is ready in Ilo, the service I
n (SRVIN) signal is set and BUSI
Set the read data in N.

When 5RVIN is detected on the channel side, the read data is latched and the 5service Out signal (5RV
OUT).

When 5RVOUT is detected on the I10 side, 5RVIN and B
Resets the data on USIN and when the next data is ready, Data In (DATIN) and BUSI
Place the following data on N:

The subsequent sequence uses Da t instead of 5RVOUT.
a Out (DATOUT) is set and 5R
The process proceeds exactly the same as for VIN.

Td above the sequence is the cable delay between the channel and I10, Tch is the 5RV-IN- at the channel.
Processing time for SRVOUT set or DATA I + M set, TIO is 5RVO at Ilo
UT-+DATIN set or DATOUT→5R
This is the processing time up to VIN.

Also, in the case of write operation, RvOUT or DATA
When T is set, the channel sets the write data in BUSOUT and transfers it to Ilo, and other than that, it is controlled in exactly the same way as in the case of a read.

In the case of a conventional I10 interface, the data transfer rate C of the interface becomes larger as the data transfer rate of Ilo becomes larger, and as a result, it becomes necessary to reduce Td.
Cable length restrictions become stricter.

The object of the present invention is to make the data transfer rate of a high speed I10 interface independent of the cable length, while maintaining compatibility with conventional interfaces.

To provide an I10 interface control method.

This invention enables synchronous data transfer control for the I10 interface, and allows the interface cable length to be determined independently of the data transfer rate.

The reason why the conventional I10 interface control method has a limit on the interface cable length is that Ilo is 5RVIN
After sending /DATIN, 5RVOUT is sent from the channel.
Wait for the response of /DATOUT and then
This is to reset the

So, Ilo's 5RVIN/DATI channel
After N is entered, the channel will be 5RVIN/
If there is a guarantee that DATIN can be processed, the 5RVIN/DATIN signal is set to Ilo for a certain period of time or more.
As long as it holds, Ilo will be 5RV from the channel.
OUT/DATI without waiting for OUT
N is reset, and a new data transfer request signal 5RVIN
/DATIN can be set.

Such a method of data transfer by sending out pulsed 5RVIN/DATIN signals by Ilo under the guarantee of channel processing time will hereinafter be referred to as synchronous data transfer.

In the case of this synchronous data transfer, Ilo can control the reset of SRIN/DATIN without waiting for a 5RVOUT/DATOUTCD response from the channel, so
This means that there is no longer any restriction on the length of the interface cable.

Therefore, in a situation where the processing time from the channel can be guaranteed, synchronous data transfer is advantageous.

The present invention makes it possible to control Ilo using either the conventional method or the synchronous method, and also makes it possible to arbitrarily select either one.

FIG. 1 shows the circuit at Ilo, where flip-flop 7' (FF) is a flip-flop that selects whether to use control according to the conventional 110 interface or a synchronous data transfer method, with output III I It selecting synchronous data transfer and output If II selecting the conventional method.

Which method to use is 5ETSYN-P and 5ET
It is controlled by the ASYN-P signal, and the source of the signal may be the decoded output of a command or a signal that is preset.

If FF1 is reset, 5
When RVOUT falls (SRVOUT-N="1"),
F2 is set and read data is ready at Ilo (DATAREADY-p=!Ilo
I), the AND gate 8 and the OR gate 9 operate, and SRVIN is set (SRVIN-P=III I
f) is carried out.

The 5RVIN is held, and the SRV
When SRVOUT is input from the channel for IN (SRVOUT-N="O"), the inverter 3 and the AND gate 5 operate to reset the FF2, and the S
RVIN is reset.

In this manner, conventional I10 interface control is realized.

If FFI is set, 5R from the channel
When VOUT falls, FF2 is set.

After that, the read data is ready at I10 (DA
When TAREADY-P="1") and an appropriate input pulse is input from TP-P, the AND gate 7 and OR gate 9 operate to set the pulse as SRVIN.

The output of the AND gate is FF after a certain time with a suitable delay, not depending on the 5RVOUT from the channel, by the delay line 4 and the AND gate 6.
2 is automatically reset.

This realizes synchronous data transfer.
The logic relating to -DATAOUT can be realized by the same logic as that shown in FIG.

Control of BUSOUT and BUSIN can be achieved by the same control in both the conventional method and the synchronous data transfer method.

That is, for a read operation, Ilo is 5RVIN
Or while DATIN is set, BUSIN
Data is set on the upper side and latched in the channel on the rising edge of 5RVIN or DATIN.

For write operations, data is set to BUSOUT during the 5RVOUT or DATOUT set period in the channel, and 5RVOUT/DATOUT is set in Ilo.
Data is received on the rising edge of T.

This invention realizes synchronous data transfer over an I10 interface, thereby eliminating the cable length limitation of high-speed I10 and enabling conventional VO interface control.

[Brief description of the drawings]

FIG. 1 shows an embodiment of the present invention, and FIG. 2 shows a conventional control sequence.
It's 4 delay lines.

Claims (1)

[Claims] In an I10 interface having a transmission line for a data transfer request signal sent from an input/output device to a channel, a transmission line for a data transfer request acceptance signal which is sent from the channel to the input/output device and is set in response to the setting of the data transfer request signal and reset in response to a reset, a data bus from the input/output device to the channel along which data is transferred when the data transfer request signal is sent out when data is transferred from the input/output device to the channel, and a data bus from the channel to the input/output device along which data is transferred when the data transfer request acceptance signal is sent out when data is transferred from the channel to the input/output device, the I10 interface comprises: means for designating an I10' interface operation mode; first means for sending out the data transfer request signal until a data transfer request acceptance signal from the channel in response to the request signal is returned;
an I10 interface control system comprising: second means for transmitting a pulsed data transfer request signal by resetting the data transfer request signal for that request signal after transmitting the data transfer request signal; means for selecting one of the first means or second means in accordance with the designation of the designation means; and means for applying an output of one of the first means or second means selected by the selection means to a transmission line for the data transfer request signal.