JPS5829625B2 - Manufacturing method for MIS integrated circuit device - Google Patents

Description

Detailed Description of the Invention The present invention relates to a metal-insulator-semiconductor (hereinafter referred to as MIS or MOS) constructed of a polycrystalline Si (silicon) layer as a resistor.
The present invention relates to a method of manufacturing an integrated circuit device (referred to as ``MIS''), particularly a method of manufacturing an MIS integrated circuit device in which the polycrystalline silicon layer has a variable resistance.

In complementary MO8) transistor circuits for watches, it has been considered to insert a high resistance between the input section and the output section for the purpose of stabilizing oscillation in the oscillation circuit section.

When this resistor is incorporated into a semiconductor integrated circuit (IC) chip, it has been considered to use it as a polycrystalline Si thin film resistor.

It was found that when a bias voltage was applied to the chip substrate of such an IC, the resistance value of the thin film resistor changed.
It has become clear that the material can also be used as a variable resistor for semiconductor ICs.

As mentioned above, when attempting to construct a thin film resistor or a variable resistor using polycrystalline Si, it is necessary to introduce impurities into polycrystalline Si in order to control the resistance value to a desired value. .

As a result of the study, it was found that it is appropriate to introduce impurities into polycrystalline Si by impurity ion implantation.

Therefore, the main object of the present invention is to provide a novel method for manufacturing an MIS integrated circuit device including a thin film resistor made of polycrystalline Si.

Another object of the present invention is to provide a method for manufacturing the MIS integrated circuit device, which is easy to manufacture.

Further objects of the invention will become apparent from the following description and drawings.

In order to achieve the above object, the gist of the present invention is to provide a method for manufacturing a MIS integrated circuit device having an insulated gate field effect transistor and a resistor [i. forming a second insulating film to serve as a gate insulating film of a type field effect transistor, forming a polycrystalline silicon layer on the first and second insulating films, and forming the resistor on the first insulating film. a step of forming a second polycrystalline silicon layer that will become a gate electrode of the insulated gate field effect transistor on the first polycrystalline silicon layer that will become a body and a second polycrystalline silicon layer that will become a gate electrode of the insulated gate field effect transistor; A step of implanting impurity ions into the crystalline silicon layer to give a predetermined resistance value; and a step of covering the portion of the first polycrystalline silicon layer to be the resistor with an impurity-introducing mask film and masking the polycrystalline silicon layer. By simultaneously introducing impurities into a portion not covered by the film and a predetermined portion of the main surface of the semiconductor substrate, the resistance of the polycrystalline silicon layer portion is lowered, and the source of the insulated gate field effect transistor is added to the main surface of the semiconductor substrate. Alternatively, there is provided a method for manufacturing an MIS integrated circuit device, comprising the steps of forming a drain region and, after removing the mask film, forming a bias electrode on the resistor through an insulating film. .

The present invention will be specifically explained below along with the manufacturing process of some examples.

Embodiment 1 FIG. 1 shows an embodiment in which the present invention is applied to a variable resistance element formed as a part of a complementary MO8 IC.

(a) Prepare an n-type Si substrate (wafer) 1, cover the surface with a thermal oxide film (SiO2) 2 to a thickness of 1000 to 2000 A, and mask a part of the oxide film 2 with a photoresist film 3. Then, B (boron) ions were implanted through the oxide film (B: I x 10'%cffl, 100ke
v') A B implantation layer 4 is formed on a part of the Si substrate under the oxide film that is not covered with the photoresist film 3.

(b) Using the photoresist film 3 as a mask, the oxide film on the implantation layer 4 is removed by etching.

This creates a step for mask positioning in the process of oxide film 2[d.

(C) The photoresist mask 3 is removed, a new oxide film 5 (thickness: 120 OA) is formed by thermal oxidation, and boron is simultaneously diffused to form a P-type well region 6 (depth: 5 to 6 μm).
) to form.

(d) Photoetching the oxide film 5 to expose each active region 1a, 6p of the substrate button and well.

(e) Gate oxide film 7 is formed on the exposed surface by thermal oxidation.
(thickness: 125OA) and monosilane (S
Polycrystalline S1 layer 8 (thickness: 500
0A') is formed.

(f) Polycrystalline Si layer 8 is photo-etched to remove unnecessary portions, leaving portions 8a, sb and 8c which will serve as gate ends and variable resistance sections.

Resistor ions are implanted so that a desired resistance value is obtained in the variable resistance section 8c.

For example, boron ions are implanted at an impurity concentration of 1014 to 10''/crA at an energy of 50 keφ.

This boron ion implantation can be performed without using a mask to form a pattern over the entire surface of the semiconductor substrate, or can also be performed using a mask such as a resist that exposes only the variable resistance section 8c.

(g) Polycrystalline silicon 8a and sb are aligned with the mask, and the oxide film 7 in the source and drain regions for the n-channel MO8FET, and the oxide film 7 in the source and drain regions for forming the p-channel MO8 are treated with hydrofluoric acid. Remove by etching with a mixed etchant containing nitric acid.

(h) CVD (Chemica) on the surface of the semiconductor substrate.
5i by VaporDeposition) method
029, and then [p-channel MO8FET forming part, that is, the partial button with polycrystalline silicon 8b as the gate electrode, and both ends of the resistor, that is, the C of the electrode extension part of the resistor.
Selective etching is performed on VD5iO29.

Next, side light is diffused using boron nitride as an impurity source to form the source region 10 of the p-channel MO8FE'l' formation. Drain region 11. Both ends of the variable resistance section 8c are made into p-type high concentration impurity regions.

(i) Etching and removing the above CVD5i029,
Hn channel MO8F with second CVD 5in213
Selectively etch the CVD 5 in 213 on the ET forming part.

Next, a source region 14 and a drain region 15 of an n-channel MO8FET formation portion are formed by phosphorus diffusion, and at the same time, the polycrystalline silicon 8a is made into an n-type.

(j) The CVD 5iO 213 is removed, a new insulating film 25 of CVD 5i02 or the like is formed on the entire surface, and the insulating film 25 is contact-etched.

Finally, electrodes 16, 17° 18, 19, 2 are connected to the source and drain region buttons and the contact portions of the resistor by vacuum At (aluminum) evaporation method and photoetching method.
0 and 21, and a variable electrode (bias electrode) 22 is provided on the resistor via an insulating film 25, thereby completing a complementary MO8-IC device.

Figure 2 shows a MOS/IC device 1 manufactured by the above method.
/? FIG.

To the variable resistor shown in FIGS. 1 and 2, an electric field is applied from the variable electrode 22 to the polycrystalline Si resistor 8c [voltage 1] via the insulating film CVD 5i0213.

Since the conductivity type of the resistor is p-type, when the electric field (G) is applied here, a depletion layer spreads from the insulating film side to the resistor, the number of carriers decreases, and the resistance value increases.

(If you lower the electric field →, carriers will increase and the resistance value will decrease.

Figure 3 shows ID-V based on experimental data of the variable resistor mentioned above.
An example of the D characteristic is shown.

According to the manufacturing method of the above embodiment, the objective can be achieved for the following reasons.

1. The length of the current path in the resistor section is determined by 5i029 when forming the source and drain regions of the MOSFET.

Therefore, ion implantation for determining the resistance value of the resistor portion can be performed without using a mask or the like to limit the ion implantation range.

2. Since the ion implantation method is used, the amount of impurities introduced can be relatively accurately controlled, and the resistance value can be controlled accurately.

3. Since the ion implantation is performed before forming the source and drain regions of the MOSFET, the polycrystalline Si layer into which impurity ions have been implanted is annealed at the processing temperature during the formation of the source and drain regions.

As a result, the implanted impurity becomes an effective impurity for setting the resistance value.

4. Since the MOSFET has a Si gate structure, the polycrystalline Si layer for forming the resistor can be formed without adding any special manufacturing steps.

In the first embodiment, the variable electrode is provided on the CVD-8iO2 film or the PSG film, and an electric field is applied to the resistor through these insulating films.

However, in forming the above-mentioned CVD-8iO2 or PSG, it is not always easy to control the thickness, and it is difficult to obtain a constant film thickness.

On the other hand, when the resistor is used as a variable resistor, its characteristics are greatly affected by the thickness of the insulating film, so it is recommended that the thickness of the insulating film be constant.

Therefore, in the case of an IC, considering that the substrate is grounded, the following manufacturing method can be considered to compensate for the drawbacks of the insulating film.

Embodiment 2 FIG. 4 shows part of the manufacturing process of an example in which the present invention is applied to another type of complementary MO8IC.

(a) Two p-type wells 6.23 are formed on one main surface of the n-type Si substrate 1, corresponding to steps a and b of Example 1.
form.

Of the two wells, well 6 contains n-channel MO8F.
ET, the well 23 will be used as a bias power supply connection for the resistor section, and a p-channel MO8FET will be formed in the substrate located in the middle of the two wells.

(b) Partially etching the oxide film 5 to form a gate oxide film? A, 7b are formed, and at the same time, a thermal oxide film 7c for resistor control is formed on the well 23.

A polycrystalline Si layer is formed on these thermal oxide films, and this polycrystalline Si layer is made of polycrystalline Si according to step f of Example 1.
8a, 8b and the polycrystalline Si resistor 8c, and then these polycrystalline Si 8a, a
b Implant impurity ions into 8c.

(C) Following the process of Example 1, the p-type source/drain regions 10 and 11 are formed by acceptor diffusion, and at the same time, part of the well 23 is nip-diffused, and this is used as a variable electrode (bias electrode). ) Take-out portion 24.

Step i of Example 1 [Therefore, n-type source/drain regions 14 and 15 are formed in the well 6 by donor diffusion.

Finally, connect each source, drain region, variable electrode extraction button, and both terminals of the resistor.

By forming the U electrodes 16 to 22, a complementary MO8 IC with a variable resistance section is completed.

The manufacturing method of Example 2 can achieve its purpose for the same reason as Example 1.

[Brief explanation of the drawing]

Figures 1 a to j are manufacturing process diagrams of an embodiment of the present invention;
The figure is a cross-sectional view of the main part of the completed IC of the above-mentioned embodiment, FIG. 3 is a diagram of I, -V, and characteristic curves of the resistor with vl as a parameter, and FIG. FIG. 3 is a cross-sectional view of a part of the manufacturing process of the example. 13. 1a... Active region on substrate, 2... Thermal oxide film, 3. ...Photoresist mask, 4...B implantation layer, 5...thermal oxide film, 6...p
Type well, 6a...active area on well 6, 7
, 7a. 7b... Gate oxide film, 7c... Thermal oxide film of variable resistance section, 8... Polycrystalline Si, 8a, ab... Polycrystalline Si gate, 8c... Polycrystalline Si resistor, 9 ...C
VD・SiO2 mask, 10, 11...p type source・
Drain region, 12... p-type contact portion of resistor, 13-CVD-8i02 mask, 14, 15-n
Type source drain, 16, 17, 18, 19... Source, drain electrode, 20.21... Resistor electrode, 2
2... Variable electrode, 23... P-type well for forming variable resistance part, 24... Variable electrode extraction part, 25...
Insulating film.

Claims (1)

[Claims] 1. A first insulating film on a main surface of a semiconductor substrate and gate insulation of the insulated gate field effect transistor for a method of manufacturing an MIS integrated circuit device having an insulated gate field effect transistor and a resistor. forming a second insulating film that will become a film; and forming a polycrystalline silicon layer on the first and second insulating films, and forming a first polycrystalline silicon layer that will become the resistor on the first insulating film. forming a second polycrystalline silicon layer to serve as a gate electrode of the insulated gate field effect transistor on the crystalline silicon layer and the second insulating film; and implanting impurity ions into at least the first polycrystalline silicon layer. a step of adjusting the resistance to a predetermined resistance value, and a step of covering the portion of the first polycrystalline silicon layer that is to be the resistor with an impurity-introduced mask film, and the portion of the polycrystalline silicon layer that is not covered with the mask film; and a step of lowering the resistance of the polycrystalline silicon layer portion by simultaneously introducing impurities into a predetermined portion of the main surface of the semiconductor substrate, and forming a source or drain region of the insulated gate field effect transistor on the main surface of the semiconductor substrate. and, after removing the mask film, forming a bias electrode on the resistor through an insulating film.