JPS5829626B2 - Method for manufacturing complementary MIS integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a complementary MIS or MOS (metal-insulator-semiconductor) integrated circuit device in which a polycrystalline Si (silicon) layer is used as a resistor. The present invention relates to a method of manufacturing a complementary MIS integrated circuit device with variable resistance.

It has been considered to insert a high resistance between the input section and the output section of a complementary MOS transistor circuit for watches [i-] in order to stabilize the oscillation in the oscillation circuit section.

When this resistor is incorporated into a semiconductor integrated circuit (IC) chip, it has been considered to use it as a polycrystalline Si thin film resistor.

It was found that when a bias voltage was applied to the chip substrate of such an IC, the resistance value of the thin film resistor changed.
It has become clear that semiconductor ICs can also be used as variable resistors.

When attempting to construct a thin film resistor or a variable resistor using polycrystalline Si as described above, it is necessary to introduce impurities into the polycrystalline Si in order to control the resistance value to a desired value.

As a result of investigation, it was found that an appropriate method for introducing impurities into polycrystalline Si is by impurity ion implantation.

Therefore, the main object of the present invention is to provide a novel method for manufacturing a complementary MIS integrated circuit device including a thin film resistor made of polycrystalline Si.

Another object of the present invention is to provide a method for manufacturing the above-mentioned complementary MIS integrated circuit device, which is easy to manufacture.

Further objects of the invention will become apparent from the following description and drawings.

The gist of the present invention for achieving the above object is to form a second conductivity type well region on one main surface of a first conductivity type semiconductor substrate,
A complementary MIS integrated circuit device, wherein a second conductivity type insulated gate field effect transistor is formed on one main surface of the first conductivity type semiconductor substrate, and a first conductivity type insulated gate field effect transistor is formed on the main surface of the well region. A method of manufacturing,
a step of forming a polycrystalline silicon layer through an insulating film on the well region formed simultaneously with the well region, and a step of implanting impurity ions into the polycrystalline silicon layer on the well region to a desired resistance value; A portion of the polycrystalline silicon layer that is to be a resistor is covered with an impurity-introduced mask layer, and a portion of the polycrystalline silicon layer that is not covered with the mask layer is used as a source or drain region of an insulated gate field effect transistor. and forming an electrode for applying a predetermined potential to the well region under the resistor of the polycrystalline silicon layer. It's in the manufacturing method.

The present invention will be specifically explained below along with the manufacturing process of some examples.

Embodiment 1 FIGS. 1A to 1I are cross-sectional views of a semiconductor substrate through each manufacturing process of the embodiment.

(a) An n-type Si substrate (sea urchin...) 1 is prepared, the surface is covered with a thermal oxide film (SiO2) 2 to a thickness of 1000 to 2000A, and a part of the oxide film 2 is covered with a photoresist film 3. Using a mask, B (boron) ions were implanted through the oxide film (B: 1 x 10' months - 9100 keV'), and a part of the Si substrate under the oxide film that was not covered with the photoresist film 3 [B was implanted into the implanted layer 4]. to make.

(b) Using the photoresist film 3 as a mask, the oxide film on the implantation layer 4 is removed by etching.

This creates a step in the oxide film 2 for mask positioning in step d.

(C) Remove the photoresist mask 3 and form a new oxide film 5 (thickness 1200 A') by thermal oxidation,
At the same time, boron is diffused to form p-type well regions 6 and 23 (depth 5 to 6 μm).

(d) Photoetching the oxide film 5 to expose the active regions 1a, 6b and 23a of the substrate and well.

(.

) Gate oxide films 7a, 7b are formed on the exposed surface by thermal oxidation.
and 7c (thickness: 1250A), and on this a polycrystalline Si layer (thickness: 5A) formed by decomposing monosilane (SiH4).
000A) is formed, and then the polycrystalline Si layer is photoetched to form a gate electrode (G) and a portion 8a which will become a variable resistance section.

Unnecessary parts are removed leaving 8b and 8c.

Resistor ions are implanted so that a desired resistance value is obtained in the variable resistance section 8c.

For example, acceptor impurity concentration 1014 to 1015/cn'? Enter.

This boron ion implantation can be performed over the entire surface of the semiconductor substrate without using a mask, or can be performed using a mask such as a resist that exposes only the cut variable resistance section 8c.

(f) Using polycrystalline silicon 8a, 8b, and 8c as masks, oxide film 7a in the source and drain regions for forming an n-channel MO8FET, oxide film 7b in the source and drain regions for p-channel MO8FET, and p-type The oxide film 7c on the well region 23 is removed by etching with a mixed etchant of hydrofluoric acid and nitric acid.

(g) CVD (Chemica) on the surface of the semiconductor substrate
5i by VaporDeposition) method
Then, CvDSiO 29 is selectively etched on the Cp channel MO8FET shape portion, that is, the portion where the polycrystalline silicon 8b is used as the gate electrode, and on both ends of the resistor, that is, the electrode extension portion of the resistor.

Next, by diffusion using boron nitride as an impurity source, the source region 10 of the p-channel MO8FET forming part is
．． Drain region 11. Electrode extension portion 24 of p-type well region 23. Both end portions 8C1 and 8c3 of the variable resistance portion 8c are made into p-type high concentration impurity regions.

(h) Etching and removing the CVD5iO29,
Connect the second CVD5i0213, n-channel AMO8F
Selectively etch the CVD5i0213 on the ET forming part.

Next, a source region 14 and a drain region 15+ of an n-channel MO8FET formation portion are formed by phosphorous diffusion, and at the same time, the polycrystalline silicon 8a is made to be n-type.

(i) The above CVD5iO213 is removed, and a new insulating film 25 such as CVD5i02 is formed on the entire surface,
The insulating film 25 is contact-etched, and then vacuum At
Electrodes 16, 17, 18, 19, 20, 21 connected to the source and drain region buttons and the contact portions of the resistor are provided by (aluminum) vapor deposition method and photoetching method, and electrodes 22 are provided in the electrode extraction portion 24. By doing so, a complementary MO8 IC device is completed.

Figure 2 shows a MOS/IC device manufactured by the above method [
FIG. 1 is a drawing for explaining an operation mode of a variable resistor section in FIG.

In a variable resistor as shown in Figures 1 and 2,
An electric field due to a voltage v1 is applied to the polycrystalline Si resistor 8c of the p-type well region 23 as a bias electrode via the insulating film 7c.

Since the conductivity type of the resistor 8c2 is p-type, here (G)
When the electric field is lowered, a depletion layer spreads from the insulating film side to the resistor, the number of carriers decreases, and the resistance value increases.

Conversely, if the electric field is lowered, carriers will increase and the resistance value will decrease.

FIG. 3 shows the bias voltage (v1', αV) and the voltage of the variable resistor (2) that changes depending on Vl.

−■. An example of the characteristics is shown.

According to the manufacturing method of the above embodiment, the objective can be achieved for the following reasons.

1. A resistor can be formed on a semiconductor substrate forming a complementary MO8FET, and is insulated from this substrate.

2. The well region 23 formed at the same time as the well region 6 for the n-channel MO8F'ET can be used, and the resistance of the resistor 8c2 can be increased by applying an appropriate bias voltage from the well region 23 to the resistor 8c2. The value can be a predetermined value.

3. By forming the insulating film 7c in the portion where the resistor 8c2 is formed by using an oxide film obtained by oxidizing the surface of the well region 23, its thickness can be easily controlled.

Since the thickness of the oxide film 7c is relatively accurate, the bias voltage applied from the region 23 to the resistor 8c2 can be made almost constant regardless of manufacturing variations in the device.

4. Since impurities are introduced by the ion implantation method which allows relatively high precision, the resistance value of the resistor 8c2 can be set relatively accurately.

5. The length of the resistor 8c2 is determined by 5i029 and the high concentration impurity conduction when forming the source/drain regions of the MOSFET.

Therefore, ion implantation for determining the resistance value of the resistor can be performed without using a mask or the like to limit the ion implantation range.

6. Since the ion implantation is performed before forming the source/drain regions of the MOSFET, the polycrystalline Si layer implanted with impurity ions is annealed at the processing temperature during the formation of the source/drain regions.

As a result, the implanted impurity becomes an effective impurity for setting the resistance value.

7. By forming the MOSFET with a Si gate structure, the polycrystalline Si layer for forming the resistor can be formed without increasing any special manufacturing process.

[Brief explanation of drawings]

Figures 1a to 1i are cross-sectional views of a semiconductor substrate divided into manufacturing steps according to an embodiment of the present invention, Figure 2 is a cross-sectional view of the main parts of an IC when completed in the above-mentioned embodiment, and Figure 3 shows vl as a parameter. ■ of the resistor. -VD characteristic curve diagram. DESCRIPTION OF SYMBOLS 1... N-type Si substrate, 1a... Active region on substrate, 2... Thermal oxide film, 3... Photoresist mask, 4... B implantation layer, 5... Thermal oxide film, 6...p
Type well, 6a...active area on well 6, 7
, 7a. 7b... Gate oxide film, 7c... Thermal oxide film of variable resistance section, 8... Polycrystalline Si, 8a, ab... Polycrystalline Si gate, 8c... Polycrystalline Si resistor, 9 ...C
VD・5i02 mask, 10, 11...p-type source,
Drain region, 8cl, 8c3...p-type contact portion of resistor, 18...CVD=SiO2 mask, 1
4,15...n-type source, drain, 16,17,1
8゜19...source, drain electrode, 20.21...
- Resistor electrode, 22... Variable electrode, 23... P-type well for forming variable resistor part, 24... Variable electrode extraction part, 25... Insulating film.

Claims (1)

[Claims] 1. A second conductivity type well region is formed on one main surface of the first conductivity type semiconductor substrate, and a second conductivity type insulated gate field effect transistor is formed on the one main surface of the first conductivity type semiconductor substrate. and forming a first conductivity type insulated gate field effect transistor on the main surface of the well region, the method comprising: forming an insulating film on the well region formed at the same time as the well region. a step of forming a polycrystalline silicon layer through a mask, a step of implanting impurity ions into the polycrystalline silicon layer above the well region to obtain a desired resistance value, and a step of implanting a portion of the polycrystalline silicon layer that will become a resistor through an impurity introduction mask. a step of introducing an impurity into a portion of the polycrystalline silicon layer not covered with the mask layer and a portion to be a source or drain region of an insulated gate field effect transistor while the polycrystalline silicon layer is covered with a layer; forming an electrode for applying a predetermined potential to the well region under the resistor. 2 Above 1. The second conductivity type insulated gate field effect transistor has a structure in which a polycrystalline silicon layer serves as a gate electrode, and the polycrystalline silicon layer on the well region is connected to the first conductivity type insulated gate field effect transistor. 2. The method of manufacturing a complementary MIS integrated circuit device according to claim 1, wherein the gate electrode of the second conductivity type insulated gate field effect transistor is formed simultaneously.