JPS5829656B2 - logic circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic circuit that operates similar to a flip-flop circuit.

The conventionally known synchronous D-type flip-flop circuit (
The FF (hereinafter abbreviated as FF) is generally configured as shown in FIG. 1 or 2.

FIG. 1 shows an example using six Nant gates, which operate in response to a clock pulse CP to obtain an output Q which is an input signal delayed by one clock pulse time.

Q is an output having the opposite phase to the output Q.

FIG. 2 shows an example using eight Nant gates, which are operated by a clock pulse CP and a clock pulse CP having an opposite phase.

In order to integrate such a curved FF, it goes without saying that a circuit configuration with as few elements and wires as possible is desired from the viewpoint of power consumption and degree of integration.

This invention reduces the number of gates through which pulses pass and appropriately sets the time delay of pulses passing through the gates, thereby reducing the number of wires and creating a logic circuit that enables low-power operation and improved integration. This is what we provide.

The basic logic circuit of this invention is composed of four Nant gates or four Nor gates.

FIG. 3 shows the basic configuration when using a Nant gate.

That is, the first and second Nantes gates G1. G2 feed back one output to the other input, and similarly connect the third and fourth Nant gates G3 . Regarding G4, one output is fed back to the other input, and the first and second Nant gates G1 . G
2 outputs to the third and fourth Nant gates G3. G
4 is entered.

Then, a clock pulse CP is commonly input to the first and second gates G, , G2, and the third and fourth gates G3, .
A clock pulse CP having an opposite phase to this is commonly input to G4, a signal is sent to the first and second gates respectively, D is input, and outputs Q1 . It is now possible to obtain Q2.

FIG. 4 shows an operation timing chart of this logic circuit.

FIG. 5 is an operation timing chart of the circuit of FIG. 2 shown for comparison.

The logic circuit according to the present invention has a basic configuration consisting of four gates, and by providing a delay element DL at the output end of the second gate G2 as shown in FIG. This is D without the D input.

That is, by inserting the delay element DL, the second gate G2
The delay in the output change of the first gate G1 is made larger than that of the first gate G1, and as a result, the third
It becomes possible to perform the same operation as the basic circuit shown in the figure.

In this case, the delay element DL only needs to delay the time when the gate output changes from high level to low level, and does not need to delay the time when the gate output changes from low level to high level. .

However, when using the Noah gate, this relationship is reversed.

The logic circuit according to the present invention has I2L (
Integrated Injection Logi
The effect is particularly great when using c).

(2) 2L is a recently developed logic element, which can be expressed as a circuit as shown in FIG.

That is, it is composed of an impark NPN transistor T1, and an injector PNP l-transistor T2 whose collector is connected to the base of this transistor T1 and whose base is connected to the emitter.

The inverter transistor T1 is constituted by a so-called reverse structure particle transistor in which the emitter and collector of a normal planar transistor are reversed, and the injector transistor T2 shares its collector and base with the pace emitter of the inverter transistor T1. Constructed as a lateral structure transistor.

Logic operation is performed by applying an external power source EE to the emitter of the injector transistor T2 and supplying charge to the base of the impark transistor T through this transistor T2.

In the example shown in FIG. 7, the impark transistor T1 is of a multi-collector type, and three output terminals OUT, -0UT3 are provided, and three input terminals IN1 - ■N3 are provided.
In the following explanation, this symbol 12L will be represented as shown in FIG.

FIG. 9 shows a logic circuit corresponding to FIG. 6 when such 2L is used.

They are basically the same in that they are composed of four gates G, 1 to G14 and operate with only one input.

Although the delay element DL shown in FIG. 6 is omitted in FIG. 9, it is used for the first and second games 1-G, 1. This is because by selecting the shape of G and □, it has the same function as adding a delay element.

That is, in the configuration of FIG. 9, the shape of the injector transistor in the second gate G12 is different from that of the other gates, and the supply current is set to be about % of that of the other gates.

As a result, the rise time of the input of the second gate GI2 is the same as that of the first gate G1. It will be longer than that of .

In this way, when the clock pulse CP changes from a low level to a high level, if the D input is at a high level, the potential at the input of the first gate G11 will be higher than that of the second gate G2. This causes the potential at the input portion of the second gate G, 2 connected to the output of the first gate G11 to become low level.

Conversely, if the D input is at a low level, the first game 1-01. The input part of the gate 1-G, □ does not reach a high level, and the potential of the input part of the second gate 1-G, □ goes to a high level, and the input part of the first gate G11, which connects to the output of the second gate G, 2, becomes high level. Reduce potential to low level.

As described above, the first and second games (G1. .

The potential at the input part of G1□ is uniquely determined as in the case where the delay element DL is inserted as shown in FIG. 6, and the desired logic operation as shown in FIG. 4 can be performed.

In this way, eliminating the need for the D input simplifies wiring and greatly contributes to improving the degree of integration when considering the case where several stages of this type of logic circuit are continuously connected to form a counting circuit, etc. .

In addition, in a counting circuit, etc., two gates can be connected from the output of one gate to the input stage.
In order to take out two feedback loops, an extra gate must be added in the conventional type that requires inputs D and D, but if the logic circuit according to the present invention is used, such an extra gate is not necessary. Become.

The logic circuit of FIG. 9 can be further modified to reduce wiring.

An example thereof is shown in FIG. This is the second game 1-G,
□ supply current to the first gate G1. At the same time, the supply current of the third gate 1-G, 3 is made smaller than that of the fourth gate G14, and the output of the first gate 1-011 and the third gate G13 are made smaller than that of the fourth gate G14. This eliminates the wiring between inputs.

Even in this case, the state when the clock pulse CP goes from a low level to a high level is different from that of the third and fourth gates G and 3.
．． By setting a difference in the rise time of the input part of G14, malfunctions will not occur because it is uniquely determined by the output of the second gate G,2.

Similarly, if the difference in rise time of the input parts of the third and fourth gates is reversed, the difference between the second gate G12 and the fourth gate G,4 as shown in FIG. Wiring can be omitted.

FIG. 12 is an example of a 5-letter counting circuit using the logic circuit of FIG. 10.

This is based on the circuit shown in Figure 10, and consists of three stages connected in cascade and the output of the final stage fed back to the input of the first stage.
It can be seen that the number of wires is very small.

FIG. 13 is an operation timing chart of this 5-letter counting circuit.

FIG. 14 is based on the logic circuit of FIG. 10, and has fifth and sixth gates G15 . This is an example in which a latch circuit made of G16 is provided.

By providing the latch circuit in this way, it is possible to obtain outputs Q and Q that are in a completely complementary relationship.

A similar effect can be obtained by providing a latch circuit in the same way as in the logic circuits shown in FIGS. 9 and 11.

FIG. 15 shows an embodiment of a % frequency divider circuit using the logic circuit of the present invention.

This is based on the logic circuit shown in FIG. 9, and the fourth gate G1
4 is fed back to the input of the first gate G, 1, and the output of the first and second gates G, □, G1 □ is fed back to the fourth and third gates G14, . By combining with the output of G13 and taking it out, the clock pulse CP, % of CP
Divided output Q.

This is to obtain Q.

If a similar percentage frequency divider circuit is configured based on the logic circuits shown in FIGS. 10 and 11, it can be represented as shown in FIGS. 16 and 17, respectively.

Set and reset functions can also be provided to change the contents of the logic circuit according to the present invention.

FIG. 18 is an example of this, in which gates Go, Ga4 are added to the logic circuit of FIG. 9, and a set signal S1 is added.
The reset signal R is input to a desired gate.

It goes without saying that the logic circuits shown in FIGS. 10 and 11 can have similar set and reset functions, and the way of setting and resetting can be modified in various ways depending on the purpose.

In the above description, the first stage gates, that is, the first and second gates G1. , G1□, but the supply currents of the first and second gates G, ,IG,□ are set equal, and the third and fourth gates G13°G,4 Even by simply making a difference in the supply currents, one wiring between the input stage and the output stage can be omitted, as shown in FIG. 19, which is effective.

Of course, in this case, the first and second gates G11. G.2
For each, the D input must be input.

By applying the circuit shown in FIG. 19, it is also possible to construct a circuit similar to J-KFF.

FIG. 20 is an example.

That is, the fifth and sixth gates G15 . A latch circuit consisting of G16 is provided,
The outputs of the third and fourth gates G13 and G14 are respectively connected to the first and second gates G1. .

Returning to the input of G1□, the first and second games) G, .

Inputs are input into J, respectively, in G and 2.

FIG. 21 is an example in which the circuit of FIG. 20 is provided with set and reset functions by adding gates Go, Ga4, as in the example of FIG. 18.

Although several examples have been given above, we have also experimentally confirmed what degree of difference is preferable when making a difference in the current supplied by the injector of the gate.

As a result, it was found that when the ratio of supply currents is less than 1.3, the operation becomes unstable, and when it exceeds 2.5, the operating frequency becomes undesirably low.

In this case, since the stability varies depending on the operating frequency, measures such as increasing the supply current ratio depending on the operating frequency may be taken.

In addition, instead of changing the shape of the injector to vary the supply current as a means of differentiating the rise time of the gate input section, for example, a capacitor may be provided at the gate input section to make a difference in the size of the capacitance. .

As explained in detail above, the logic circuit according to the present invention has a small number of elements, and the number of wiring can be reduced by appropriately setting the time delay of the pulse passing through the gate.
Low power operation and higher integration density can be achieved.

In the above description, the embodiment was mainly based on a multi-output NAND gate using 2L, but the logic circuit according to the present invention can also be constructed with a NAND gate using CMO8 or TTL.

Further, in the case of a negative logic configuration, a NOR gate may be used instead of a Nandt gate.

Furthermore, when f2L is used, due to its nature, a means of cutting off the supply current from the injector may be used to output a low level.

In addition, the present invention can be modified in various ways without departing from its spirit.

[Brief explanation of drawings]

1 and 2 are diagrams showing conventional synchronous type FF,
Figure 3 is a diagram showing a logic circuit using four Nant gates which is the basis of this invention, Figure 4 is its operation timing chart, Figure 5 is an operation timing chart of the circuit in Figure 2, and Figure 6 is this diagram. A diagram showing the configuration of an example of a logic circuit according to the invention, FIG. 7 is an equivalent circuit diagram of ■2L, FIG. A diagram showing an example of a logic circuit according to the present invention configured with
Figures 10 and 11 are diagrams showing modifications of Figure 9;
Figure 2 is a diagram showing a 5-letter counting circuit constructed using the logic circuit of Figure 10, Figure 13 is its operation timing chart,
Fig. 14 shows an embodiment in which a latch circuit is provided in the logic circuit of Fig. 10, and Figs. 15 to 17 show percentage frequency divider circuits constructed using the logic circuits of Figs. 9 to 11, respectively. 18 is a diagram showing an embodiment in which the logic circuit of FIG. 9 is provided with set and reset functions, FIG. 19 is a diagram showing an application example of the present invention, and FIG. 20 is a diagram showing the logic circuit of FIG. FIG. 21 is a diagram showing an example of a circuit similar to J-KFF using a circuit, and FIG. 21 is a diagram showing an example in which the circuit of FIG. 20 is provided with set and reset functions. G, , G, 1...First Nantes gate, G
2. G, 2... Second Nantes gate, G3. G
13...Third Nantes Gate, G4. G14・
...Fourth Nantes gate, DL...Delay element.

Claims (1)

[Claims] 1. Constructed using four NAND or NOR gates, the outputs of the second and first gates are fed back to the inputs of the first and second gates, respectively, and the outputs of the third and fourth gates are fed back to the inputs of the first and second gates, respectively. The outputs of the fourth and third gates are fed back to the inputs, respectively, and the outputs of the first and second gates are input to the third and fourth gates, respectively, so that the delay in the output change of the second gate is The clock pulse commonly input to the first and second gates and the clock pulse commonly input to the third and fourth gates are set to be larger than that of the third and fourth gates, and A logic circuit characterized in that a desired input signal is input to a gate of No. 1 to perform a logic operation similar to a D-type flip-flop. 2 Each of the first to fourth gates is composed of a logic element consisting of an inverter transistor and a complementary injector transistor with a collector connected to the base of this transistor and a base connected to the emitter. Claim 1: By setting the rise time of the gate input section to be longer than that of the first gate, the delay in output change of the second gate is made larger than that of the first gate. Logic circuit described in section.