JPS5943845B2 - logic circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic circuit that operates similar to a flip-flop circuit.

Figure 1 shows the conventionally known master-slave type D.
This is a type flip-flop circuit (hereinafter abbreviated as FF).

Consists of 8 Nant gates, clock pulse CP,
It operates in response to CP, and outputs pulse outputs Q and Q, which are input signals and delay the D signal by one clock pulse time.

Of the clock pulses CP and CP, for CP, the second
As shown in the figure, it can be omitted as an internal clock using the gate output of the first stage.

It is easy to construct a J-type FF from these D-type FFs.

Examples are shown in FIGS. 3 and 4.

When integrating such FF into a single chip, it is desirable to reduce the number of gates and wiring as much as possible from the viewpoint of power consumption and degree of integration.

The present invention provides a logic circuit that operates similar to a master-slave type FF, which reduces the number of gates and wires, reduces power consumption, and improves the degree of integration.

The logic circuit according to the present invention is basically composed of six Nant gates or NOR gates.

FIG. 5 shows the basic configuration when using a Nant gate.

That is, the first and second Nantes gates G1. G2 feed back one output to the other input, and similarly the third and fourth Nant gates G3 . Regarding G4, one output is also fed back to the other input.

Fifth and sixth Nantes gates G5. G6 also feeds back one output to the other input, and the fifth and sixth gates G5. G6 constitutes a latch circuit, and the first and second
Gate G1. The output of G2 is passed through the latch circuit to the third
Fourth gate G3. It is designed to be input to G4.

Then, the first and second gates G1. A clock pulse CP is commonly input to G2, and the third and fourth gates G3. G4
Commonly input a clock pulse CP of opposite phase to this, input D input to the first gate G1, and input the D input to the third and fourth gates)
Outputs Q2 and Qt are obtained from G3 and G4.

Here, by providing a delay element DL at the output end of the second gate G2, the delay in the output change of the second gate G2 is reduced to the first
is larger than that of gate G1, and as a result,
b input is omitted.

In this case, the delay element DL only needs to delay the time when the gate output changes from high level to low level, and does not need to delay the time when the gate output changes from low level to high level. good.

However, when using the Noah gate, this relationship is reversed.

FIG. 6 shows an operation timing chart of the logic circuit configured in this manner.

The logic circuit according to the present invention has I2L (
Integrated Injection Logi
The effect is particularly great when using c).

(2) 2L is a recently developed logic element, which can be expressed as an equal circuit as shown in FIG.

That is, it is composed of an inverter NPN transistor T1 and an injector PNP transistor T2 whose collector is connected to the base of this transistor T1 and whose base is connected to the emitter.

The inverter transistor T1 is constituted by a so-called reverse structure particle transistor in which the emitter and collector of a normal planar transistor are reversed, and the injector transistor T2 shares its collector and base with the base emitter of the inverter transistor T1. Constructed as a lateral structure transistor.

Logic operation is performed by applying an external power supply VER to the emitter of the injector transistor T2 and supplying charge to the base of the inverter transistor T1 via this transistor T1.

In the example shown in FIG. 7, the inverter transistor T1 is of a multi-collector type, and two output terminals 0UT1 and 0UT2 are provided, and three input terminals IN1 to ■N3 are provided.
The symbol for I2L will be expressed as shown in FIG. 8 in the following explanation.

FIG. 9 shows a logic circuit corresponding to FIG. 5 when such 2L is used.

It is basically the same in that it is composed of six first to sixth gates G11 to G16 and operates with only one input.

Although the delay element DL shown in FIG. 5 is omitted in FIG. 9, this is because the delay element DL shown in FIG. This is because by selecting the shape of G1□, it has the same function as adding a delay element.

That is, in the configuration of FIG. 9, the shape of the injector transistor in the second gate G12 is different from that of the other gates, and the supply current is set to be about 1/2 that of the other gates.

As a result, the rise time of the input of the second gate G12 is longer than that of the first gate G11.

In this way, when the clock pulse CP changes from a low level to a high level, if the D input is at a high level, the potential at the input part of the first gate 1-G1□ will be higher than that of the second gate G12. The potential at the input portion of the second gate G1□ connected to the output of the first gate G11 becomes low level.

Conversely, if the D input is at a low level, the input part of the first gate 1 cannot go to a high level, the potential at the input part of the second gate G12 becomes a high level, and the output of the second gate G1□ The potential at the input portion of the first gate G11 connected to the gate G11 is suppressed to a low level.

As described above, the first and second gates G1 when the clock pulse CP goes from low level to high level depending on whether the D input is high level or low level.

The potential at the input part of G1□ is uniquely determined as in the case where the delay element DL is inserted as shown in FIG. 5, and the desired logic operation as shown in FIG. 6 can be performed.

In this way, eliminating the need for the b input simplifies wiring and greatly contributes to improving the degree of integration when considering the case where several stages of this type of logic circuit are connected in cascade to form a counting circuit, etc. .

In addition, in a counting circuit, etc., two gates can be connected from the output of one gate to the input stage.
In order to take out two feedback loops, an extra gate must be added in the conventional type that requires D and D inputs, but if the logic circuit according to the present invention is used, such an extra gate is not necessary. .

- The logic circuit shown in FIG. 9 can be modified in various ways.

In FIG. 10, the outputs of the first and second gates G1□, G, and 2 are used as internal clocks, and the external clock pulse d is omitted.

FIG. 11 shows that the output of the third gate G13 is fed back to the input of the first gate G1, and the output of the third gate G13 is fed back to the input of the first gate G1. G
This is an example in which a signal input terminal is provided in 1□, and a circuit configuration similar to a type FF is made in J-.

FIG. 12 is a combination of FIGS. 10 and 11, and is an example of a circuit similar to a J-type FF in which the clock pulse CP is omitted.

As outputs, the third and fourth gates G13. G14 as well as the fifth and sixth gates G15. The output of G16 can also be used.

FIG. 13 is an example of this, in which outputs Q and Q are taken out from the fifth and sixth gates G and 5°G16 of the circuit shown in FIG.

This circuit has an output Q1. By connecting Q2 as the outputs Q and Q in FIGS. 1 to 4, it is possible to operate similar to a normal FF.

FIG. 14 shows a synchronous ternary counting circuit constructed by connecting the circuits shown in FIG. 13 in two stages.

The operation timing chart of this counting circuit is 15th.
It will look like the figure.

In the logic circuit of FIG. 9, the third and fourth gates G13
j By making a difference in the current supplied to G14, the number of wiring lines can be further reduced.

FIG. 16 is an example of this. By making the current supplied to the fourth gate G14 larger than that to the third gate G13, the wiring between the sixth gate G16 and the fourth gate 014 can be omitted. ing.

If the magnitude relationship of this supply current is reversed, the wiring between the fifth gate G15 and the third gate G13 can be omitted as shown in FIG. 17.

Regarding the logic circuit of FIG. 11, the third and fourth
If we make a difference between the supply currents of gates G13 and G14, we get
Again, a circuit similar to a J-type FF without wiring as shown in FIG. 18 or 19 can be obtained.

By changing the way in which the clock pulse σ0 shown in the logic circuit of FIG. 9 is applied, the third and fourth gates G13.
The clock pulse CP may be applied only to the third gate G13 among the gates G14.

In this case, the third and fourth gates G13. As shown, even if there is no difference in the supply current between the fifth gates G1. The wiring between the gate G13 and the third gate G13 can be omitted.

In the circuit shown in FIG. 20, it is possible to construct a circuit similar to a J- type FF, as in the case of FIG. 9, and its configuration is as shown in FIG. 21.

In the logic circuit shown in FIG. 10, if the J and K terminals are left open, it becomes a 1/2 frequency divider circuit.

The operating waveforms at that time are shown in FIG.

For comparison, FIG. 23 shows operating waveforms when the circuit shown in FIG. 11 is used as a 172 frequency divider circuit by opening the terminal J.

As is clear from comparing Figures 22 and 23, the output Q
Although the waveform of 1 is slightly different, there is no difference in frequency division operation.

It is also possible to omit the clock pulse CP in the logic circuit of FIG.

In that case, the configuration is such that the outputs of the first and fourth gates GI I and GI4 are input to the third gate G13 as shown in FIG.
0. The output of G1□ may be input to the third gate G13.

Even if the logic circuits shown in FIGS. 24 and 25 are used, J −
It is possible to construct a circuit similar to a type FF, as shown in FIGS. 26 and 27, respectively.

To change the contents of the logic circuit, set and reset terminals may be provided.

An example in which set and reset terminals are provided in the logic circuit of FIG. 9 is shown in FIGS. 28 and 29.

In these figures the gate Gs. GR is for transmitting set and reset signals.

Note that some of the set and reset signal lines can be omitted depending on the agreement.

It is of course possible to similarly provide set and reset functions to a modification of the logic circuit shown in FIG. 9, that is, a circuit similar to a J-type FF, a circuit in which the application of the clock pulse CP is partially omitted, etc.

Several examples have been given above, and we have also experimentally confirmed what degree of difference is preferable when making a difference in the current supplied by the gate injector.

As a result, it was found that when the ratio of supply currents is less than 1.3, the operation becomes unstable, and when it exceeds 2.5, the operating frequency becomes undesirably low.

In this case, since the stability varies depending on the operating frequency, measures such as increasing the supply current ratio depending on the operating frequency may be taken.

In addition, instead of changing the shape of the injector to vary the supply current as a means of differentiating the rise time of the gate input section, for example, a capacitor may be provided at the gate input section to make a difference in the size of the capacitance. .

As explained in detail below, the logic circuit according to the present invention has a small number of elements, and the number of wiring can be reduced by appropriately setting the time delay of the pulse passing through the gate.
It enables low power operation and improved integration.

In the above description, the embodiment was mainly based on a multi-output NAND gate using 2L, but the logic circuit according to the present invention can also be constructed with a NAND gate using CMO8 or TTL.

Further, when configured with negative logic, a NOR gate may be used instead of a Nant gate.

Furthermore, when using 2L, due to its nature, a method of cutting off the supply current from the injector may be used to output a low level.

In addition, the present invention can be modified in various ways without departing from its scope.

[Brief explanation of drawings]

Figures 1 and 2 show a conventional master-slave type D FF, and Figures 3 and 4 show a conventional J- type FFF.
5 is a diagram showing a logic circuit using six Nant gates which is the basis of this invention, FIG. 6 is an operation timing chart thereof, FIG. 7 is an equivalent circuit diagram of I2L, and FIG.
9 shows the basic configuration of a logic circuit according to the present invention using 2L; FIGS. 10 to 13 show variations thereof; 1
Figure 4 is a diagram showing the configuration of a synchronous ternary counting circuit using the logic circuit of Figure 13, Figure 15 is its operation timing chart, and Figures 16 to 21 are the diagrams of Figure 9 with a reduced number of wires. A diagram showing a modified example of the logic circuit, FIG. 22 is an operation timing chart of the 1/2 frequency divider circuit based on the logic circuit of FIG. 21, and FIG. 23 is an operation of the 1/2 frequency divider circuit based on the logic circuit of FIG. 11. Timing charts, FIGS. 24 to 27 are diagrams showing modified examples of the logic circuit in FIG. 20, and FIGS. 28 and 29 are diagrams showing examples in which the logic circuit in FIG. 9 is provided with set and reset functions. It is. G1. G1. ...First Nantes Gate, G2.
G12...Second Nantes Gate, G3. G13
・・・・・・Third Nantes Gate, G, , G14・
...Fourth Nantes gate, DL...Delay element.

Claims (1)

[Claims] 1. Constructed using six NAND or NOR gates, the outputs of the second and first gates are fed back to the inputs of the first and second gates, respectively, and the outputs of the third and fourth gates are fed back to the inputs of the first and second gates. The outputs of the fourth and third gates are fed back to the inputs, respectively, and the delay of the output change of the second gate is set to be larger than that of the first gate, and the output of the fourth and third gates is fed back to the input. The clock pulses input to the first gate and the clock pulses input to the third and fourth gates are set in opposite phases to each other, and the outputs of the first and second gates are passed through a latch circuit consisting of the fifth and sixth gates. 3,
A logic circuit characterized in that the state of a fourth gate is controlled to perform a logic operation. 2 The first to sixth gates are composed of a logic element consisting of an inverter transistor and an injector transistor complementary to this in which the collector is connected to the base of this transistor and the base is connected to the emitter. 2. The logic circuit according to claim 1, wherein the rise time of the input section is set to be longer than that of the first gate.