JPS5927504B2 - decoding circuit - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a decoding circuit for character information, etc. used in facsimile machines and the like. In recent years, high-speed facsimile devices have adopted a method of converting the run length of character information into an appropriate compressed code and transmitting it for the purpose of shortening transmission time and compressing the transmission band. Recently, the use of modified Hoffmann (MH) codes as a compression encoding method has been attracting attention. By the way, as shown in the attached table, this MH code is determined individually for run lengths of 63 or less, but for run lengths of 64 or more, it is determined for each 64. For example, a white run length of 70 Then, since 70 = 64 + 6, [110111110], and White Lanre L--9-- L-Heonongs 64 is also [110111110].
1101100110101] It is encoded as L--ri--J. Therefore, when decoding such an MH code into a signal corresponding to the original run length, the decoding memory is used for run lengths of 63 or less (hereinafter referred to as lower digits) and for run lengths of 64 or more (hereinafter referred to as lower digits). Henceforth, it will be necessary to prepare separately for those corresponding to the upper digits. However, since such decoding memory uses expensive ROM (read only memory), etc.
Using two sets of memories means that the decoding circuit cannot be realized at low cost. Therefore, the present invention focuses on this point, and when decoding a compression-encoded binary code signal such as the MH code mentioned above, one decoding memory is used in common for upper and lower digits. The present invention proposes a decoding circuit that can be installed to perform decoding. The details of the decoding circuit of the present invention will be explained below in accordance with the case where an MH code with a white run length of 70 is decoded in an embodiment shown in FIG. Corresponds to white run length 70 serially connected to manual terminal 1 [110111110]
The MH signal is a clock pulse φ. are sequentially loaded into the shift register 2 for parallel conversion by
When [11011] corresponding to [11011] is loaded into this shift register, the parallel conversion output corresponding to [11011] is applied as a reading address signal to the decoding memory 3 constituted by a ROM. In this case, the shift register 2 uses a 10-bit code that is larger than the maximum number of bits of the white MH code, 9, shown in the attached table, and that each MH signal is inserted into the shift register 2 before being introduced. First, a circuit (not shown) converts the content of the first bit (0 or 1) of each MH signal to 4.
1n or 80n signals are loaded across all bits of the shift register, after which each MH signal is introduced into the shift register 2. Therefore, when [11011] of the white run length 64 mentioned above is loaded, the parallel output of this shift register 2 becomes [0000011011], which becomes the address input of the memory 3. Since this is not directly related to the gist of this topic, further explanation will be omitted. The memory 3 is configured such that the address input from the shift register 2 has the lower digits (run length 63 or less) M as shown in the attached table.
If it corresponds to the H code, the binary code of the run length number corresponding to the MH code is derived to the six parallel output terminals 01 to 06, and 07=07 is output to the other output terminals 07 and 08, respectively. 60, derive the output 08-61'', and if the address input above corresponds to the MH code of the upper digits (run length 64 or more), calculate the run length number corresponding to the MH code. a×
The binary code corresponding to a when 64 is derived to the output terminals 01 to 06, and the output terminals 07 and 08 are
It is configured in advance to derive outputs of 07-61'' and 08="0'', respectively. Therefore, when the address signal [the parallel output of the shift register 2] corresponding to the white run length 64 is applied to the memory 3, the outputs of 01 to 06 of this memory 3 are a
Since it is -1, it becomes [000001], and 07-
81Z08-801. This 07-゛1” output (earth digit judgment output) is the first 1
The bit extraction circuit 4 is operated to generate the clock pulse φ2.
is derived by 1 bit A, and by this A1, the first
The binary down counter 5 is loaded with the binary output [000000] from the memory 3. Well, at this time,
Since 08="O", the second 1-bit extraction circuit 6 is not operated, and therefore the binary output from the memory 3 is not loaded into the second binary down counter 7. At the time when the MH signal [1110] corresponding to the white run length 6 is loaded into the shift register 2 (at this time, the parallel output of the shift register 2 becomes [.00000q, 1110] due to the above-mentioned reason). Then, in response to this address signal from shift register 2, the output of memory 3 from 0 to 06 becomes [000110],
And, 07=601,08-6r".This 08-
The output of 61'' (lower digit judgment output) operates the second 1-bit extraction circuit 6, derives the clock pulse φ2 by 1 bit A2 in the same manner as described above, and uses this A2 to output the second binary down counter. 7 is loaded with the binary number output [000110]-6 from the memory 3. Note that the first and second counters 5 and 7 are in this state before each binary number output from the memory 3 is loaded. Outputs Cl and C each represent whether each counter is loaded or not.
2 are both set to 6...I, so that the output of the AND gate 9 is also set to I2, and the flipflop 10 is preset by the output of this AND gate. Then, each of the binary codes [
000001] and [000110], the respective outputs Cl and C2 of this counter are both 601. Next, when the third 1-bit extraction circuit 8 derives the next 1-bit portion A3 of the clock pulse φ2, which is delayed by 1 bit from the output A2 of the second 1-bit extraction circuit 6, this A3 is used. Then the flip-flop 10 is set and its output becomes "high 1", so
The clock pulse φ2 is applied to the second counter 7 through the AND gate 11, and this counter thereby counts down sequentially. At the same time, the clock pulse φ2 derived through the AND gate 11 is sequentially introduced into the output shift register 12. When six clock pulses φ2 are applied to the second counter 7 in this way, this counter has the contents of all its bits capiO'', and the output C2 of this counter becomes 6 high 1, but at this time The output C1 of the first counter 5 is 6
Since it is low 7, flip-flop 10 is not reset. From this state, the second counter 7 outputs the clock pulse φ2.
When one more pulse is applied, the content of the second counter 7 becomes [111111] and at the same time a boro-1 output B is generated, and this output B causes the first counter 5 to be downgraded. 1 counter 5 is

The state becomes [000000], and the output C becomes 6 high. From this state, when [111111]-63 clock pulses φ2 are applied to the second counter 7, the second counter 7 again

[000000], and its output C2 is 1
...I". Therefore, at this time, AND gate 9
The output of is 7, which resets the flip-flop 10 and closes the AND gate 11, so that the second counter 7 and the output shift register 1
The application of clock pulse φ2 to φ2 is blocked. Therefore, in this state, the shift register 12 has 6+1+63=
This means that 70 clock pulses φ2 have been introduced,
This means that the decoding of the white run length 70 has been completed. Furthermore, when an MH signal with a white run length of 63 or less is introduced to the human input terminal 1, the outputs of 01 to 06 of the memory 3 are not loaded to the first counter 5 but only to the second counter 7, and thereby As soon as the second counter 7 reaches the "O" state, the application of the clock pulse φ2 to the counter 7 and the output shift register 12 is immediately blocked, but the operation in this case is explained above. It is clear from this. Although the explanation so far has been made regarding the case of decoding the white MH code, the same applies to the decoding of the black MH code. At this time, when both white and black MH codes are used like a facsimile image signal, when the clock pulse φ2 is introduced into the output shift register 12 for the white code, the clock pulse φ2 is changed to 10° by the number of clock pulses. The signal of 11' may be loaded into this shift register, and the signal of 11' may be similarly loaded into the shift register for the black code, or vice versa. Furthermore, instead of using burner reader counters for the first and second counters 5 and 7 as in this embodiment, by configuring the memory 3 to derive the inverted binary code, It is also possible to use a binary up counter. It goes without saying that the present invention is applicable not only to MH codes, but also to decoding binary code signals encoded in a similar manner. As described above, the decoding circuit of the present invention converts the run length M of character information etc. into M-a(N+1)
When decoding a binary code signal such as an MH signal encoded by a serial combination of a code corresponding to a(N+1) and a code corresponding to n when +n
Using the parallel conversion output of the MH signal as an address, sequentially derive binary codes corresponding to the above a and n, and indicate which of the above A and n the binary code output corresponds to. Since decoding is performed using a memory configured to derive the output, it is necessary to provide separate decoding memories for the MH code with run length n and the MH code with run length a(N+1). Therefore, this type of decoding circuit can be realized at low cost, and is suitable as a decoding circuit in a signal compression circuit such as a fatanmiri device.

[Brief explanation of drawings]

The drawing is a circuit block diagram showing one embodiment of the decoding circuit of the present invention. 2: Shift register for parallel conversion, 3: Memory for decoding, 4, 6, 8: 1 bit extraction circuit, 5, 7: 1st
2nd counter, 10: flip-flop, 12: output shift register.

Claims (1)

[Claims] 1 Run length M of character information, etc. M=a(N+1)+
n (where a is zero or a positive integer, n is an integer such that 0≦n≦N), when a=0, only the code corresponding to n is assigned, and when a≧1, a( A circuit for decoding a binary code signal such as a modified Huffman signal encoded in such a manner that a serial combination of a code corresponding to N+1) and a code corresponding to n is assigned, the circuit comprising: A shift register for serial-to-parallel conversion of the value code signal and the parallel output of this shift register are used as addresses to sequentially derive binary codes corresponding to the above a and n, and the binary code outputs are the same as the above a and n. A decoding memory configured to derive a judgment output representing which one corresponds, and each of the above binary codes corresponding to a and n from this memory in accordance with a judgment signal from the memory. The first and second
a counter, and a first and second
The circuit includes a circuit that starts the counting operation of the counter and stops the counting operation when both counters reach a predetermined state, and a circuit connection that takes out the clock pulses counted by the first and second counters as a decoded output. decoding circuit.