JPS5831676B2 - Storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to reading information from a storage device, particularly a ROM device (read-only memory), etc., and in particular realizes high-density and high-speed response of arrayed sense lines in a highly densely configured storage section. It also provides a new means for connecting selected sense lines to a sense common bus.

Conventional ROM devices using semiconductor integrated circuits (ICs) include those using diodes as storage elements and various other types, but in recent years, ROM devices using MOS transistors that can achieve a high integration ratio have been increasingly used.

As a method of arranging memory elements, as shown in Fig. 1, MOS
A system has generally been used in which the source of the transistor 1 is grounded, the gate is connected to the row line of the row address circuit 2, and the drain is connected to the column line of the column address and sense circuit.

This method was unsuitable for high density because it required row address lines and ground lines to be arranged alternately.

In addition, as shown in FIG. 2, in order to achieve higher integration and lower power consumption, the column address circuit 4 and the sense circuit 5 are separated to provide a column line and a sense line, and the source of the transistor 1 is connected to the column line, A method has also come to be used in which the drain is connected to the sense line, the gate is connected to the row line, and only the column line to be selected is grounded.

In this method, for example, when one column line is grounded, the left and right memory cells are simultaneously grounded, so the number of drive wirings is significantly reduced compared to the case of FIG. 1, which is convenient for high density.

In recent years, the capacity of ROM etc. has been increasing more and more, for example, 6
4, bit ROM etc. are being realized.

In these ROM devices, storage elements are arranged in an XY matrix, so if there are 64 bits, for example,
The X and Y element configuration is 256×256.

Therefore, for example, if one word has an 8-bit configuration, these 8
Even if each bit is assigned to each Y row, each bit must be able to select only one of the 32 bits in each Y row.

Therefore, unless these Y-row selection means can be constructed with dimensions comparable to the Y-direction dimensions of the ROM constituent elements, the Y-row selection means will increase the size of the entire ROM device.

This is because the dimensions of the means for selecting the Y rows on at least one side determine the dimensions of the Y rows of the matrix arrangement.

The configuration shown in FIG. 3 can be considered as one means for solving these problems.

That is, FIG. 3 takes a 64-bit ROM as an example, and each of the 8 bits is Y.

- The case where it is assigned to line 77 is shown.

Sense circuit. , bl to b7 are each 8-bit 2
The information in the bit~21bit~27bit part is Y.

This is the circuit extracted from row Y7. In addition, Y in Figure 3.

Although only four memory cells are shown in the -77th row in the X direction, it actually consists of, for example, 32 memory cells.

M1 to M4 are each Y.

~Memory cells in row Y7, SW1 to SW7 are Y selection circuit 6
This is a switch circuit that is turned on and off by

Now, when trying to select memory M1, the row address circuit 2 sets the gate of memory M1 high, the Y selection circuit turns on SW4 and SW7, and the VDD-8W7
-8W4-Ml - Flow current through the ground loop and read the 2° bit information from the sense circuit bo.

Similarly, the information of the 21st to 27th bit portions is simultaneously read by the sense circuits b1 to b7.

In the configuration shown in Fig. 3, Y rows corresponding to each bit are grouped into one group, and desired information is grouped by short-circuiting parts other than the Y lines to be selected for each Y line in this group. However, the third
In the example shown in the figure, 256 memory transistors are connected to the Y line (sense line), and it has a large capacitance CY.

That is, the parasitic capacitance CY inside the IC of each Y line is superimposed on the output to be detected, resulting in 4 CY in the example of FIG.

Since such a large parasitic capacitance acts on the output, high-speed response cannot be expected.

In view of these problems, the present invention provides a high-speed, high-density storage device.

FIG. 4 shows a semiconductor integrated circuit RO according to an embodiment of the present invention.
The configuration of M is shown.

In the figure, the column address circuit 4 corresponds to Y in FIG.

, Yl, and the portions corresponding to Y2 to ¥7 are omitted.

The memory elements (M, , 11~) are MOS transistors in this case, and their gate electrodes are connected to the row lines (r4□~), and when the information at that address is "111", the source , the drain is the husband column line (C4, ~
), is connected to the sense line (B4, ~ ), and the information is °O''
When , it is not connected.

Suppose now that the column address circuit 4 selects only C41 to be at a low level, and the row address circuit 2 selects only r41 to be at a high level.

At this time, MO3I-transistors M4111 and M411
□ is selected, sense lines S41 and 842 and column line C
A transistor Q41.4 acts as a switch controlled by Q41.4. Through Q42, the sense common bus S B4.
.

Set it to 5B42worou level.

R413 and R42 are for setting the sense line and sense common bus line to high level when there is no storage transistor at the selected location.

Here, the information obtained by the sense circuits 10 and 11 corresponds to 2° bit and 2' bit, respectively.

In this way, with a switch controlled by a column line,
Only the selected sense line is sensed by the common bus line 5B41. S
Since it is connected to B4□, the parasitic capacitance mainly consists of the drain capacitance C8 of the storage transistor connected to the sense line and the capacitance C8B of the sense common bus line, and the parasitic capacitance can be significantly reduced.

FIG. 5 shows another embodiment of the switch section of the present invention.

In this case, the switching transistors (Q, 1~) are n-
It is a channel type transistor, and the column line (C5, ~
) is selected at low level, so the transistor (T5
1~) and the resistance (R511~).

In Fig. 5, (B5.~) is the sense line, R50, R
5□ corresponds to R419R4□ in FIG.

FIG. 6 is a schematic diagram of an IC pattern of the switch section of the present invention shown in FIG. 4.

Transistor source/drain regions (B4.~), gate electrodes (041~), wiring (841~, C41)
~SB1°SB2) and contacts to the wiring (indicated by square symbols) are shown.

To explain FIG. 6 in correspondence with the transistor symbols in FIG. 4, B41 is the toruin of Q41, B439 B4
5 M... are respectively Q4□ and Q435 Q44 and Q45. Drain of...B42°B44.・
...are respectively Q41 and Q431, Q4□ and Q44.
Corresponds to the source of...

With such a pattern arrangement, the source region and drain region of each transistor can be shared by two transistors, and the element density in the integrated circuit can be increased.

In Figures 4 and 6, the case where there are two 2-bit sense common bus lines has been explained, but for example, in the case of 4 bits, C41 and C
43・C42 and C44・C45 and C47・C46 and C4
8,... (C44 and above are not shown in the figure.

), each column line is grouped every other column, and in the example of FIG. 6, G41, G43. C42 and C44...
If they are connected in common, a similar configuration can be achieved.

For example, in the case of 8 bits, C41, C43, and C4
5 and C4□, C4□ and C44, C46 and C48,...
This can be similarly easily achieved by grouping column lines like this.

As described above, according to the present invention, the information of the sense line selected by selecting the column lines, sense lines, and column lines that are arranged alternately is sent to the sense common bus through the switch controlled by the column line. By connecting the sense lines, the parasitic capacitance of multiple sense lines is not superimposed as in the past, and a high-speed ROM device can be realized. Also, unlike in the past, a separate decoder is not required to switch the output of the sense lines. Since it is possible to achieve higher density more easily.

Further, as shown in FIG. 6, the transistors serving as switches controlled by the column lines each have a source.

Since the drain region is shared, the memory transistors of the ROM device, which were conventionally dominated by the area of these regions, can be configured with higher density.

[Brief explanation of the drawing]

1 and 2 are circuit diagrams showing the arrangement of storage elements in a conventional ROM device, FIG. 3 is a circuit diagram showing a Y row decoding method according to the conventional method, and FIG. 4 is a circuit diagram showing the arrangement of storage elements in a conventional ROM device. A circuit diagram of a semiconductor memory device in which a sense line is connected to a sense common bus line by a controlled switch, FIG. 5 is a circuit diagram showing another embodiment of the present invention, and FIG. 6 is an IC pattern of a memory device according to the present invention. FIG. 2...Row address circuit, 4...Column address circuit, 10, 11...Sense circuit,
r41~...Row wire, S41~...Sense M1. , S B41 , S B42...Common bus bar, M411,...Storage element, Q41...
...transistor switch.

Claims (1)

[Scope of Claims] 1. Column lines and sense lines are arranged alternately in one direction, a memory element is connected between the column lines and the sense lines, and row lines and column lines arranged in the other direction are provided. A memory device characterized in that an output is determined by information at an address selected by a row line and a row line, and each sense line is connected to a sense common bus line through a switch controlled by a column line. 2. The switch shall connect the sources of one set of MOS transistors and the drains of the other set in common, connect the sense line to one common connection, and connect the other common connection to the sense common bus line. The storage device according to claim 1, characterized in that: 3 Arrange the column lines so that every other column line is connected to form a group, and connect the sense lines located on both sides of the column lines of each group to multiple lines via switches commonly controlled by the column lines of each group. 2. The storage device according to claim 1, wherein the storage device is connected to a sense common bus.