JPS5831798B2 - Transmission delay variation control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a transmission delay variation control method for suppressing transmission delay variation on the receiving side in a digital communication system that performs time division multiplex transmission in units of blocks.

In a digital communication system that packetizes only the significant part of an audio signal and transmits it by time division multiplexing, processing time for packetization on the transmitting side, delay time due to transmission buffer,
The delay time of the transmission path fluctuates depending on various conditions, which causes the arrival time of packets at the receiving side to fluctuate, causing fluctuations in the received signal and significantly deteriorating the quality of decoded audio. Become.

In order to absorb such fluctuations in the received signal, it would be sufficient to provide a buffer memory on the receiving side, but this has the drawback that its capacity becomes extremely large, making the structure uneconomical.

The present invention improves the conventional drawbacks as described above, and aims to absorb transmission delay fluctuations between the transmitting side and the receiving side with an economical structure.

A detailed explanation will be given below with reference to the drawings. FIG. 1 is a block diagram of the main part of a transmitting section of a digital communication system that performs time-division multiplex transmission in units of blocks. Data in units of blocks, which are packetized significant parts of audio signals, is transferred to a transmission buffer memory SQB via a bus BUS. added to.

For example, when transmitting 512 channels of data over a 92 channels high-speed transmission line, the transmission buffer memo'J S Q
B has a data storage capacity for 16 blocks #0 to #15, and is a FIFO (First In First Out) that is output in the order of input block data.
) method.

The data read from the transmission buffer memory SQB is supplied with signals such as a synchronization signal and a block number (channel number) applied via the signal line 5YBN to the multiplexer M.
It is added at the PX and sent out to the transmission path.

In the sending buffer memo IJSQB, as shown in Figure 2a,
When data A and B in blocks are input and accumulated, data B is immediately sent out after data A, but as shown in Figure 2, data A is followed by data C.
, D, ...... are input, and then data B is input and stored, then data A is followed by data C,
Data B will be sent out after data D, . . . are sent out.

Therefore, a delay variation occurs due to the transmission buffer memory SQB of data B when viewed from data A.

When focusing on one block constructed in this way, the time variation between it and other blocks is equal to the capacity of the transmission buffer memory IJSQB, that is, the maximum 1
There will be 6 blocks.

This accounts for a large portion of the delay variation.

FIG. 3 is a block diagram of the receiving section according to the embodiment of the present invention. 5REC receives the signal transmitted from the transmitting section via the transmission line, extracts the synchronization signal, block number, etc., and performs speed conversion, etc. The reception processing unit TSM is a memory that exchanges time slots. For example, when time division multiplex transmission of 92 channels is performed, the TSM is a memory that exchanges time slots.
It has a data storage capacity of 28 blocks.

C0NT is a control unit that processes exchange information and controls each part.VSM is a control unit that stores exchange information and is read out sequentially.CNT1 counts the timing of blocks and stores them. A counter whose count content is the write address of the memory TSM; Ml is a first memory which stores the count content of the counter CNT1, that is, the write address of the memory TSM, with the block number extracted by the reception processing unit 5REC as the address; Ml is a second memory that transfers and stores the contents of the first memo IJM1 after a predetermined time, REGl is a register that sets the maximum delay variation value, and REG2 is a correction parameter 4.
1.42 register, SUB is subtraction circuit, CM
P is a comparison circuit, and CNT2 is a counter that counts the clock CLK.

Assuming that this receiving section accommodates 512 channels,
Memories M1, M1, and VSM have areas for 512 channels, and when the count content of counter CNT1 is "2", data DATA whose block number VCN is K will be written to address 2 of memory IJTSM. , and the count value "2" of the counter CNT1 is written to the address of the first memory M1.

In the transmitting section, when no data is stored in the transmitting buffer memory SQB, control blocks are transmitted.

This block is called a fill-in synchronous 7" lock, and since there is no waiting in the transmit buffer memory IJSQB and there is only a delay in the transmission path, it will arrive at the receiving unit in the minimum time. .

The maximum delay variation value F is set based on this arrival time to absorb delay variation.

Block number VCNn of the fill-in synchronization block mentioned above
is extracted by the receiving unit 5REC and added to the subtraction circuit SUB, and the number of blocks corresponding to the maximum delay variation value F set in the register REG1 is subtracted.

The maximum delay variation value F is 16 in the transmission buffer memory SQB.
If we take the time for 18 blocks by adding two blocks to allow for blocks, then in 512 channels, it will take 100 minutes.
Since this corresponds to the time for the channel, F=100 is set in the register REG1.

The calculation result of VCN n100 in the subtraction circuit SUB becomes one input of the comparison circuit CMP, and the other input becomes the count contents of the counter CNT2 to determine whether or not synchronization is achieved.

The determination in the comparison circuit CMP is that, assuming that the count content of the counter CNT2 is P, synchronization is established when the following conditions are satisfied.If it is determined that the synchronization is not established, the counter CNT2 is set to VCNn- F is set and incremented by clock CLK.

In reality, the correction parameter AI of register REG2 takes into account deviations during stepping.

Using J2, The synchronization is determined by the following.

In the synchronized state as described above, after the address "2" in the first memory M10 is written,
After a time corresponding to F, the count contents of counter CTN2 become K, and the second memo 'JM
It is written to address 2.

K as exchange information at address i of exchange processing memo IJVsM
is stored, it is read at the read timing of address i and becomes the read address of the second memory M2, and "2" is read from the address of the second memory M2, and this "2"
Since this becomes the read address of the memory TSM, the data at the block number is inserted into the l channel and sent out.

As described above, the contents are transferred to either the first memory M1 or the second memory M2 after the maximum delay variation value F has elapsed;
Since the block-based data DATA is sent out after the maximum delay variation value F from the data sent out before it, the delay variation is absorbed.

Also, in the above embodiment, the memo 'J T S M is 92
This is for distributing block-by-block data received on the high-speed transmission path of the channel to 512 channels according to the exchange information, but the data storage capacity is sufficient for 128 blocks, and the first and second memories M1 , M2 is 51
Although it has an area corresponding to 2 channels, only 7 bits per channel (addressing from 0 to 127) is required, so the overall memory capacity is smaller than that of a configuration that simply buffers data for 512 channels. This will result in a significantly smaller number.

As explained above, the present invention includes a memory IJTsM that stores information in units of blocks, a first memory M1 that writes an information storage address of the memory TSM using a block number as an address, and this first memory IJM1. A second memory IJM2 that transfers and stores the contents of the memory, and a counter CNT2 that counts the clock CLK on the receiving side and controls the transfer from the first memory M1 to the second memory M2,
The block number VCNn of the fill-in synchronization block that is sent when there is no waiting buffer on the sending side, and the value corresponding to the time that is larger than the maximum delay time of information from the sending part to the receiving part (for example, 100 in the case of 512 channels). The difference between the values is set in the counter CNT2, and the count contents of the counter CNT2 are stored in the first memory M1 and the second memory IJM.
2 and the contents of the second memory M2 as the read address of the memo IJTsM to absorb information delay fluctuations.It is economical because it is possible to absorb transmission delay fluctuations with a configuration with a small memory capacity. As well as being
Since the delay time is set based on the reception of the fill-in synchronization block, there is an advantage that delay fluctuations can be absorbed stably.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the main parts of the transmitter, and FIG. 2a is a block diagram of the main parts of the transmitter. b is an explanatory diagram of delay variation due to transmission buffer memory, 3rd
The figure is a block diagram of a receiving section according to an embodiment of the present invention. SQB is a transmission buffer memory, MPX is a multiplexer, 5REC is a reception processing unit, Ml, M2 are first and second memories, VSM is a memory for exchange processing, CNT1, CN
T2 is a counter, SUB is a subtraction circuit, CMP is a comparison circuit, REGl, REG2 are registers, TSM is a memory IJ
, C0NT is a control unit.

Claims (1)

[Claims] 1. In a digital communication system that time-division multiplex transmits information from multiple channels in blocks and with block numbers added, there is a memory that stores information in blocks, and a memory that stores information in blocks using the block numbers as addresses. a first memory into which an information storage address is written; a second memory into which the contents of the first memory are transferred and stored; and a clock that is incremented on the receiving side to transfer the contents from the first memory to the second memory. and a counter that controls the block number of the fill-in synchronization block sent when there is no waiting buffer on the sending side and a value corresponding to a time larger than the maximum delay variation value of information from the sending part to the receiving part. The difference is set in the counter, the contents of the first memory are transferred and stored in the second memory using the count contents of the counter as an address, and the information in units of blocks is stored using the contents of the second memory. A transmission delay fluctuation control method characterized by absorbing delay fluctuations in information transmission as a memory read address.