JPH0473817B2 - - Google Patents

Description

[Detailed Description of the Invention] Industrial Application Field The present invention provides a method for connecting PCM multiplex transmission lines to
The present invention relates to a drop/relay device for adding/dropping arbitrary channel signals in a multiplex transmission path.

Summary of the Invention The present invention is a branching and repeating device that adds/drops arbitrary channels of a PCM multiplex transmission path, and stores a received signal in a storage circuit once, and then stores the received signal in a storage circuit according to timing pulses output from a pulse generation circuit independent of the received signal. Branching a part of the signal read from the storage circuit,
Another channel signal is inserted into the remaining passing signals by an insertion circuit, and a new frame synchronization signal is inserted by the timing pulse output from the pulse generation circuit, and the signal is sent to the line. .

This has the effect of preventing a failure in one multiplex transmission line section from spreading to other multiplex transmission line sections.

Prior Art Conventionally, in order to drop or add an arbitrary channel signal from a PCM multiplex transmission line, the method shown in Fig. 3 or 4 was used.
The configuration shown in the figure is adopted. The configuration shown in Fig. 3 consists of two PCM multiplex converters 1 connected in cascade.
Once the multiplexed signal is separated into multiple channel signals,
The passing channels 2 are connected in cascade as they are, and the signals are multiplexed again together with the branching and adding channels 3 and sent out to the transmission path. In this case, since the multiplexed signal is once separated into channel signals and then cascaded at the channel level, the apparatus becomes complex and large-scale, and the relay quality deteriorates due to the cascade connection of channels.

The configuration of FIG. 4 is the input/output interface circuit 7.
In between, a branch circuit 5 and an insertion circuit 6 are connected in cascade, and any branch channel signal is branched from the branch circuit 5 to the channel input/output circuit, the pass channel signal is passed as a multiplexed signal, and the insertion channel signal is inserted. The circuit 6 inserts the signal into the corresponding time slot in the multiplexed signal. In this case, the circuit scale can be small, and no deterioration occurs due to relaying. However, if a fault occurs in the multiplex transmission section on the input side, there is a drawback that the fault spreads to the multiplex transmission section on the output side, as described below.

FIG. 5 is a block diagram showing a detailed example of the branching configuration of FIG. 4. That is, the output of the receiving circuit 9 is supplied to the branch circuit 12 and the synchronizing circuit 10, and the synchronizing circuit 10 establishes frame synchronization by the output signal of the receiving circuit 9, and generates a synchronizing pulse synchronized with the frame phase of the received signal. do. The pulse generation circuit 11 generates a branch circuit 1 based on the frame synchronization pulse.
2. Insertion circuit 13, frame pulse insertion circuit 14
The various timing pulses necessary for these operations are generated and supplied to them.

The branch circuit 12 uses the timing pulse inputted from the pulse generation circuit 11 to separate and extract an arbitrary channel signal, and branches and outputs the signal to the channel input/output circuit 8. The insertion circuit 13 inserts the channel signal inputted from the channel input/output circuit 8 into the time slot of an empty channel of the output signal of the branch circuit (signal other than the branch channel), outputs it to the frame pulse insertion circuit 14, and outputs it to the frame pulse insertion circuit 14. The insertion circuit 14 inserts a frame synchronization signal into the output of the insertion circuit 13 and sends it out to the multiplex transmission path through the transmission circuit 15.
Since the above-mentioned branch circuit 12, insertion circuit 13, frame pulse insertion circuit 14, etc. are all operated by timing pulses generated by the pulse generation circuit, the multiplex transmission line section on the input side becomes a failure and the synchronous circuit Since it cannot operate when 10 is out of synchronization, there is a drawback that the failure also spreads to the multiplex transmission line section on the output side.

Problems to be Solved by the Invention The present invention solves the above-mentioned conventional drawbacks and provides a branching and repeating device that prevents a failure occurring in a multiplex transmission line section from spreading to other sections.

Means for Solving the Problems A branching and repeating device of the present invention is a branching and repeating device that is connected to a PCM multiplex transmission line and performs drop-addition of arbitrary channel signals, and includes a receiving circuit that receives a PCM signal, and the receiving circuit. a synchronization circuit that establishes frame synchronization from the output signal of the receiver circuit; a storage circuit that temporarily stores the output signal of the reception circuit; and a storage circuit that is driven by the frame synchronization pulse output from the synchronization circuit 10 to perform writing in the storage circuit. A write counter that generates an address signal, a pulse generation circuit that generates timing pulses necessary for the operation of each part independently of the received signal, and a read address of the storage circuit that is triggered by the timing pulse output from the pulse generation circuit. a read counter that sequentially generates signals; a branching circuit for branching any channel signal among the output signals of the storage circuit to a channel input/output circuit; and a channel input/output circuit for branching the signal of the passing channel outputted from the branching circuit. an insertion circuit that inserts a signal of an insertion channel input from the insertion circuit; a frame pulse insertion circuit that inserts a frame synchronization signal into the output signal of the insertion circuit according to a timing pulse output from the pulse generation circuit; It is characterized by comprising a transmitting circuit that sends the output of the circuit to the line.

Embodiments of the Invention Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. That is, the output of the receiving circuit 9 is supplied to the memory circuit 16 and the synchronizing circuit 10, and the synchronizing circuit 10 generates a synchronizing pulse synchronized with the frame phase of the received signal using the output signal of the receiving circuit 9. The write counter (W counter) 17 is triggered by the frame synchronization signal and starts counting, and sequentially generates write addresses for the memory circuit 16. Therefore, the storage circuit 16 writes the input signal in synchronization with the frame phase of the received signal. On the other hand, the pulse generation circuit 11 has a built-in oscillator that is independent of the received signal, and this oscillator is used to operate the read counter (R counter) 18, branch circuit 12, insertion circuit 13, and frame pulse insertion circuit 14. A timing pulse is generated and supplied to each. The read counter 18 starts counting starting from a timing pulse indicating the frame phase supplied from the pulse generating circuit 11, generates a read address signal for the memory circuit 16, and supplies the read address signal to the memory circuit 16. Therefore, the multiplexed signal read out from the storage circuit 16 with a frame phase independent of the received signal is input to the branch circuit 12.

The branch circuit 12 uses the timing pulse inputted from the pulse generation circuit 11 to separate and extract an arbitrary channel signal, and branches and outputs the signal to the channel input/output circuit 8. The insertion circuit 13 inserts the channel signal input from the channel input/output circuit 8 into the time slot of an empty channel of the output signal (signal other than the branch channel) of the branch circuit 12, and outputs it to the frame pulse insertion circuit 14. Pulse insertion circuit 1
4 inserts a frame synchronization signal into the output signal of the insertion circuit 13 and sends it out to the multiplex transmission path through the transmission circuit 15. In this embodiment, the above-mentioned branch circuit 1
2. Insertion circuit 13, frame pulse insertion circuit 14
etc. are all operated by the timing pulses generated by the pulse generation circuit 11, so the synchronization circuit 1
Even when 0 occurs out of synchronization, the frame pulse insertion circuit 14 continues to send out a multiplexed signal including a frame synchronization signal. However, since the received signal of the receiving circuit 9 is random, the passing channel will of course be a failure, but synchronization in the multiplex transmission path section on the transmitting side has been established, and the drop/add channel will not be a failure. Does not occur.

FIG. 2 is a time chart showing signals of various parts for explaining the operation of this embodiment. Now, assuming that the PCM multiplex transmission line as shown in Figure A is input to the receiving circuit 9, the synchronization circuit 10 outputs a synchronization pulse as shown in Figure B at the beginning position of each frame of the received signal. be done. Therefore, the memory circuit 16
From address 0 to address 24, for example, channels 1 to 2 follow synchronization pattern F, as shown in Figure C.
4 channel signals are written. On the other hand, the pulse generating circuit 11 supplies a multi-frame pulse as shown in FIG. . Therefore, the output of the storage circuit 16 becomes a signal with a frame phase independent of the received signal, as shown in FIG. It is easy to branch any channel signal from the output of the storage circuit 16 by the branch circuit 12 and to insert any channel signal by the insertion circuit 13. These branches,
Since all insertions are performed in accordance with the timing pulses output by the pulse generation circuit 11, the frame synchronization pattern F is output from the frame pulse insertion circuit 14 even during a period when a failure occurs on the receiving side.
is always sent normally (E in the same figure). At this time, it is desirable to hold all the contents of the memory circuit 16 at "1" in order to prevent bit synchronization information from being lost in the subsequent section.

Further, when the failure is recovered, the synchronization circuit 10 establishes synchronization using the received signal and triggers the write counter 17, thereby causing the memory circuit 16 to be 0
Of course, by writing each channel signal in order starting from the address, a channel in which a failure has occurred can also be recovered.

Effects of the Invention As described above, in the present invention, an input signal is written into a memory circuit by frame synchronization established from a received signal, and reading from the memory circuit 16 is performed by an oscillator independent of the received frame phase. Readout is performed according to the created independent frame phase, an arbitrary channel signal is branched from the readout signal, and an insertion channel signal is placed on an empty channel and sent out, and the frame synchronization signal also follows the timing pulse of the pulse generation circuit. Since the configuration is configured such that the load is loaded at the beginning of the transmission frame and transmitted, it is possible to prevent the synchronization of the output side multiplex section from being disrupted due to the use of the input side multiplex section and the failure spreading. There is.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a time chart showing an example of the signals of each part of the above embodiment, FIGS. 3 and 4 are block diagrams showing an example of the configuration of a conventional branch repeater, and FIG.
This figure is a block diagram showing a detailed example of the configuration of FIG. 4. In the figure, 1: PCM multiplex conversion device, 2: relay channel, 3: branch channel, 5: branch circuit, 6: insertion circuit, 7: input/output interface circuit, 8: channel input/output circuit, 9: receiving circuit ,1
0: Synchronous circuit, 11: Pulse generation circuit, 12: Branch circuit, 13: Insertion circuit, 14: Frame pulse insertion circuit, 15: Transmission circuit, 16: Memory circuit, 1
7: Write counter, 18: Read counter.

Claims (1)

[Scope of Claims] 1. In a branching and repeating device that is connected in the middle of a PCM multiplex transmission path and performs branching/insertion of arbitrary channel signals, there is provided a receiving circuit that receives a PCM signal, and frame synchronization from the output signal of the receiving circuit. a storage circuit for temporarily accumulating the output signal of the receiving circuit; and a write counter driven by a frame synchronization pulse output from the synchronization circuit to generate a write address signal for the storage circuit. , a pulse generation circuit that generates timing pulses necessary for the operation of each part independently of the received signal, and a read counter that is triggered by the timing pulse output from the pulse generation circuit and sequentially generates read address signals for the storage circuit. , a branching circuit for branching any channel signal in the output signal of the storage circuit to a channel input/output circuit; and an insertion channel signal input from the channel input/output circuit to the passing channel signal output from the branching circuit. a frame pulse insertion circuit that inserts a frame synchronization signal into the output signal of the insertion circuit according to a timing pulse output from the pulse generation circuit; and a frame pulse insertion circuit that sends the output of the frame pulse generation circuit to a line. A branch relay device comprising a transmitting circuit.