JPS5832408B2 - sequence controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sequence controller equipped with a function of monitoring input/output elements, and its purpose is to monitor input/output elements during execution of sequence control operations without using advanced equipment such as a computer. It is an object of the present invention to provide a sequence controller having functions, and in particular, it is an object of the present invention to automatically determine the section of a sequence control program to be monitored according to the operating state of the sequence, and to set the starting point address and ending point address of the section. The objective is to obtain only the minimum amount of monitor information necessary to facilitate the investigation of the cause of failure.

With the development of sequence controllers that apply computer technology, it has become possible to monitor input and output elements using this sequence controller as an intermediary, and it has become possible to quickly and reliably discover failure points in controlled objects.

However, since monitoring can generally be carried out using a high-end computer, there is a problem in that the equipment is old-fashioned and expensive.

There are also known sequence controllers that can perform monitoring without using a computer, but these cannot perform monitoring unless the sequence control operation of the sequence controller is stopped. Since it was not possible to monitor the output elements, it was extremely difficult to reliably discover the location of the failure.

Furthermore, in the past, a monitoring program was required separately from the sequence control program, and this monitor program also had to be modified when the sequence was changed.

In order to eliminate such conventional problems, the present invention eliminates the need for a special monitor program by reusing a sequence control program as a monitor program. Automatically determines the section of the sequence control program that should be monitored, and stores the operating status (on, off state) of the specified input/output element as the minimum necessary monitoring result and the input/output element device number during sequence control operation. This system stores the signal status and device number stored in the device and displays them to help determine the true cause of the failure.

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a block diagram showing a schematic configuration of the entire sequence controller, where 1 is a main memory circuit such as a core memory that stores sequence control data of sequence cycles programmed in advance, and 2 is a memory address of the main memory circuit 1. A program counter that sequentially reads specified control data; 3 is a memory data register that stores the control data read from the memory address specified by the program counter 2; 4 is a control stored in the memory data register 3; An instruction register 5 to which data is set via the data bus DB is a memory gate that controls setting of the control data to the instruction register 4.

The command word used as the control data is composed of an operation section indicating the type of command ♦, and an address section specifying an address of an internal input/output element, a memory address of the main memory circuit 1, etc., which will be described later.

The types of instructions include on-off from internal input/output elements.
Input/output test commands that perform logical operations on OFF input signals, output commands that turn on and off output elements among internal input/output elements based on the results of logical operations, jump instructions and monitors that cause jumps based on the results of logical operations. There is a special life cold used in the Linda program.

Table 1 shows the types of command words and their meanings.

Reference numeral 6 denotes an instruction decoder which decodes the operation part of the control data set in the instruction register 4 and issues various command signals.

Reference numeral 10 indicates an external input element 10a1, such as a limit switch or a push button switch, which is turned on and off by checking the operation of each operating element of the controlled device such as a machine tool, and an external input element 10a1 that instructs the operation of each operating element of the controlled device. On-
This is an external input/output element group consisting of external output elements 10b such as output relays and solenoids that are turned off.

Numeral internal input elements 11a1 and respective external outputs are paired with each external input element 10a and convert the on-off operating state of the external input element 10a into an input signal in the form of an electrical signal at an internal level of the sequence controller. element 10
a large number of output elements that are paired with the external output element 10b and turn on and off the external output element 10b in response to an internal level output signal; This is an internal input/output element group consisting of a large number of internal output elements 11b such as timer elements, relay elements, dummy elements, etc. that operate in response to the input signal.

Reference numeral 12 denotes an internal input/output element 11a at an address specified by the control data from among the internal input/output element group 11.

Input selector 12a1 output selector 1 to select 11b
2b, and the on/off state of the selected internal input/output elements 11a and 11b is an input signal of H'' when it is on and 'L' when it is off.
The signal is sent out from the output terminal of the input selector 12a onto the line IT and applied to the logic operation circuit 143.

In particular, if the control data is the output unit ♦, the output signal sent from the logic operation circuit 14 via the line OT is set to the internal output element 11b selected by the output selector 12b.

The logic operation circuit 14 of this embodiment receives various command signals decoded by the instruction decoder 6, and if this command signal is an input/output test command, the line IT
The on-off input signals from the internal input/output elements 11a and 11b inputted through If it is an output command, the on-off output signal based on the memorized test result is sent to line O.
It is designed to be sent to T.

15 is a control pulse generation circuit that generates clock pulses and control pulses for timing the execution of each instruction, etc.;
In this embodiment, the lock pulse CL and control noculus OP are as shown in FIG.

Control pulses CL1 to CL6 are generated periodically, and the execution of the - command ♦ is carried out in one control pulse period from when this control pulse OP is issued until when C16 is issued.

16 is a control circuit for the main memory circuit 1; 17 is a gate at a memory address specified by the program counter 2; 18 is a save register that stores the memory address of the program counter 2 when a subroutine jump instruction is given; 19-
Reference numeral 23 denotes a gate that is opened and closed by the control pulse to execute a predetermined command.

100 is an ordinary sequence controller (a circuit added to this) to achieve the above-mentioned monitoring;
As shown in FIG. 2, this circuit 100 includes means 155 and 156 for setting a starting point address and an ending point address according to the result of determining the section of the sequence control program to be monitored;
It is composed of means 153 for enabling monitoring while the sequence system program for the set section is being executed, storage means 130 for storing the monitoring results, and display means 144 for displaying the contents stored in the storage means. Ru.

Note that 30 in the program list shown in FIG.
Monitor section determination program after address 0 and circuit to enable this program 150.151.152,1
It has 54.

The configuration of each part will be explained below based on FIG. 2.

Reference numeral 101 is a register for an abnormal circuit number that stores numerical data input from the data input terminal when a pulse is input to the load signal input terminal, and the address of the control data set in the instruction register 4 is stored at the data input terminal. The load signal input terminal is inputted to the instruction decoder 6 (
The special base ◆ABN decoded by the iron and the control pulse CL5 are inputted via the AND gate 102.

Reference numeral 103 denotes an abnormal circuit number display for externally displaying the contents stored in the register 101.

Reference numerals 104, 105, and 106 are respectively a push button switch for sequentially clearing the counter, a push button switch for sequentially adding the counter, and a push button switch for external command to start monitoring.

154 is a push button switch 10 for external command to start monitoring.
6, the first flip-flop 150 is set by the first flip-flop 154, and the second flip-flop 7'' is set by the signal ABN given from the control data.151 is the starting point address of the section to be monitored in a series of programs. a third flip-flop, 1, which issues a gate signal for setting the register 155;
Reference numeral 52 denotes a fourth flip-flop which generates a data 1 signal for setting the end point address of the interval to be monitored in a series of programs in the register 156.

These flip-flops constitute a part of the monitor section discriminating means.

A monitoring start flag circuit 153 is kept set while the signal state of the input/output element group 11 is to be monitored, and detects a match between the register 155 where the starting point address is set and the memory address specified by the program counter 2. It is set by the output signal of the comparator 157, and reset by the output signal of the comparator 158 which detects a match between the register 158 where the end point address is set and the memo address designated by the program counter 2.

Reference numeral 111 denotes an issuing diode for displaying monitoring permission that lights up when the first flip-flop 154 is set, and the Q terminal output of the first flip-flop 154 is inputted through the inverter 112.

Reference numeral 115 denotes a sequential counter that switches the memory address of the auxiliary storage circuit 130 that stores the signal state of the input/output element as a monitoring result, and the clear pulse signal generated by the push button switch 104 is input to the clear terminal CL, and the addition terminal UP4 While the monitoring start flag circuit 153 is set, a control pulse CL6 is inputted through the AND gate 118 and the OR gate 117 and advances, thereby switching the memory address of the auxiliary storage circuit 130.

A memory address display 119 externally displays the contents of the sequential counter 115, and the contents of the sequential counter 115 are inputted thereto.

120 is a line I from the output terminal of the input selector 12a.
On T (this sent internal input/output element 11a.

The on-off input signal of 11b is sent to the logic operation circuit 14.
Separately from (this, input/output test command ◆TNA.

An input/output test circuit that tests with TFA, TNO, and TNE, and outputs a nHn signal as a test result if the on-off input signal satisfies the conditions of the input/output test command, and if it does not, outputs an LI+ signal as a test result. So, this circuit 12
The AND gate 121 that constitutes 0 has an OR gate 125.
Test commands ◆TNA, TNO, TNE and internal input/output elements 11a, 11 being sent out on line IT via
The on-off input signal of b is input, and the AND gate 12
2 (Test life 4 yen-TF via or gate 126
A.

TFO, TFE are input, and the on-off input signals of internal input/output elements 11a, 11b sent out on line IT are input via inverter 123, and the outputs of both analogues 1121 and 122 are the OR game. -N2
It is designed to be output via 4.

Regarding this auxiliary memory circuit 130, in which the test result output of this input/output test circuit 120 and the connection address of the corresponding input/output element are stored in the auxiliary memory circuit 130, the input of the read/write instruction terminal R/W is Sometimes the data input terminal Dine is input H11, 41L? +The state and the connection address of the corresponding input/output element are written to the memory address specified by the address designation signal input to the memory address input terminal ADD, and the input of the read/write instruction terminal R/W is set to H''
At this time, the contents written in the memory address specified by the address designation signal input to the memory address input terminal ADD3 and the input/output element connection address are output to the data output terminal Dout. Ru.

The address part of the control data is inputted to the data input terminal of the register 155 via the line AD, and the Q terminal output of the third flip-flop 151 and the control pulse CL4 are inputted to the load signal input terminal via the AND gate 164. The address part of the control data is input to the data input terminal of the register 156 from the line AD.
The fourth load signal is input to the load signal input terminal.
The Q terminal output of the flip-flop 152 shown in the figure and the control pulse CL4 are inputted via an AND gate 165.

The register 155 is connected to one input terminal of the comparator 157.
The output of the program counter 2 is input to the other input terminal, the output of the register 156 is input to one input terminal of the comparator 158, and the output of the program counter 2 is input to the other input terminal G. It is now possible to do so.

FIG. 5 shows an example of the program.

In this program, memory addresses 1 to 277 are a sequence control program, and memory addresses 300 to 370 are a monitor section discrimination program for determining the section of the sequence control program to be monitored.

In particular, memory addresses 100 to 177 are sequence control programs that execute the startup circuit shown as an example of the sequence circuit in FIG.
is a determination program for determining the startup circuit as an interval to be monitored, and memory addresses 310 to 317 are determination programs for determining other sequence circuits, such as unit advance cycle circuits, as an interval to be monitored.

The operation of this embodiment will be explained with reference to FIG.

When monitoring is to be performed, the operator presses the monitoring start external command push button switch 106 to set the first flip-flop 154.

If the first flip-flop 154 is set, a signal is given to the specific address 3770 of the input selector 12a, and the test result at memory address 300 satisfies the condition, and the monitoring program from memory address 302 onwards is executed.

In the monitoring program, memory address 302
Check the startup circuit using the control data TFAO100G, and if the condition is satisfied (when the startup circuit is OFF), execute the program at memory address 304 and below to obtain the control data ABNa.
Storm 1 is displayed on the display 103 by OO01, and the second and third flip-flops 150 and 151 are set by the special table ◆ABNa by the control data ABNa0001 at the time when the control pulse CL5 is generated.

The program counter 2 is incremented by 1 and becomes 0305 by the last control pulse CL6 of this control pulse cycle, and the control data N0P0100 at the memory address 305 is read out and the instruction register 4 is set.

Since the third flip-flop 151 is set, the control pulse CL4 is generated and the control data N0, which is the starting point address of the section to be monitored, is stored in the register 155.
The address field 0100 of PO100 is set.

Then, the fourth flip-flop 152 is set by the next (7) control Ll] Hals CL5, and the next control pulse CL
4, the address part 01 of the control data N0PO114, which is the end point address of the section to be monitored, is stored in the register 156.
14 is set.

The third and fourth flip-flops 151 and 152 are reset by the control pulse CL5, respectively.

Next, the control data JMPOOOO at memory address 307 is executed (thereby jumping to memory address 0, the sequence control program is executed again, and the controlled object is sequence-controlled).

When the sequence control program is executed in this way and the content of the program counter 2 becomes 0100 again, the comparator 15
Since the human power data inputted to 7 match, a match signal is output from the comparator 157.

At this time, since the flip-flop 154 is still in the set state, the monitor start flag circuit 153 is set by the next control pulse CL2.

When the sequence control program progresses further and the contents of the program counter 2 become 0114&, the comparator 158
Since the human power data inputted to the two match each other, a match signal is outputted from the comparator 158.

Therefore, the monitor start flag circuit 153 is reset by the next control pulse CL5.

While the flip-flop 153 is set, the contents of the sequential counter 115 are incremented by 1 every time the control pulse CL6 is generated, and the contents of the auxiliary memory circuit 1 are incremented by 1 every time the control pulse CL4 is generated.
The memory address (
The data input to this data input terminal Din, that is, the address part of the control data and the output of the input/output test circuit 120 are written.

In this way, the control data TNA0001 to TFAO10 stored in memory addresses 100 to 114 of the main memory circuit 1
Address parts 0001 to 0101 indicated by 1,
and test results based on the control data are sequentially written into the auxiliary storage circuit 130G.

This stored content can be displayed on the display 144 by operating the pushbutton switches 104 and 105.
The operator investigates the cause of the failure based on the operating status of each input/output element.

What is displayed on the display 144 is the signal state immediately after the occurrence of the abnormality, and since it includes the signal that caused the true failure, the cause of the failure can be easily investigated.

On the other hand, when a match signal is output from the comparator 158, the second
The first flip-flop 150 is reset, which further resets the first flip-flop 153.

Therefore, from now on, the monitoring program will not be executed and only the sequence control program will be repeatedly executed until the first flip-flop 154 is set by the push button switch 106 again.

It should be noted that the test result for the memory address 302 is unsatisfactory (
If the startup circuit is ON and normal), a jump instruction from memory address 303 causes the program to jump to memory address 310 and check the next sequence circuit.

If there is no abnormality in the next sequence circuit 0, then ζ checks the next sequence circuit, sequentially searches for a sequence circuit with an abnormality, and sequentially determines the interval to be monitored.

As is clear from the above description, the present invention automatically determines the section of the sequence control program that should be monitored due to the occurrence of an abnormality during the sequence operation of the controlled object, and determines the starting point address and ending point address of the section to be monitored. The operating status of input/output elements is monitored based on part of the sequence control program, so it is not only possible to investigate the cause of the failure based on the signal status immediately after an abnormality occurs, but also to monitor the operating status of input/output elements based on part of the sequence control program. The cause can be easily investigated based on the signal status of the number of points determined.

Furthermore, since a part of the sequence control program is used as the monitor program, there is no need to change the monitor program in response to a cycle change.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of the sequence controller according to the present invention, FIG. 2 is a detailed diagram of the monitoring circuit 100 shown in FIG. 1, FIG. 3 is a timing chart of various control signals, and FIG. 5 is a sequence circuit diagram, and FIG. 5 is a diagram showing a program sheet in which a sequence control program and a monitor interval discrimination program are written. 1... Main memory circuit, 2... Program counter, 4... Instruction register, 14... Logical operation circuit, 10... External input/output element group, 11... Internal input/output element group,
12... Input/output selection circuit, 100...
Monitoring circuit, 101...Register, 10
3... Abnormal number display, 150,151°15
2.154...flipflop, 120...
...Input/output test circuit, 130...Auxiliary memory circuit, 134...Display circuit, 144...
・Display device, 153...Monitor start flag circuit,
155,156...Register, 157,158
...Comparator.

Claims (1)

[Claims] 1 Read pre-programmed control data sequentially from the main memory, take in input signals from the input elements specified by the read control data, perform logical operations, and output the output elements ζ specified by the read control data. On the other hand, in a sequence controller that sequentially controls a controlled object by providing an output signal based on the result of the logical operation, the operating state of the input/output element stored in the main storage device is checked to monitor the occurrence of an abnormality. a monitor section discriminating means comprising a monitor section discriminating program for discriminating the section on the program to be processed, and a start memory address data of the monitor section and an end point memory address data of the monitor section output from the monitor section discriminating means are respectively set. A start point address setting means and an end point address setting means, and an input/output specified by the control data read in the section from the memory address set in the start point address setting means to the memory address set in the end point address setting means. Auxiliary storage means for storing a signal state of an element or a corresponding input/output element device number together with this signal state; and a signal state of the input/output element stored in the auxiliary storage means or a corresponding input/output element device along with this signal state. A sequence controller comprising: display means for displaying a number.