JPS5855522B2 - sequence controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sequence controller having a function of monitoring input/output elements, and its purpose is to monitor input/output elements without using advanced equipment such as a computer and without having an interrupt function. The objective is to provide a sequence controller that can be monitored online.

With the development of sequence controllers that utilize computer technology, it has become possible to quickly and reliably discover faults in controlled objects using this sequence controller as an intermediary.

However, in the past, it was necessary to use a high-end computer, which resulted in a large loss of equipment and increased costs.Furthermore, online monitoring was only possible with a sequence controller that had an interrupt function. .

The present invention was proposed in view of such problems, and even if a conventional sequence controller does not have an interrupt function, it is possible to connect input/output elements online without using a high-end machine by simply adding a simple device. It is characterized by being able to perform monitoring.

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a block diagram showing a schematic configuration of the entire sequence controller that implements the present invention, in which 1 is a main memory circuit such as a core memory that stores sequence control data of sequence cycles programmed in advance, and 2 is a main memory circuit. 1 is a program counter that specifies a memory address and sequentially reads predetermined control data; 3 is a memory data register that stores the control data read from the memory address specified by program counter 2; and 4 is a memory data register 3. An instruction register 5 to which control data stored in the instruction register 4 is set via a data bus DB is a memory gate that controls setting of the control data to the instruction register 4.

The instruction word used as the control data is composed of an operation section that indicates the type of instruction, and an address section that specifies an address such as an address of an internal input/output element, a memory address of the main memory circuit 1, etc., which will be described later.

The types of commands include an input/output test command that determines the on-off state of an internal input/output element, an output command that turns on or off an output element among internal input/output elements based on the determination result, and an output command that turns on or off an output element among the internal input/output elements based on the determination result. There are jump commands that cause a jump, and special commands used in monitoring programs.

Table 1 shows the types of command words and their meanings.

Reference numeral 6 denotes an instruction decoder which decodes the operation part of the control data set in the instruction register 4 and issues various command signals.

Reference numeral 10 indicates an external input element 10a1, such as a limit switch or a push button switch, which is turned on and off by checking the operation of each operating element of the controlled device such as a machine tool, and an external input element 10a1 that instructs the operation of each operating element of the controlled device. On-
This is a group of elements that can be connected to the outside and includes an external output element 10b such as an output relay or solenoid that is turned off.

11 pairs with each external input element 10a and converts the on-off operating state of the external input element 10a into an electrical signal form at the internal level of the sequence controller. A large number of output elements that operate on and off the external output element 10b in response to an internal level output signal, and operate in response to an internal level output signal without directly exchanging signals with the external input/output element group 10. This is an internal input/output element group consisting of a large number of internal output elements 11b such as timer elements, relay elements, and dummy elements.

Reference numeral 12 denotes an internal input/output element 11a at an address specified by the control data from among the internal input/output element group 11.

Input selector 12a1 output selector 1 to select 11b
2b, and the on-off state of the selected internal input/output element 11a, Ilb is LHI+ when it is ON, and LPA when it is OFF, from the output terminal of the input selector 12a. The output signal sent out on the line IT, and especially if the control data is an output command, is sent out from the test flag circuit 14 through the line OT so that it is set to the internal output element 11b selected by the output selector 12b. It has become.

The test flag circuit 14 receives various command signals decoded by the instruction decoder 6, and if the command signals are input/output test commands, the test flag circuit 14 receives the command signals from the internal input/output elements 11a, 11b input via the line IT. −
Determine whether the off signal satisfies the test command condition and store the result, and if the command signal is an output command, send an on-off output signal to the line OT based on the stored determination result. It is designed to be output.

Reference numeral 15 denotes a control pulse generation circuit that generates control pulses for timing the execution of each instruction, etc. In this embodiment, control pulses OF, CLI to CL6 as shown in FIG. This control pulse O
This is done in one cycle from when P is issued until CL6 is issued.

16 is a control circuit for the main memory circuit 1; 17 is a gate at a memory address specified by the program counter 2; 18 is a save register that stores the memory address of the program counter 2 when a jump instruction is given; and 19-23 are This is a gate that is opened and closed by the control pulse to execute a predetermined command.

Reference numeral 100 denotes a monitoring circuit which forms the main part of the present invention, and a functional block diagram of this circuit 100 is shown in FIG.

First, to conceptually explain the function performed by this monitoring circuit 100, a group of input conditions including one output element for controlling the same is defined as a unit of operation, and the presence or absence of an abnormality is determined for each unit of operation. Based on this determination result, each input condition of the operation unit with the abnormality is examined in order on-line and stored in the monitor storage device 200, and this stored result is read and displayed off-line.

The operator is able to decipher the displayed content and find out the fault condition that caused the abnormality.

Here, the monitor program is divided so that it can monitor the input conditions for each operation unit and find failure conditions in the input conditions, and the operation that is determined to be abnormal by the discrimination program that determines whether there is an abnormality in each operation unit. A monitor program corresponding to the unit is selected, and the above-mentioned monitoring is performed.

In FIG. 7, 200 is a monitor storage device that stores monitoring results, 210 is a memory address switching circuit, and 220 is a memory address switching circuit.
control means.

The first control means 220 issues a monitor start command (switch 10
6 is given, the sequence control is switched to the execution of a determination program that determines the presence or absence of an abnormality for each operation unit.

Reference numeral 230 denotes a second control means, which enables the monitor storage device 200 and the memory address switching circuit 210 when it is determined that there is an abnormality in any operation unit by executing a determination program, and determines that there is an abnormality. The input test circuit 120 executes the monitor program for the determined operation unit.
The monitoring results given by the above are sequentially stored in the storage device 200.

Furthermore, when the monitor program ends, the memory device 200 and the memory address switching circuit 210 are disabled and the sequence control is returned to.

This achieves online monitoring without stopping scanning.

Reference numeral 240 denotes an abnormal circuit number display device, in which an abnormal circuit number corresponding to the operation unit determined as abnormal by the discrimination program is set and displayed.

250 is a display circuit for displaying the monitoring results stored in the storage device 200, which is displayed by manually switching the storage address switching circuit 210.

The operator will be able to read this and find the cause of the abnormality.

Next, details of each of the above-mentioned functional blocks will be explained with reference to FIG. 2.

The monitor storage device 200 is shown as a storage circuit 130, and the storage address switching circuit 210 is shown as a sequential counter 115.

The first control means 220 corresponds to the push button switch 106 and the D flip-flop 109, and by closing the switch 106, a command to start monitoring is given, and the D flip-flop 109 is set.

This set signal (Q terminal output) is applied to address 3770 of the input selector 12a.

As a result, the sequence control program (0
Subsequently to addresses 000 to 0277), the determination program for addresses 0300 and below is executed, and the presence or absence of an abnormality is determined for each operation unit.

If there is an abnormality in the startup circuit, the abnormal circuit number 0001 is set in the register 101 by the command at address 0304 and displayed on the display 103 as the abnormal circuit address display device 240, and the flag is set by the command 5ON3770 at address 0305. 107 is set.

The operand 3770 of this instruction selects the address 3770 of the output selector 12b in FIG. It will be set.

When flag 107 is set, gates 131 and 118
A signal is given to

By executing the startup circuit monitor program at addresses 0306 to 0316 in FIG.
The signal as a result of monitoring at 20 is also applied to AND gates 118 and 131 via inverter 125.

As a result, the memory circuit 130 and the sequential counter 115 are enabled only when the conditions of the test command are not satisfied, and data specifying the input/output element that does not satisfy the condition, ie, input/output address data, is stored in the sequential memory circuit 130.

End of the monitor program, i.e. instruction 5O at address 0317
The flag 107 is reset by F3770, and the next address instruction JMPOOOO returns to the sequence control program to continue scanning.

By resetting the flag 107, the sequential counter 115 can be manually incremented by the switch 105, and the monitor result can be read out and displayed on the display 134 as the display circuit 250.

Note that 111 is a light emitting diode for displaying a monitoring start command that lights up when the flip-flop 109 is set, and the Q terminal output of the flip-flop 109 is inputted through the inverter 112.

A memory address display 119 externally displays the contents of the sequential counter 115, and the contents of the sequential counter 115 are inputted thereto.

Reference numeral 120 denotes an input/output test circuit that tests whether the on-off states of the input/output elements 10a and 10b satisfy the conditions of the input/output test command. Internal input/output elements 11a, 11b being sent out on line IT
The on-off signal of the internal input/output elements 11a and 11b is inputted to the AND gate 122, and the test command TFA is inputted to the AND gate 122.
An off signal is inputted via an inverter 123, and the outputs of both AND gates 121 and 122 are outputted via an OR gate 124.

Therefore, if the conditions of the test command are satisfied, H′′,
If the condition is not satisfied, a signal of "TL t" is output as a determination result.

Reference numeral 134 denotes a display device for displaying input/output element address data output from the data output terminal Dout of the memory circuit 130.

Next, the operation of the sequence controller configured as described above will be explained with reference to FIGS. 3 to 5. The content of the program counter 2 is incremented by 1 by the control signal UPI generated when the control pulse CL6 is generated, and the control pulse C.L.
The gate 17 is activated by the control signal MST generated when 2 occurs.
is opened, and the control data at the memory address specified by the program counter 2 is read out and stored in the memory data register 3.

And the control signal C generated when the control pulse CL3 is generated.
The memory gate 3 is opened by M, and the control pulse C
The instruction register 4 is opened by the control signal 5GISR generated when L3 is generated, and the control data stored in the memory data register 3 is set in the instruction register 4.

When the control data is set in the instruction register 4 in this way, the address signal set in the address field is sent onto the line AD, and the internal input/output elements 11a and 11b at the address specified by the address signal are turned on/off. When it is on, it is sent out as an "H" signal, and when it is off, it is sent out on line IT as an "L" signal.

The control data set in the instruction register 4 is changed according to the program every time the control pulse CL3 occurs, and therefore the address signal sent on the line AD and the on-off signal sent on the line IT are changed by the control pulse. It will be updated every time CL3 occurs.

By controlling each circuit in this manner, the program shown in FIG. 5 is executed.

In executing this program, memory addresses 1 to 277
When the execution of the sequence control program stored in TNA3770 is completed, the control data TNA3770 at memory address 300 is
is read out, and the test flag circuit 14 determines whether the flip-flop 109 of the monitoring circuit 100 is set or not.

Therefore, if the flip-flop 109 is in the reset state, the control data JMNOOOO at the memory address 301 is executed to jump to the memory address 0, and the sequence control program is executed again, but the monitoring program is not executed.

When the operator desires to perform monitoring, the operator presses the push button switch 106 for external command to start monitoring and sets the flip-flop 109.

When the flip-flop 109 is set, the light emitting diode 111 for a monitoring start command is turned on.

Further, the push button switch 104 for clearing the sequential counter is pressed to set the content of the sequential counter 115 to O.

If the flip-flop 109 is set, the program does not jump to memory address O, but moves to address 302 and thereafter, and the discrimination program is executed.

In the determination program, the starting circuit is first checked.

That is, the control data TFAO100 at memory address 302
is read out and activated, and the test flag circuit 14 determines the on/off state of the internal input/output element (CR1) corresponding to IJ-CR1.

Since the starting relay CRI is a relay that is always on during normal operation, if it is off, it means that there is an abnormality in the starting circuit.

Next, control data JMN0321 at memory address 303 is executed.

Therefore, if relay CR1 is off, that is, if the starting circuit is abnormal, the control data AB at the next memory address 304
NO001 is read and monitoring of the startup circuit is started.

As a result, control data A is generated at the time when control pulse CL5 is generated.
The address field 0001 of BNO001 is set in the register 101, and the abnormal circuit number display 103 indicates that the starting circuit is abnormal.

461 is displayed. Next, the control data 5ON3770 of the memory number table 305 is read out, so that the flip-flop 107, which is a monitoring start flag circuit, is set at the time when the control pulse CL5 is generated.

In this case, since no input/output test command is output, the output of the input/output test circuit 120 is II L j+, and the output of the inverter 125 is H91.

Therefore, when the flip-flop 107 is set, the contents of the counter 115 are sequentially incremented by 1 and become 1 at the time when the control pulse CL6 is generated.

By reading the control data TNA0001 at the next memory address 306, numerical data 0001 specifying the input/output address of the internal input/output element is input to the data input terminal Din of the memory circuit 130, and the test circuit 120 receives the test command. TNA and internal input/output element (LS
2) on-off signal is input.

If the internal input/output element (LS 2 ) is on (normal), the test conditions are satisfied, so the test circuit 120
An H''' signal is output, and if it is off (abnormal), the test conditions are not satisfied, so the test circuit 120 outputs an L''' signal.

If the output of the test circuit 120 is 11 L 11, the input to the read/write designation terminal R/W of the memory circuit 130 becomes n L II when the control pulse CL4 is generated, so the numerical data 0001 is used as the data specifying the input/output element. The data is written to the memory address 1 designated by the sequential counter 115, and upon generation of the control pulse CL6, a pulse signal is input to the addition input terminal UP of the sequential counter 115, and the contents of the sequential counter 115 are incremented by 1 to become 2.

However, if the output of the test circuit 120 is H'', neither the gates 131 nor 118 are opened, so the numerical data oooi is not written to the memory circuit 130 and the sequential counter 115 is not incremented by +1.

Next, by reading the control data TFA O002 at memory address 307, numerical data 0002 is input to the data input terminal Din of the memory circuit 130, and the test command 4-TFA and the internal data at input/output address 2 are input to the test circuit 120. An on-off signal for input/output (LS3) is input.

If the internal input/output element (LS2) is off (normal), the test conditions are satisfied, so the test circuit 120 returns ゛°H.
'' signal is output, and if it is on (abnormal), the test conditions are not satisfied, and the test circuit 120 outputs an ''L'' signal.

If the output of the test circuit 120 is Ll+, the input of the reading/writing instruction terminal R/W of the storage circuit 130 becomes "LD" when the control pulse CL4 is generated, so that the numerical data is 000.
2 is written to the memory address designated by the sequential counter 115, and upon generation of the control pulse CL6, a pulse signal is input to the addition input terminal UP of the sequential counter 115, and the contents of the sequential counter 115 are incremented by 1.

However, if the output of the test circuit 120 is H'', neither of the gates 131 and 118 are opened, so the numerical data 0002 is not written to the memory circuit 130 and the sequential counter 115 is not incremented by +1.

In this way, the control data from addresses 306 to 316 are read out, and if the contacts constituting the starting circuit are normally open contacts, the test command TNA is used, and if the contacts are normally closed contacts, the test command TFA is used to read out the control data. The test circuit 120 determines whether the on-off state of each internal input/output element (L8.2) to (CR2) corresponding to the test condition satisfies the test condition. Only the input/output addresses of the elements are sequentially written starting from memory address 1 of the storage circuit 130.

When the control data TNAOIOI at memory address 316 is executed and the determination of all internal input/output elements corresponding to the contacts LS2 to CR2 constituting the startup circuit is completed, control data 5OF3770 at memory address 317 is read out next.

By this control data 5OF3770, the flip-flop 107, which is an internal input/output element at the special address 3770 specified by the address field, is reset by the control pulse CL5, and by resetting the flip-flop 107, the flip-flop 109 is also immediately reset. .

As a result, neither the sequential counter 115 nor the memory circuit 130 will operate from this point forward, and the monitoring results of one operation unit can be effectively stored and held.

When the control data JMPoooo at the next memory address 320 is read out, a jump is made to memory address O.

This ends the monitoring and the sequence control program is executed again.

Note that by resetting the flip-flop 109, the light emitting diode 111 is turned off and the operator is notified that the monitoring has ended.

On the other hand, if the starting relay CRI is on, that is, if the starting circuit is normal, the control data JMNO321 at the memory address 303 is executed to jump to the memory address 321 to check the unit advance cycle circuit.

In other words, the control data TFA0200 at memory address 321
Control data TFAO176 at memory address 322 and control data TFAO177 at memory address 323 are sequentially executed.

In this case, the unit advance cycle circuit is abnormal only when all of the internal input/output elements at input/output addresses 200, 176, and 177 are off, and normal otherwise.

Therefore, if all the internal input/output elements at input/output address 200°176.177 are off, after the control data JMNO340 at the next memory address 324 is executed, the control data ABNOO02 in the memory 325 is read out and the unit forward cycle circuit is activated. Monitoring begins.

In this case, the abnormal circuit number display 103 displays ``chip 2'' which means that the unit advance cycle circuit is abnormal.

On the other hand, if even one of the internal input/output elements at the input/output address 200.176.177 is turned on, after the control data 0340 at the memory address 324 is executed, the memory address 3
After jumping 40 degrees, the next circuit is checked.

The program is executed in this way, and the presence or absence of an abnormality is determined for each operation unit.The on-off state of each internal input/output element corresponding to the input conditions that make up the operation unit in which the abnormality has occurred is determined, and the test is performed. If the input/output address of the input/output element that does not satisfy the conditions is stored in the memory circuit 130, and if there is no abnormality in any circuit, the control data JMPOOOO at the memory address 370 is executed to jump to the memory address O and restart the sequence. A control program will be executed.

In addition, the time required to complete one cycle of the program is extremely short, and since the monitoring program always returns to the sequence control program after execution, monitoring is executed while the sequence control is being executed, and the interrupt function is This means that online monitoring can be performed even with a sequence controller that does not have one, and in this case there is no need to use a host computer, which is extremely practical.

The operator presses push button switch 1 for external command to start monitoring.
When it is confirmed that the light emitting diode 111 that was turned on by pressing 06 is turned off, the monitoring result is displayed externally.

First, the sequential counter clear push button switch 104 is pressed to set the content of the sequential counter 115 to O.

Next, push button switch 105 for sequential counter addition is pressed.

As a result, the contents of the sequential counter 115 are incremented by 1 and become 1.

The input of the read/write instruction terminal R/W of the memory circuit 130 is H1
1, so when the content of the sequential counter 115 reaches 1, the numerical data stored at memory address l, that is, the input/output address of the first internal input/output element that did not satisfy the conditions of the test instruction, is output as data. The signal is output to the terminal Dout, and its input/output address is displayed on the display 134.

When the push button switch 105 for sequential counter addition is pressed again, the content of the sequential counter 115 becomes 2, and the input/output address of the second internal input/output element that did not satisfy the conditions of the test command is transferred to the data output terminal Dout. The input/output address is displayed on the display 134.

In this way, each time the push button switch 105 for sequential counter addition is pressed, the contents of the sequential counter 115 are incremented by 1, and the input/output address of the internal input/output element that did not satisfy the conditions of the test command stored in the memory circuit 130 is Display unit 1 in order
34.

The operator first has to increment the contents of the sequential counter 115 by 1 when the special address 3770, which means that the monitoring has ended, is displayed on the display 134.

The operator can know which internal input/output element system circuit has an abnormality based on the input/output address displayed on the display 134.

FIG. 6 shows another embodiment of the monitoring circuit 100.

Components in FIG. 6 having the same reference numerals as those in FIG. 2 perform the same functions as the components in FIG.

In addition, in FIG. 6, the input/output selection circuit 12 shown in FIG.
, register 101, AND gate 102, and abnormal circuit number display 103 are omitted.

In FIG. 6, 140 is a storage circuit that stores the addresses of internal input/output elements 11a and 11b that do not satisfy the conditions of the input/output test command when the monitoring start flag circuit 107 is in the set state.

In this embodiment, when a pulse is input to the load signal input terminal, numerical data input from the data input terminal is stored, and when a pulse is input to the reset terminal R, the plurality of registers 140-1 to 140-n are reset. The address part of the control data is connected to the data input terminal of each register 140-1 to 140-n on the line AD.
The load signal input terminal is input with the outputs of the anti-games 1141-1 to 141-n, and the reset terminal R is input with the push button switch 10 for sequentially clearing the counter.
The pulse generated by 4 is input.

A selector 143 decodes the content of the sequential counter 115 and selects the AND gates 141-1 to 141-n.When the content of the sequential counter 115 is 1, the AND gate 1411 is enabled, and when the content is 2, the AND gate 14 is activated.
12...n, the anime game N41-n is enabled.

The output of the AND gate 131 is input to one input terminal of each AND gate '1411 to 141-n.

Reference numeral 144 denotes a display circuit for externally displaying the stored contents of the memory circuit 140, and each register 140-1 to 140-14 of the memory circuit 140
A plurality of indicators 144-1 to 144-1 to which the outputs of 0-n are input.
44-n.

Therefore, according to this embodiment, while the flip-flop 107, which is the monitoring start flag circuit, is set, the input/output element that does not satisfy the conditions of the input/output test instruction is determined by the input/output test circuit 120. Only the output addresses are sequentially stored in the registers 140-1 to 140-14 of the memory circuit 140.
0-n, and at the same time, those input addresses are externally displayed on each display 144-1 to 144-n of the display circuit 144.

In this embodiment, unlike the embodiment shown in FIG. 2, there is no need to sequentially operate the counter addition push button switch in order to externally display the stored contents of the memory circuit 130.

In the embodiment described above, the test command TNA is used in the monitor link program.

Although TFA is used, test commands TNA and TNO are sent to the AND gate 121 of the input/output test circuit 120.

TNE is input through the OR gate, and test commands TFA and TPO are input to the AND gate 122.

If TFE is input through the OR gate, all test commands TNA, T
FA, TNO, TFO, TNE, TFE can be used.

In addition, a monitoring circuit 1 is provided in the test flag circuit 14.
If the same test circuit as the input/output test circuit 120 used in 00 is provided, the input/output test circuit 120 is not provided in the monitoring circuit 100 and the test circuit provided in the test flag circuit 14 is monitored. It may also be used as the circuit 100.

Furthermore, in the above embodiments, what is stored in the memory circuit 130 or 140 is the input/output address of the input/output element, but it is also necessary to store the position in which the input/output element is programmed. Can be done.

For example, the data input terminal Din of the memory circuit 130 has a first
If the output of the program counter 2 shown in the figure is input, the program address of the input/output element is memorized, and the Q terminal output of the flip-flops 107 and 109 and the control pulse CL
By providing a counter that is incremented by 1 under the AND condition of 6 and inputting the output of this counter to the data input terminal Din of the memory circuit 130, it is possible to determine which input/output element is programmed in the monitoring program for monitoring each sequence circuit. The storage circuit 130 stores whether or not there is one.

If the operator knows the programmed position of the input/output element, he or she can refer to the program sheet and know the input/output address of the input/output element.

As described above, according to the present invention, even if the sequence controller does not have an interrupt function, online monitoring can be performed without stopping sequence control, and since a host computer is not required, monitoring can be performed easily and at low cost. It has the following advantages.

In addition, during the monitoring execution process, the presence or absence of an abnormality is determined for each operating unit, and the circuit number corresponding to the operating unit with an abnormality is displayed, and only the input conditions are monitored to identify input/output elements that do not satisfy the conditions of the test command. Since the data is stored, the cause of the failure can be easily and reliably investigated based on the monitoring results.

Furthermore, the storage device for storing the monitoring results has the advantage of requiring a relatively small capacity as long as it can store the input conditions corresponding to one operation unit.

[Brief explanation of the drawing]

The figures show an embodiment of the present invention, and FIG. 1 is a schematic block diagram of a sequence controller according to the present invention, and FIG.
The figure is a detailed diagram of the monitoring circuit 100 in FIG.
3 is a timing chart of control pulses, FIG. 4 is a sequence circuit diagram, FIG. 5 is a schematic diagram of a program sheet in which a sequence control program and a monitoring program are written, and FIG. 6 is another embodiment of the monitoring circuit 100. FIG. 7 is a functional block diagram of the monitoring circuit 100. 1...Main memory circuit, 2...Program counter, 4...Instruction register, 6...Instruction decoder, 14.
...Test flag circuit, 10... External input/output element group, 11... Internal input/output element group, 12
...Input/output selection circuit, 12a...Input selector, 12b...Output selector, 100.
... Monitoring circuit, 101 ... Register, 103 ... Abnormal circuit number display, 104
...Push button switch for sequential counter clearing, 10
5...Push button switch for sequential counter addition, 10
7...Monitoring start flag circuit (flip-flop to J-), 115...Sequential counter,
119...Memory address display, 120...
...Input/output test circuit, 130.140...Memory circuit, 134...Display circuit, 143...
... Selector, 144 ... Display circuit, 200.
...Monitoring storage device, 210...Memory address switching circuit, 220...First control means, 2
30... second control means, 240...
Abnormal circuit number display device, 250... Monitor result display circuit.

Claims (1)

[Claims] 1 Sequentially read out the sequence control data programmed in advance and stored in the storage device, import the on/off state of the input/output element specified by the read control data, and turn on/off the input/output element specified by the read control data. Determine whether the state satisfies the conditions of the input/output test command commanded by the control data, select the output element commanded by the control data, and execute the control using the result of the determination as a condition. In a sequence controller that sequentially controls a controlled object by turning on and off the selected output element according to an output command specified by data,
A monitor program is stored in a storage area different from a sequence control data storage area of the storage device, and this monitor program monitors a group of input conditions for controlling one of the output elements as a unit of operation. It is separated into multiple monitor programs and multiple discrimination programs that determine the presence or absence of an abnormality, and if the on/off state of each input/output element, which is the input condition for each operation unit, does not satisfy the conditions of the test command, the Monitoring storage device 130, 1 that stores data specifying input/output elements
40, and a memory address switching circuit 115 that sequentially switches the memory addresses of the monitor memory devices 130, 140 in synchronization with the execution of the monitor program, and in response to a monitoring start command, the memory address of the monitor memory devices 130, 140 is switched from the memory device storing the sequence control data to First control means 106, 10 that reads and executes a determination program that determines the presence or absence of an abnormality for each operation unit.
9 is provided, and the monitor storage device 130, 1 is stored immediately before the start of execution of the monitor program of the operation unit determined to be abnormal.
40 and a second control means 107゜131.118 for enabling the memory address switching circuit 115, and an abnormal circuit number display device for outputting and displaying an abnormal circuit number assigned to an operation unit determined to be abnormal. Display circuits 134 and 144 for data stored in the monitor storage devices 130 and 140 and specifying the input/output elements;
A sequence controller characterized by being provided with.