JPS5832498B2 - How to use hand tools - Google Patents
How to use hand toolsInfo
- Publication number
- JPS5832498B2 JPS5832498B2 JP48093296A JP9329673A JPS5832498B2 JP S5832498 B2 JPS5832498 B2 JP S5832498B2 JP 48093296 A JP48093296 A JP 48093296A JP 9329673 A JP9329673 A JP 9329673A JP S5832498 B2 JPS5832498 B2 JP S5832498B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor device
- insulating film
- manufacturing
- hand tools
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に関し、その目的とする
ところは半導体装置の絶縁被膜の段差部をテーパに形成
するにある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and an object thereof is to form a step portion of an insulating film of a semiconductor device into a tapered shape.
半導体装置、特に基板に絶縁被膜が形成され該絶縁被膜
の段差部分をまたいで配線金属層を備えたＭＯＳ Ｉ
Ｃの如き集積回路装置において、段差部分の配線金属層
の段切れを防止する方法の−・例としてＰＳＧ（Ｐｈｏ
ｓｐｈｅｒ ５ｉｌｉｃａｔｅ Ｇｌａｓｓ ）層を絶
縁被膜に積層して被着し、絶縁被膜の段差部分にテーパ
エツチングを施すことが広く用いられている。Semiconductor devices, particularly MOS I, in which an insulating film is formed on a substrate and a wiring metal layer is provided across the stepped portion of the insulating film.
In integrated circuit devices such as C, PSG (Pho
It is widely used to stack and deposit a layer of spheroidal glass on an insulating film, and to perform taper etching on the stepped portions of the insulating film.
このＩ） Ｓ Ｇ層の形成は気相成長の手段により次式
の如くなされ混合物の形で析出をみる１３シかしてたと
えば一基板内において複数個所のデーパエッチを所望す
る部分があるとき必らずしも−・様に施せないという欠
点があった。This I) S G layer is formed by means of vapor phase growth as shown in the following formula, and is deposited in the form of a mixture. There was a drawback that it could not be applied to sushi-like.
本発明は上記欠点を除去するため（こなされた半導体装
置の製造方法を提供するものである。The present invention provides a method for manufacturing a semiconductor device that eliminates the above-mentioned drawbacks.
本願にか＼る半導体装置の製造方法の一実施例につき以
下に説明する。An embodiment of the method for manufacturing a semiconductor device according to the present application will be described below.
基板に被着された絶縁被膜の段差部分をまたいで形成さ
れた配線金属層を備えた半導体装置につき一例としてＭ
ＯＳ ＩＣの如き集積回路装置につきその製造方法を
以下にのべる。As an example, M
A method of manufacturing an integrated circuit device such as an OS IC will be described below.
これは基板に絶縁被膜が被着されこの段差部分をまたい
で配線金属層を被着するにあたり、絶縁被膜にＰＳＧ層
を積層被着し、該層のＰ（りん）濃度の犬なる部分のＰ
を除去するものである。This is because when an insulating film is applied to a substrate and a wiring metal layer is applied across this stepped part, a PSG layer is laminated and applied to the insulating film, and the P
It is intended to remove.
即ちＰＳＧ層の形成については従来と異なるところはな
い。That is, the formation of the PSG layer is not different from the conventional method.
次に該Ｉ） Ｓ Ｇ層について発明者は種々の点から検
討を行なった結果、チー・パエッチングに好適するＰ濃
度（ＰＳＧ層について）は４×１０２０〜６×１０２０
個／鼾であるのにたいし、部分的にＩ Ｘ １０２’個
／ｃｍ以上の所があることが判明した。Next, as a result of examining the I) S G layer from various points, the inventor found that the P concentration (for the PSG layer) suitable for Chi-Pa etching is 4 x 1020 to 6 x 1020.
It was found that while the number of snores was I x 102' snores/cm or more in some places.
そしてＩ）濃度が大なるＰＳＧ層程レジストとの密着性
が低下するのでいわゆるオーバエツチングになりやすく
、シたがってテーパエツチングのバラツキを招来する。and (I) the higher the concentration of the PSG layer, the lower its adhesion with the resist, which is more likely to cause so-called over-etching, resulting in variations in taper etching.
そこでバラツキの少いテーパエツチングを行なうために
はＰ Ｓ Ｇ層におけるＰ濃度を均一にすることが必要
であるとし、被着したＰＳＧ層に次にあげるいずれかの
処理を施すことによって達成される。Therefore, in order to perform taper etching with little variation, it is necessary to make the P concentration in the PSG layer uniform, and this can be achieved by performing one of the following treatments on the deposited PSG layer. .
（］、） 濃硝酸中にてボイルする。(],) Boil in concentrated nitric acid.
（２）王水中にてボイルする。(2) Boil in aqua regia.
（３）ぶつ酸（ＨＦ）中に浸漬する。(3) Immerse in butic acid (HF).
このぶつ酸は約１０％濃度の液で好適する。This butic acid is preferably used in a solution having a concentration of about 10%.
（４）ぶつ酸、硝酸よりなる混液中に浸漬する。(4) Immerse in a mixed solution of butic acid and nitric acid.
上記処理を施すことによってＰＳＧ層中のＰ濃度は５×
１０２０〜９ Ｘ １０２０個／ｃｙｎの範囲にて均一
となり、集積回路装置における絶縁被膜のテーパエツチ
ングがウェハ内およびロット内でバラツキなく達成でき
るようにな−った。By performing the above treatment, the P concentration in the PSG layer is reduced to 5×
It became uniform in the range of 1020 to 9 x 1020 pieces/cyn, and taper etching of an insulating film in an integrated circuit device could now be achieved without variation within a wafer and within a lot.
本願は上記実施例に限定されるものでなく、ＰＳＧ層を
適用してテーパエツチングを行なう半導体装置に広〈実
施でき顕著な効果のあるものである。The present invention is not limited to the above-mentioned embodiments, but can be widely applied to semiconductor devices in which taper etching is performed using a PSG layer, and can have remarkable effects.
Claims (1)
成された配線金属層を備えた半導体装置の製造にあたり
、絶縁被膜にＰＳＧ層を積層して被着する工程と、該層
のＰ濃度の犬なる部分のＰを除去する工程とを具備した
半導体装置の製造方法。1. In manufacturing a semiconductor device equipped with a wiring metal layer formed across a stepped portion of an insulating coating applied to a substrate, the process of laminating and depositing a PSG layer on the insulating coating and the P concentration of the layer A method for manufacturing a semiconductor device, comprising the step of removing P in a dog portion of the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP48093296A JPS5832498B2 (en) | 1973-08-22 | 1973-08-22 | How to use hand tools |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP48093296A JPS5832498B2 (en) | 1973-08-22 | 1973-08-22 | How to use hand tools |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5043891A JPS5043891A (en) | 1975-04-19 |
| JPS5832498B2 true JPS5832498B2 (en) | 1983-07-13 |
Family
ID=14078394
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP48093296A Expired JPS5832498B2 (en) | 1973-08-22 | 1973-08-22 | How to use hand tools |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5832498B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS611875U (en) * | 1984-06-08 | 1986-01-08 | リコーエレメックス株式会社 | panel structure |
| JPS6165783U (en) * | 1984-10-05 | 1986-05-06 |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6318697A (en) * | 1986-07-11 | 1988-01-26 | 日本電気株式会社 | Multilayer interconnection board |
-
1973
- 1973-08-22 JP JP48093296A patent/JPS5832498B2/en not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS611875U (en) * | 1984-06-08 | 1986-01-08 | リコーエレメックス株式会社 | panel structure |
| JPS6165783U (en) * | 1984-10-05 | 1986-05-06 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5043891A (en) | 1975-04-19 |
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