JPS5832509B2 - Vertical field effect transistor and its manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a GaAs vertical field effect transistor (FET).
and its manufacturing method.

FETs using GaAs have conventionally been manufactured with a structure using a Schottky barrier as a gate.

The advantage of using GaAs as a material is that it has high electron mobility.

The Schottky barrier FET is an element that takes full advantage of this advantage, and has been proven to have excellent high frequency characteristics.

However, there has been a desire for further improvement in characteristics with regard to higher output and the like.

In view of the current situation, the present invention provides G a A 5G
The object of the present invention is to provide a vertical FET that uses an aAlAs-based crystal and has excellent frequency and output characteristics.

The present invention will be explained in detail below using examples.

FIG. 1 shows the basic structure of the present invention.

Figure a is an overhead view, and figure b is a sectional view taken along line A-A'.

The n-type GaAs channel is formed vertically as shown in the figure, and the p-type GaAs region 6 is the gate.

When a reverse bias is applied between the source electrode 7, drain electrode 9, and gate electrode 8, a depletion layer is expanded in the channel 3 as shown by the broken line, and conductivity modulation is performed.

The region 5 provided between the gate and the n-type GaAs layer 2 is made of n-type GaAs with reduced doping, and has the purpose of reducing the junction capacitance between the gate and drain and improving frequency characteristics.

For this purpose, it is desirable to make the carrier density in the region 5 as low as possible, but at least lower than the carrier density in the channel.

This FET is manufactured as follows.

First, an n-type GaAs substrate 1 (1 to 1018crIL
-3) n-type G by continuous liquid phase epitaxial growth method on top
An aAs layer 2 and an n-type Ga 0.9 A10.1 layer 4 are grown.

The thicknesses of these epitaxial layers are 4μ and 0.5μ, respectively.
It is 5μ.

This epitaxial layer is then mesa-etched leaving the channel region.

The channel was formed in a band-like shape, and the width of this band-like region, in other words, the thickness of the channel, was suppressed to 0.8 μm.

In order to improve the reproducibility of this width, H
The composition of the etching solution was controlled within 1% using 2SO4:H2O2:H2024:1:1, and the time and temperature were also precisely controlled.

The etching depth is 3μ. After etching, the wafer is carefully cleaned and the gate regions are formed.

For this purpose, we again used the continuous liquid phase growth method to
An s layer 5 and a pGaAs layer 6 are epitaxially grown.

Since growth generally does not proceed on Ga1-xAlXAs once exposed to air due to the mesa etching described above, growth occurs only in the area where mesa etching was previously performed, resulting in the structure shown in Figure 1. is obtained.

In this way, the surface layer is Ga1xANxAs (0<x<1
), and a transistor with stable characteristics can be obtained.

By adjusting the growth time, the surface of the growth layer and Gao, g AAo
, 1As 4 surface to obtain a flat surface as shown in the figure.

A source electrode 7 and a gate electrode 8 are formed by a lift-off method, and a drain electrode 9 is formed to complete the FET.

The width of the source electrode was 1 μm, and the width of the gate electrode was 5 μm.

When the FET manufactured through the steps described above was operated, good results were obtained with a power gain of 6 dB and an output IW at 8 GHz.

FIG. 2 shows another embodiment of the invention.

PET of this structure is made similarly to the rabbit example, but in a second stage of growth.

--GaAs5 p pGaAs6 p n--GaA
Grow 3 layers of s 10.

This is to reduce the thickness of the p-GaAs layer 6 and shorten the effective gate length.

According to this method, the gate length can be reduced to 1 micron or less, and the frequency characteristics can be improved.

A voltage is supplied to the gate region 6 through a p-GaAs region 11 formed by diffusion.

The subsequent electrode attachment is the same as in the Sagi embodiment.

The carrier density of n-GaAs 10 is also reduced as in region 5, which helps to keep the capacitance between the source and gate low.

FIG. 3 shows another embodiment of the present invention, in which a region 12 with low carrier concentration is provided within the channel.

By providing this region, the carrier concentration of the source/drain and the carrier concentration of the channel can be selected independently.

This eliminates the need to increase source-drain resistance.
The expansion of the channel depletion layer can be adjusted.

Furthermore, since the length of the channel can be determined independently of the gate width, the length of the channel can be made extremely short.

Therefore, a vertical FET with very good high frequency characteristics could be obtained.

FIG. 4 shows another embodiment of the present invention, in which the GaAAAs used as a growth mask is removed by etching after growth to reduce the source contact resistance.

As described above, the vertical FET of the present invention is an amplification element that is excellent not only in high frequency characteristics but also in output characteristics, and its practical effects are extremely large.

Although the above embodiments have mainly been explained using GaAs, it is of course possible to replace GaAs with GaAlAs.

Further, although GaAlAs was used as a growth mask in the embodiment, it is of course possible to use an oxide film as a mask.

Furthermore, it goes without saying that the present invention can be carried out regardless of the conductivity type.

[Brief explanation of the drawing]

FIG. 1 is an embodiment of the present invention, in which a is an overhead view of a vertical FET and b is a cross-section of AA'. 2, 3, and 4 show another embodiment of the present invention. In FIGS. 1 to 4, 1 is an n-type GaAs substrate,
2 is an n-type GaAs growth layer, 3 is a channel, and 4 is an n-type G layer.
These are ao, 9Alo, and 1As growth layers. 5 is an n-type GaAs layer, 6 is a p-type GaAs gate region,
? , 8.9 are source, gate, and drain electrodes, respectively. 10 is an n-type GaAs region, 11 is a p-type GaAs region formed by diffusion, 12 is an n-type GaAs channel layer, and 13 is an n-type GaAs source region.

Claims (1)

[Claims] 1. Gal on a GaAs substrate having a predetermined conductivity type.
-xA I x A s (0<xζ''), a mesa-shaped semiconductor region having the same conductivity type as the substrate is formed to serve as a channel region, and a surface of the mesa-shaped semiconductor region The layer is Ga1-2Al□As (
0 < z 1), and a first semiconductor layer having a carrier density smaller than the carrier density of the mesa-shaped semiconductor region on both sides of the mesa-shaped semiconductor region, and a second semiconductor constituting the gate region. At least two of the layers are Ga1-
yAlyAs(0<y<1) and Ga1-y'A]y
The vertical type is formed of 'As (O<y'<1), and has a first electrode part on the upper part of the mesa-shaped semiconductor region and a second electrode part on the side of the GaAs substrate. Field effect transistor. 2 G on a Ga As substrate with a predetermined conductivity type.
At least one a1-xAlxAs (0<, x<, 1) layer and the top layer of Ga1, Al□As
A plurality of semiconductor layers having the same conductivity type as the substrate are formed, and a mesa-shaped region of a predetermined width is etched into the formed plurality of semiconductor layers. At least two layers of a first semiconductor layer having a carrier density smaller than that of the mesa-shaped semiconductor region and a second semiconductor layer constituting the gate region are formed on both sides of the mesa-shaped semiconductor region using Gal + yAl 4s ( A method for manufacturing a vertical field effect transistor, comprising the step of forming it by epitaxial growth of Gax-y'AIy'As (0<y'<1).