JPS5832785B2 - electronic parts container - Google Patents
electronic parts containerInfo
- Publication number
- JPS5832785B2 JPS5832785B2 JP53127082A JP12708278A JPS5832785B2 JP S5832785 B2 JPS5832785 B2 JP S5832785B2 JP 53127082 A JP53127082 A JP 53127082A JP 12708278 A JP12708278 A JP 12708278A JP S5832785 B2 JPS5832785 B2 JP S5832785B2
- Authority
- JP
- Japan
- Prior art keywords
- solder
- band
- chip carrier
- pad
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
【発明の詳細な説明】
本発明は電子部品容器、特に半導体集積回路(IC)用
のチップキャリヤーと称される容器の改良に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in electronic component containers, particularly containers referred to as chip carriers for semiconductor integrated circuits (ICs).
従来電子部品素子、特にICを収容し回路基板上へ実装
するための容器としては、所謂デュアルインライン型パ
ッケージ等に代表されるように、回路基板への接続リー
ドを容器本体に取付けたものが使用されてきた。Conventionally, containers for housing electronic component elements, especially ICs, and mounting them on circuit boards have used containers with connection leads to the circuit board attached to the container body, as typified by so-called dual-in-line packages. It has been.
しかし価格低下及び実装密度向上の見地から、近時チッ
プキャリヤーと称される容器が採用され初めている。However, from the standpoint of reducing costs and increasing packaging density, containers called chip carriers have recently begun to be adopted.
これは第1図aにその断面構造を例示するように、IC
チップ1をセラミック等から成る容器本体2に収容し、
ワイヤ3により導体層4との間を結線した後、蓋5で気
密封止し、一方導体層4はセラミック容器本体2の側壁
か或いは本体2を貫通して形成したスルーホールかを経
由して本体2の裏面にまで延在させ、ここに接続パッド
6を設けたものである。As shown in FIG. 1a, the cross-sectional structure of the IC
A chip 1 is housed in a container body 2 made of ceramic or the like,
After connecting the conductor layer 4 with the wire 3, it is hermetically sealed with the lid 5, while the conductor layer 4 is connected via the side wall of the ceramic container body 2 or through a through hole formed through the body 2. It extends to the back surface of the main body 2, and a connection pad 6 is provided there.
接続パ゛ノドは容器本体裏面の外周に沿って配列される
のが常である。The connection pins are usually arranged along the outer periphery of the back surface of the container body.
このチップキャリヤーは半田槽に浸漬して、バンド6に
予備半田7を施した後、回路基板への実装に際しては所
定位置に載置した状態にてリフロー処理を施すことによ
り実装を完了する。This chip carrier is immersed in a solder bath to apply preliminary solder 7 to the band 6, and then, when mounting on a circuit board, the chip carrier is placed in a predetermined position and subjected to a reflow treatment to complete the mounting.
半田のりフローはフラックスを塗布してヒータブロック
または赤外線ランプで加熱するか、フラックスを使用し
ないなら、還元雰囲気の炉内で加熱して行なうものであ
る。Solder flow is performed by applying flux and heating it with a heater block or infrared lamp, or if flux is not used, heating it in a reducing atmosphere furnace.
このリフロー処理時に、チップキャリヤーの載置位置が
僅かにずれていても、熔融半田の表面張力によってチッ
プキャリヤーが適正位置に移動して固着されるため、載
置位置合せが容易になるばかりか、チップキャリヤー並
びに回路基板の導体層パターンの位置精度にも余裕を生
じる。During this reflow process, even if the mounting position of the chip carrier is slightly shifted, the surface tension of the molten solder moves the chip carrier to the proper position and fixes it, which not only facilitates the mounting position but also There is also a margin in the positional accuracy of the chip carrier and the conductor layer pattern of the circuit board.
また従来の容器の如1−ドが不要であることは価格の低
下を招来する利点を生じる。Also, the elimination of the need for a conventional container has the advantage of lowering costs.
上記チップキャリヤーを実装すべき回路基板としては、
通常のプリント回路基板の他に数個のチップキャリヤー
を搭載するマザーボードと称される回路基板が一般に使
用されている。The circuit board on which the above chip carrier is mounted is as follows:
A circuit board called a motherboard, which carries several chip carriers in addition to a regular printed circuit board, is commonly used.
第1図すは4個のチップキャリヤ−8をマザーボード9
に搭載した状態の側視図であって、これはプリント回路
基板への接続リードを介して通常のプリント回路基板へ
接続、実装する1つのモジュールとして取扱われるもの
である。Figure 1 shows four chip carriers 8 and a motherboard 9.
This is a side view of the device mounted on a PC board, which is handled as one module that is connected to and mounted on an ordinary printed circuit board via a connection lead to the printed circuit board.
上記の如きチップキャリヤーと称される電子部品容器で
は、従来の如くプリント回路基板のスルーホールに挿入
固着した接続リードによるような固着強度を期待し難く
、高信頼性を得るにはこの固着強度の点での改善が望ま
れる。In electronic component containers such as those mentioned above, which are called chip carriers, it is difficult to expect the adhesion strength of connection leads that are inserted and fixed into through holes of printed circuit boards as in the past. Improvement in this area is desired.
またICの高集積化並びに実装密度の向上に伴って放熱
性の改善つまり容器の熱抵抗低下が切実に要求されて来
ているが、上記チップキャリヤーの熱抵抗を低下すべく
特別の放熱器を取付けようとすれば低価格という特徴を
損い兼ねない。Furthermore, as ICs become more highly integrated and their packaging density increases, there is an urgent need to improve heat dissipation, that is, to lower the thermal resistance of the container. If you try to install it, you may lose the low price feature.
従って本発明は、極めて簡単な構成で上記のチップキャ
リヤーの放熱性並びに回路基板への固着強度を改善する
ことを目的とするものである。Therefore, it is an object of the present invention to improve the heat dissipation properties of the above-mentioned chip carrier and the strength of its adhesion to a circuit board with an extremely simple structure.
本発明による電子部品容器は、素子を収容する容器本体
と、該素子に電気的に接続された信号端子であって前記
容器本体の一面に外周に沿って設けられた複数の半田付
はパッドとを有する電子部品容器において、前記−面の
前記信号端子用半田付はバンドより内側の領域に信号端
子としては機能しない半田付はパッドを有し、両半田付
はパッドは溶融ハンダ付着後の半田の高さがほぼ同等と
なるパターンに形成されたことを特徴とするものであり
、以下これを詳細に説明する。The electronic component container according to the present invention includes a container body that houses an element, a signal terminal electrically connected to the element, and a plurality of solder pads provided along the outer periphery on one surface of the container body. In the electronic component container, the solder for the signal terminal on the - side has a pad in the area inside the band that does not function as a signal terminal, and the pad for the double solder has a pad after the molten solder is attached. This feature is characterized in that the heights of the two are formed in a pattern that is approximately equal to each other, and this will be explained in detail below.
本発明においては容器(チップキャリヤー)本体の回路
基板への固着面に信号端子用半田付はバンドと共に熱抵
抗低下及び固着強度向上のための半田付はバンドを設け
ることにより前記の目的を達成するものである。In the present invention, the above object is achieved by providing a band for soldering signal terminals and a band for soldering to reduce thermal resistance and improve bonding strength on the surface of the container (chip carrier) body that is fixed to the circuit board. It is something.
バンドへの半田の付着量は、溶融した半田の表面張力に
よって影響され、はぼバンドの大きさに比例した高さの
半田が付着する。The amount of solder adhering to the band is influenced by the surface tension of the molten solder, and the solder adheres to a height proportional to the size of the band.
例えば−辺が0.25w1tの正方形のバンドでは半田
の付着高さは15〜20μであっても、Q、35wIt
のものでは30〜40μ、0,5wIt角のバンドでは
50〜65μの高さに半田が付着する。For example, in a square band with a side of 0.25wIt, even if the solder adhesion height is 15 to 20μ, Q, 35wIt
Solder adheres to a height of 30 to 40 μm for a band of 0.5 wIt angle, and 50 to 65 μm for a band of 0.5 wIt angle.
各バンドにおける半田付着量がこのように相違している
場合には、付着量の少ないバンドの回路基板への接が不
安定となることは言うまでもない。Needless to say, if the amount of solder adhered to each band is different in this way, the band with a smaller amount of solder adhered will be unstable in contact with the circuit board.
本発明では、かかる接続不安定を回避すべく、信号端子
用パッドと熱抵抗及び強度改善用バンドとを半田付着高
さぎほぼ同等となるようなパターンとしておく点に大き
な特徴がある。The present invention is characterized in that, in order to avoid such unstable connection, the signal terminal pad and the band for improving thermal resistance and strength are patterned so that the solder adhesion heights are approximately the same.
これを実現するためには、簡便には全バンドをほぼ同一
形状とするか、或いは熱抵抗及び強度改善用バンドを帯
状とし、その幅を信号端子用パッドの一辺と同等として
おけばよい。In order to achieve this, it is convenient to make all the bands substantially the same shape, or to make the band for improving thermal resistance and strength into a band shape, and to make the width of the band the same as one side of the signal terminal pad.
以下本発明実施例を図面に沿って詳細に説明する。Embodiments of the present invention will be described in detail below with reference to the drawings.
第2図aは本発明実施例の電子部品容器(チップキャリ
ヤー)の断面を示す図であり、11はIC素子、12は
容器本体、13は接続ワイヤ、14は導体層、15は気
密封止用蓋、16は信号端子用バンド、17は半田、1
8は熱抵抗及び強度改善用パッドを夫々示している。FIG. 2a is a cross-sectional view of an electronic component container (chip carrier) according to an embodiment of the present invention, in which 11 is an IC element, 12 is a container body, 13 is a connecting wire, 14 is a conductor layer, and 15 is an airtight seal. 16 is a signal terminal band, 17 is solder, 1
8 indicates pads for improving thermal resistance and strength, respectively.
本容器の構造は、導体層14が容器本体12の周辺部を
貫通して形成されたスルーホールを介してIC素子11
とパッド16の間を連結している点を除けば、第1図に
示した従来のチップキャリヤーとその基本構造において
は同等である。The structure of this container is such that the conductor layer 14 passes through the IC element 11 through a through hole formed by penetrating the periphery of the container body 12.
The basic structure is the same as that of the conventional chip carrier shown in FIG. 1, except for the connection between the chip carrier and the pad 16.
但し本発明に従ってチップキャリヤ一本体12の裏面に
は信号端子用パッド16より内側の領域に熱抵抗及び強
度改善用パッド18が設けられている。However, according to the present invention, a pad 18 for improving thermal resistance and strength is provided on the back surface of the chip carrier main body 12 in a region inside the signal terminal pad 16.
第2図すは本実施例によるチップキャリヤーの裏面にお
ける各パッドのパターンを示す平面図であり、各パッド
16及び18は同一大きさ及び形状を有している。FIG. 2 is a plan view showing the pattern of each pad on the back surface of the chip carrier according to this embodiment, and each pad 16 and 18 has the same size and shape.
第2図Cは半田付はパ゛ノドのパターンの他の例を示し
ており、本発明による放熱及び強度改善用パッド18は
帯状となっており、その幅は信号端子用パッド16の一
辺の長さと略同−となっている。FIG. 2C shows another example of a pin soldering pattern, in which the heat dissipation and strength improvement pad 18 according to the present invention is strip-shaped, and its width is equal to one side of the signal terminal pad 16. It is approximately the same as the length.
何れのパターンであっても、各パ゛ノド上に付着する溶
融半田高さは略同−となり、各バンドは回路基板の導体
パターンに対して均等に固着されることになる。Regardless of the pattern, the height of the molten solder deposited on each pin is approximately the same, and each band is evenly fixed to the conductor pattern of the circuit board.
本発明によるチップキャリヤーを回路基板上に半田リフ
ローにより固着した状態の断面構造例を第3図に示す。FIG. 3 shows an example of the cross-sectional structure of a chip carrier according to the present invention fixed onto a circuit board by solder reflow.
同図にて第2図と同一部分は同一番号を付しである。In this figure, the same parts as in FIG. 2 are given the same numbers.
回路基板21にはチップキャリヤ−12裏面の放熱及び
強度向上用バンド18に対応する位置にも導体パターン
22が設けられてあり、両者は半田17により結合され
ている。A conductor pattern 22 is also provided on the circuit board 21 at a position corresponding to the heat dissipation and strength improving band 18 on the back surface of the chip carrier 12, and both are bonded by solder 17.
このパッド18は発熱源であるIC素子11の直下又は
近接した位置にあるから、IC素子11から回路基板2
1を介した放熱経路の熱抵抗減に著しい効果がある。Since this pad 18 is located directly below or close to the IC element 11 which is a heat generation source, it is possible to
This has a remarkable effect on reducing the thermal resistance of the heat dissipation path via 1.
この効果を一層高めるため、回路基板21を構成する絶
縁材料としてアルミナ等のセラミック材料を用いること
は有効であるが、勿論これ以外の種類のプリント回路基
板も適用可能である。In order to further enhance this effect, it is effective to use a ceramic material such as alumina as the insulating material constituting the circuit board 21, but of course other types of printed circuit boards are also applicable.
また固着強度の面においても、半田付は面積が著しく増
大することから、顕著な効果が得られるものである。Furthermore, in terms of adhesion strength, soldering significantly increases the area, so a remarkable effect can be obtained.
尚、信号端子用パッド16がチップキャリヤ−12裏面
の周辺に沿って配置される理由は、第3図から判るよう
に、固着後にパッド16と導体パターン23間の半田付
は状態が目視検査可能であること、及び第3図の如く半
田17がチップキャリヤー12の側壁に這上って固着さ
れるとその強度が著しく向上することによる。The reason why the signal terminal pads 16 are arranged along the periphery of the back surface of the chip carrier 12 is that, as can be seen from FIG. This is because, as shown in FIG. 3, when the solder 17 climbs up and is fixed to the side wall of the chip carrier 12, its strength is significantly improved.
これにひきかえチップキャリヤ−12裏面中央に形成さ
れるパッド18は信号端子の機能を有していないから、
仮に回路基板21の導体パターン22との間の電気的接
触が不完全或いは不安定であっても深刻な障害は生じな
いため、目複検査乃至修正や交換は不要である。In contrast, the pad 18 formed at the center of the back surface of the chip carrier 12 does not have the function of a signal terminal.
Even if the electrical contact between the circuit board 21 and the conductor pattern 22 is incomplete or unstable, no serious trouble will occur, so there is no need for repeated inspection, correction, or replacement.
本発明によって設けられる放熱及び強度向上用のバンド
は、さらに目的に応じてそのパターンが種々変更され得
る。The pattern of the band for heat dissipation and strength improvement provided according to the present invention can be changed in various ways depending on the purpose.
第4図はその例を示すチップキャリヤー裏面の平面図で
ある。FIG. 4 is a plan view of the back surface of a chip carrier showing an example of this.
この例ではチップキャリヤ−31裏面に設けた放熱及び
強度向上用バンド32は電気的には全てが相互接続され
、且つ電源端子33/に接続されている。In this example, all of the bands 32 for heat dissipation and strength improvement provided on the back surface of the chip carrier 31 are electrically interconnected and connected to a power supply terminal 33/.
33は信号端子用バンドである。これにより、バンド3
2に電気的シールドの機能を兼備させ得るのである。33 is a band for signal terminals. This results in band 3
2 can also have the function of an electrical shield.
即ち水平或いは垂直方向に隣接する信号線間では雑音を
誘起し勝ちであるが、電源系の導体を介在させることに
よりかかる雑音を遮蔽するシールド効果が得られる。That is, noise is likely to be induced between horizontally or vertically adjacent signal lines, but by interposing the conductor of the power supply system, a shielding effect can be obtained to block such noise.
更に上記パターンにより、その製造上も効果を生ずる。Furthermore, the above-mentioned pattern produces effects in terms of manufacturing.
即ち各バンドを構成する導体パターンは、例えばセラミ
ック製容器本体表面にモリブデン−マンガンの如き導体
ペーストを印刷、焼成後、その表面に半田付は性を得る
ためのニッケル層及び該ニッケル層の酸化を防止し且つ
気密封着を容易にする金属を順次電気メッキして形成さ
れるが、第4図のパターンであればこの電気メッキの際
のメッキ電極接続が従来と全く同様で済むのである。That is, the conductor pattern constituting each band is made by printing a conductor paste such as molybdenum-manganese on the surface of the ceramic container body, baking it, and then soldering it to the surface with a nickel layer to obtain properties and oxidation of the nickel layer. It is formed by sequentially electroplating metals that prevent the problem and facilitate hermetic sealing, but if the pattern shown in FIG. 4 is used, the connection of the plating electrodes during electroplating can be done in exactly the same way as in the past.
また第4図のパターンであれば各パッド上への溶融半田
付着高さはほぼ均等になるから、回路基板の対応する導
体パターンへ各パッドは一様に半田付けされ得る。Further, with the pattern shown in FIG. 4, the height of molten solder adhering to each pad is approximately equal, so that each pad can be uniformly soldered to the corresponding conductor pattern on the circuit board.
尚、放熱及び強度向上用のパッド33を上記例の如く電
源系の端子(接地端子を含む)に接続することは有効で
あるが、他の信号端子33に接続したのでは寄生素子を
付加することになるし、シールド効果も期待し得ないか
ら、これは避けるべきである。Although it is effective to connect the pad 33 for heat dissipation and strength improvement to the power supply terminal (including the ground terminal) as in the above example, connecting it to another signal terminal 33 adds a parasitic element. This should be avoided, as it will cause problems and the shielding effect cannot be expected.
第4図のチップキャリヤー例において本体31の側壁に
半円状の窪み34が形成されているのは、公知の如くそ
の製造工程に起因している。The reason why the semicircular recess 34 is formed in the side wall of the main body 31 in the chip carrier example shown in FIG. 4 is due to the manufacturing process thereof, as is well known.
即ちこの形のチップキャリヤーは、例えば比較的大面積
のセラミック板に基盤目状に配列してスルーホールを穿
設した後、該スルーホール内に導体ペーストを充填し、
焼成後スルーホールに沿ってセラミック板を切断する工
程によって、多数のチップキャリヤ一本体31を一括作
成すると共に、スルーホール内の導体層で裏面の各パッ
ド33.33・と素子搭載面側の導体層を連結するもの
である。That is, this type of chip carrier is made by, for example, forming through-holes arranged in a pattern on a relatively large ceramic plate, and then filling the through-holes with a conductive paste.
After firing, a process of cutting the ceramic plate along the through-holes allows a large number of chip carrier bodies 31 to be made at once, and a conductor layer in the through-holes is used to separate each pad 33 on the back side and the conductor on the element mounting side. It connects the layers.
前記半円状窪み34は上記スルーホールに対応するもの
である。The semicircular recess 34 corresponds to the through hole.
以上の説明で明らかなように、本発明によれば格別複雑
な製造工程或いは構造を付加することなしに、所謂チッ
プキャリヤーの放熱性及び機械的固着強度を格段に向上
し得るから、その実用に供しての効果は頗る大きい。As is clear from the above explanation, according to the present invention, the heat dissipation performance and mechanical adhesion strength of the so-called chip carrier can be significantly improved without adding any particularly complicated manufacturing process or structure. The effect of providing this service is significant.
第1図aは従来のチップキャリヤーの構造を示す図、第
1図すはその実装状態を示す図、第2図a、b、cは本
発明実施例のチップキャリヤーの断面構造及び半田バン
ドパターンを示す図、第3図は本発明実施例のチップキ
ャリヤーの実装状態を示す図、第4図は本発明の他の実
施例による半田パ゛ノドパターンを示す図である。
11・・・・・・IC端子、14・・・・・・導体層、
16.33・・・・・・信号端子用半田付はバンド、1
7・・・・・・半田、18.32・・・・・・放熱及び
強度向上用半田付はバンド、21・・・・・・回路基板
。FIG. 1a shows the structure of a conventional chip carrier, FIG. 1 shows its mounting state, and FIGS. 2a, b, and c show the cross-sectional structure and solder band pattern of a chip carrier according to an embodiment of the present invention. 3 is a diagram showing a mounting state of a chip carrier according to an embodiment of the present invention, and FIG. 4 is a diagram showing a solder pin pattern according to another embodiment of the present invention. 11...IC terminal, 14...conductor layer,
16.33...Soldering for signal terminal is band, 1
7...Solder, 18.32...Soldering for heat dissipation and strength improvement is a band, 21...Circuit board.
Claims (1)
された信号端子であって、前記容器本体の一面に外周に
沿って設けられた複数の半田付はパッドとを有する電子
部品容器において、前記−面に前記信号端子用半田付は
バンドの他に信号端子としては機能しない半田付はバン
ドを有し、両半田付はバンドは溶融ハンダ付着後の半田
の高さがほぼ同等となるパターンに形成されたことを特
徴とする電子部品容器。1. An electronic component container having a container body that houses an element, and a plurality of solder pads that are signal terminals electrically connected to the element and are provided along the outer periphery on one surface of the container body. , the solder for the signal terminal on the - side has a band in addition to the band, the solder that does not function as a signal terminal has a band, and the height of the solder in both solders is almost the same after the molten solder is attached. An electronic component container characterized by being formed into a pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53127082A JPS5832785B2 (en) | 1978-10-16 | 1978-10-16 | electronic parts container |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53127082A JPS5832785B2 (en) | 1978-10-16 | 1978-10-16 | electronic parts container |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5553446A JPS5553446A (en) | 1980-04-18 |
| JPS5832785B2 true JPS5832785B2 (en) | 1983-07-15 |
Family
ID=14951120
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP53127082A Expired JPS5832785B2 (en) | 1978-10-16 | 1978-10-16 | electronic parts container |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5832785B2 (en) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5778652U (en) * | 1980-10-30 | 1982-05-15 | ||
| JPS57197840A (en) * | 1981-05-29 | 1982-12-04 | Nec Corp | Chip carrier case |
| JPS5839049U (en) * | 1981-09-08 | 1983-03-14 | 富士通株式会社 | Chippukiyariya |
| JPS5954247A (en) * | 1982-09-21 | 1984-03-29 | Nec Corp | Electronic component parts |
| JPS60224235A (en) * | 1984-04-20 | 1985-11-08 | Fujitsu Ltd | Semiconductor device |
| JPS61292332A (en) * | 1985-06-19 | 1986-12-23 | Sumitomo Electric Ind Ltd | Semiconductor chip carrier |
| US4750089A (en) * | 1985-11-22 | 1988-06-07 | Texas Instruments Incorporated | Circuit board with a chip carrier and mounting structure connected to the chip carrier |
| JPS62166640U (en) * | 1987-03-26 | 1987-10-22 | ||
| US4899210A (en) * | 1988-01-20 | 1990-02-06 | Wakefield Engineering, Inc. | Heat sink |
| US5506755A (en) * | 1992-03-11 | 1996-04-09 | Kabushiki Kaisha Toshiba | Multi-layer substrate |
| US5285352A (en) * | 1992-07-15 | 1994-02-08 | Motorola, Inc. | Pad array semiconductor device with thermal conductor and process for making the same |
| JP4667154B2 (en) * | 2005-08-03 | 2011-04-06 | 京セラ株式会社 | Wiring board, electrical element device and composite board |
| JP2010171114A (en) * | 2009-01-21 | 2010-08-05 | Renesas Technology Corp | Semiconductor device |
| JP5059966B2 (en) * | 2009-02-26 | 2012-10-31 | 富士通テレコムネットワークス株式会社 | Printed circuit board and electronic device including printed circuit board |
-
1978
- 1978-10-16 JP JP53127082A patent/JPS5832785B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5553446A (en) | 1980-04-18 |
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