JPS5833632B2 - semiconductor storage device - Google Patents

Description

[Detailed description of the invention] The present invention relates to improvements in semiconductor memory devices.

Conventional 1-bit static type semiconductor memory devices with separate pin connections have separate input and output terminals, and when reading data from the semiconductor memory device, the input circuit becomes high impedance and the input circuit is connected to the semiconductor memory device. Since the output circuit does not become high impedance when writing, generally the input and output terminals of a semiconductor memory device cannot be externally connected via one common data bus, so it is used in a semiconductor memory device unit with a common input/output signal line. I can't.

On the other hand, a storage device that can be used in a storage device unit that shares input/output signal lines in common requires a dedicated terminal for controlling the storage device unit, resulting in an increase in the number of terminals.

In a parallel bit type semiconductor memory device, input/output signal lines can be shared as shown in FIG. 1, but the allowable number of words for one chip is smaller than that of a 1 bit type.

Therefore, when manufacturing a large-capacity storage device unit, the number of chips connected to the - signal line increases, resulting in a rapid increase in load capacity.

Furthermore, in order to select each chip, a device for converting an address selection signal into a chip selection signal is required, which makes the method complicated.

The present invention provides 1-bit type, input/output separated type, and static type semiconductor memory in which data input terminals and data output terminals can be connected to the outside through a common data bus, and the load capacitance of the chip attached to the signal line is reduced. The purpose is to obtain equipment.

An embodiment of the present invention will be described with reference to FIG.

The external terminals of the 1-bit type static semiconductor memory device of the present invention with separate input/output pin connections include a data input terminal, a data output terminal, an address terminal, an R/W pulse terminal, and a chip select terminal. , a power supply VDD terminal, and a power supply VSS terminal.

The chip select terminal 17 and the R/W pulse terminal 18 are connected to the control circuit 21, and the data input terminal 16 is connected to the input circuit 20.
The data output terminal 19 is connected to the output circuit 22.

The control circuit 21 which connects the chip select terminal 17 and the R/W pulse terminal 18 is provided with an R terminal 15 dedicated to read signal extraction and a W terminal 14 dedicated to write signal extraction.
The terminal 15 is connected to the output circuit 22, and the W terminal 14 is connected to the input circuit 20.
is connected to.

The R terminal 15 or W of the control circuit 21 corresponds to the chip selection signal input to the chip select terminal 17 and the read signal or write signal input to the @R/W pulse terminal 18.
A read signal or a write signal appears on the terminal 14.

When a chip selection signal is input to the chip select terminal 17, even if a read signal or a write signal is input to the R/W pulse terminal 18, the control circuit 21 controls the read signal or write signal.

Therefore, the read signal is applied to the R terminal 15 of the control circuit 21, and the W
No write signal appears on terminal 14.

That is, the control circuit 21 is controlled by a chip selection signal or a chip non-selection signal.

When the chip is not selected, the chip selection signal is sent to the control circuit 2.
1 through the R terminal 15 and W terminal 14 of the input circuit 20. The signal enters the output circuit 12, and the input impedance of the input circuit 11 and the output impedance of the output circuit 22 become high impedance.

At the time of chip selection, a read signal input to the R/W pulse terminal 18 is input to the output circuit 22 via the control circuit 21, and the output impedance of the output circuit 22 becomes low impedance.

Further, the write signal input to the R/W pulse terminal 18 enters the input circuit 20 via the control circuit 21, and the input impedance of the input circuit 20 becomes low impedance.

When the data output terminal 19 is externally connected through one common data bus, the output circuit 22 becomes high impedance when the semiconductor memory device writes, and the data input to this terminal is written into the input circuit. Since the terminal 20 has a high impedance, the read data does not enter the input circuit 20 and can be read from this terminal.

Although an embodiment of the control circuit 21, input circuit 20, and output circuit 22 is shown in FIG. 2, the control circuit, input circuit, and output circuit of the semiconductor memory device of the present invention are limited to the embodiment shown in FIG. It is sufficient that the conditions described above are satisfied.

According to the present invention, since the pin connections are the same as those of a conventional 1-bit type input/output separated type semiconductor memory device, when it is made into a memory device unit, it is compatible with the conventional semiconductor memory device.
The data input terminal and data output terminal can be externally connected via one common data bus, and by providing a control circuit that connects the chip select terminal and the R/W pulse terminal, no special terminal is required, and the storage device unit The packaging density will increase.

The 1-bit type semiconductor memory device of the present invention has a larger load capacity per chip than the conventional parallel bit type semiconductor memory device, but when it is made into a memory device unit, the number of words differs, so the number of chips attached to one signal line is large. The load capacity of the chip is halved, and as a large-capacity storage unit is made, the load capacity occupied by the chip per signal line decreases, and furthermore, there is no need for a device to generate a signal for selecting a chip from an address signal. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional parallel bit type, input/output common type semiconductor memory device, and FIG. 2 is a circuit diagram of a 1 bit type, input/output separated type semiconductor memory device of the present invention. 1 to 12...chip, 13...chip select terminal, 16...input terminal, 17...chip select terminal, 18...R/W pulse terminal, 19...output terminal,
20... Input circuit, 21... Control circuit, 22...
Output circuit.

Claims (1)

[Claims] 1 An input terminal connected to the input circuit, an output terminal connected to the output circuit, an address terminal, a chip selector terminal connected to the control circuit, an R/W pulse terminal, and a power supply V
The semiconductor memory device consists of only a DD terminal and a power supply VSS terminal, and controls the input circuit and the output circuit via the control circuit by signals input to the chip select terminal and the R/W pulse terminal, and the semiconductor memory device A 1-bit type static type with separate input and output pin connections, characterized in that both the input circuit and the output circuit are set to high impedance when not selected, the output circuit is set to high impedance when writing, and the input circuit is set to high impedance when read. type semiconductor memory device.