JPS5833712B2 - How to write/rewrite nonvolatile memory - Google Patents

Description

[Detailed Description of the Invention] Semiconductor memories are capable of large-scale integration (hereinafter referred to as LSI) due to the fact that stored information can be easily retrieved as electrical signals at high speeds and with the development of integrated circuit (hereinafter referred to as IC) technology. Due to its improved bit density and reliability, it has recently been used as a high-speed memory device for electronic computers.

However, unlike magnetic memories, semiconductor memories have the disadvantage that when the supply of bias electrodes is cut off, the stored contents disappear (hereinafter referred to as volatility).

In order to obtain a semiconductor memory that does not have this drawback, research has been carried out on the memory function of semiconductor glasses such as chalcogenide glass, but this has not yet reached a practical stage.

In addition, silicon semiconductor I is used as a non-volatile semiconductor memory.
In the field of C, metal (2), silicon nitride film (N),
An MNO8 field effect transistor having a structure of silicon oxide film (0) and silicon (S) has been developed, but in this case, the silicon oxide film (S r 02 ) must be thin enough to allow carriers on the semiconductor surface to tunnel. Therefore, pinholes etc. are likely to occur in this silicon oxide film,
However, since the storage mechanism is based on trap levels, there is a risk that productivity and reproducibility will be poor, and for this reason, it has not been put to practical use in electronic computers.

However, in the field of semiconductor memory other than these, read-only memory (hereinafter referred to as ROM) is a type of memory that takes advantage of the high bit density and high speed of semiconductor memory to read fixed memory contents.
).

There are two ways to configure this ROM, one of which is the IC
This is a method to imbue fixed information on the glass mask used for photo-etching when manufacturing.

Another method is to uniformly manufacture ICs regardless of the content to be stored, and then electrically write information in accordance with the content to be stored.

Three methods of the latter method are known.

That is, the first method is to fuse the wiring with a current pulse, the second method is to use the memory characteristics of alumina traps, and the third method is to use a transistor (MOS) when no channel current flows. By avalanche breakdown of the junction between the drain and the semiconductor substrate, carriers having the same shape as the semiconductor substrate are injected into the oxide film, and the carriers charge the polycrystalline silicon thin film layer embedded in the oxide film to write information. This is how it was done.

The present invention improves the third method among these three methods.
In connection with the new writing method, the conventional method will first be described in more detail with reference to FIG.

In this case, as shown in FIG. 1A, a drain region 2 and a source region 3 having a conductivity type opposite to that of the substrate 1 and having a high impurity concentration, a gate silicon oxide film 4, and a silicon A field effect transistor 7 consisting of a silicon polycrystalline layer 6 buried between oxide films 4 and 5 is formed.

In this field effect transistor 7, when the drain voltage is increased, a depletion layer 8 is formed from the drain region 2 into the substrate 1.
However, as shown by the arrow, the electric field is concentrated particularly in the lower part 9 of the silicon polycrystalline layer 6, and the electric field becomes higher than in other parts of the depletion layer 8, and finally reaches the critical point of avalanche deposition. reach the electric field.

At this time, electron-hole pairs of electrons 10 and holes 11 are generated in this portion 9 as shown in FIG. 1B, and the substrate 1 is
In the case of a shape, the electrons 10 are accelerated by the electric field in the direction of the oxide film 4 as shown by the arrow 12, thereby gaining high energy and being injected into the oxide film 4.

The electrons 10 injected in this manner pass through the oxide film 4 and reach the silicon polycrystalline layer 6, charging it negatively.

On the other hand, the holes 11 are transported to the drain region 2 as shown by an arrow 13 by the electric field.

In this way, information can be written by obtaining a charged state of the silicon polycrystalline layer 6, and on the other hand, information once written in this way can be erased in principle by irradiating the field effect transistor 7 with ultraviolet rays or X-rays. Can be done.

However, such semiconductor memories generally become depletion type after writing, require a selection transistor in each cell even in the array configuration as a programmable ROM, and use an avalanche of pn junctions, so it is possible that during writing. This also resulted in the destruction of the element.

Furthermore, when this is used in an actual device, it is housed in a package and fixedly wired inside the device casing, so the package built into the device must be removed each time information is rewritten. It is actually extremely difficult to perform X-ray irradiation, and furthermore, it is practically impossible to selectively rewrite only arbitrary bits in the memory.

Therefore, the present invention takes the above-mentioned points into consideration and provides a new writing method that has not been seen before.

Furthermore, even if the package is installed in a device, it is possible to write and rewrite information in the non-volatile memory without changing the state.
The present invention provides a rewriting method and a new writing method that has never existed before.

The basic feature of the present invention is to form a high electric field region in the semiconductor substrate, supply carriers to the region, accelerate it to a high energy state, and move the insulating film and the semiconductor from the surface of the semiconductor substrate into the insulating film. By injecting energy beyond the energy barrier formed by the substrate, the charge storage means provided in the insulating film is charged in the direction of the sign of the carrier, thus writing the memory contents. be.

In the present invention, as a new method for injecting carriers in a semiconductor substrate into an insulating film, a method is proposed in which hot carriers are obtained in the pinch-off (high field velocity saturation) region of the channel of a field effect transistor and then injected. take.

The features of the writing method according to the present invention will become clear from the detailed description below in conjunction with the drawings.

First, referring to FIG. 2, an example of the storage method according to the present invention will be described.
1 has the same structure as the field effect transistor 7 shown in FIG. 1, except that a second gate electrode 23 is provided on an insulating film 27 made of a silicon oxide film.

In FIG. 2, 22 is a gate insulating film, 24 is a semiconductor substrate, 25 is a drain region, 26 is a source region, 27 is an insulating film continuous with the gate insulating film 22, and 28 is the gate insulating film 22 and the semiconductor substrate. The first gate electrode is buried between the insulating films 27, and 29 represents a depletion layer.

In order to inject carriers in the substrate 24 into the gate insulating film 22 of the field effect transistor 21, it is necessary to give the carriers enough energy to cross the barrier between the substrate 24 and the insulating film 22. .

Therefore, in the case of FIG. 2, in order to obtain a charge state of 1 on the gate electrode 28, the field effect transistor 21 is put into a pinch-off state, and carriers are made into hot carriers near the drain side of the channel, and this is insulated. Inject into membrane 22.

With the configuration of the present invention, it is also possible to electrically erase the above writing.

That is, in order to obtain a different charging state of the gate electrode 28, the drain voltage is increased to cause avalanche breakdown at the portion of the surface of the substrate 24 below the gate electrode 28 in contact with the drain region 25, thereby causing the case of FIG. Similarly, carriers generated in the depletion layer 29 of the substrate 24 are injected into the insulating film 22.

In this case, the sign of the charge of the carriers injected by the former is opposite to that of the latter, and therefore the gate electrode 28 in the above-mentioned first charged state is converted to another charged state with the opposite sign. I can do it.

Therefore, it is possible to erase the information once written to the transistor 21 (i.e., the gate electrode 28 is in a state of charge of 1) and write the opposite information (i.e., the gate electrode 28 is in a different state of charge); The opposite is also possible.

The above is an overview of the method of the present invention with respect to FIG. 2, and next, it will be described in more detail along with the configuration for realizing this method.

In FIG. 2, first, a potential is applied to the gate electrode 23 to generate an electric field as shown by the arrow between the gate electrode 23 and the buried gate electrode 28, and a potential based on this electric field is applied to the electrode 28.

On the other hand, a channel 30 is induced in the substrate 24, and a pinch-off region 31 is formed near the drain region 25 side of this channel 30.
form.

Therefore, an electric field as shown by the arrow is generated between the electrode 28 and the substrate 24.

In this state, the carrier density at the end of the channel 30 on the source region 26 side is n.

Since it is considered that a current continuity relationship is approximately established between the carrier density n in the pinch-off region 31 and the carrier density n in the pinch-off region 31, (here, Vo is the carrier velocity at the side edge of the source region 26, Vp is the carrier velocity in the pinch-off region 31, and ■ is the channel current), so it is clear that v>v.

This means that in the pinch-off region 31, the carriers in the channel 30 have the highest energy among the carriers in the crystal.

In this specification, the pinch-off region has a broad meaning as a channel region where the carrier velocity of the channel approaches velocity saturation and becomes so-called hot.

Therefore, compared to the potential of the electrode 28 buried in the insulating film 22, the potential of the region 31 is higher in the case of a p-channel or lower in the case of an n-channel, even if the absolute value of the drain voltage is large. The obtained carriers are distributed between the channel 30 or the pinch-off region 31 and the electrode 28 on the source side of the pinch-off region and the pinch-off region 31.
is drawn into the insulating film 22 by the electric field between them, is accelerated and reaches the electrode 28, and eventually the first
The gate electrode 28 of is charged to the same polarity as the carriers of the channel 30.

As a result, the gate threshold voltage seen from the second gate of the transistor changes in the enhancement direction, so the voltage of the second gate electrode is set to a value between the gate threshold voltage before writing and the gate threshold voltage after writing. By setting , information of a transistor at one address in the array configuration can be read without a complicated unit cell configuration.

Next, in this charged state, the potential of the second gate electrode 23 is removed to make it, for example, the same potential as the substrate 24, and a voltage higher than the breakdown voltage with the substrate 24 is applied to the drain region 25.

In this way, avalanche precipitation occurs between the drain region 25 and the substrate 24, which causes a charge having the opposite sign to that of the carrier charge previously injected from the channel 30, based on the electric field between the electrode 28 and the breakdown point. The carriers are accelerated in the direction of the electrode 28 and injected into the insulating film 22, so that the electrode 28 is eventually charged to a polarity opposite to the previously charged state.

Regarding FIG. 2, according to the first method described above, information can be written or rewritten once written as desired by simply changing the bias conditions of the memory field effect transistor as a memory element. This can be done reliably, and the information once written can be retained without applying a bias to the element.

Therefore, even when a large number of memory unit cells having storage transistors according to the first method are incorporated into an actual device, it is extremely easy to select desired bits and write or rewrite information individually. .

Also, according to the configuration shown in FIG. 2 for realizing the method of the present invention,
Since it has the electrode 23, when carriers are injected from the pinch-off region 31, a potential that accelerates the injected carriers can be applied to the electrode 2B. The gate electrode 28 can be sufficiently charged, and therefore a storage field effect transistor with good performance as a storage element can be obtained.

Furthermore, since the number of hot carriers is proportional to the channel current, the larger the channel current value, the faster the first gate electrode can be charged.

Channel current can also be supplied by non-avalanche means.

For example, since the bias condition of the second gate electrode 23 is such that a large current can flow between the source and drain,
Charging can also be accelerated by passing current between the source and drain.

FIG. 3 shows a modification of the configuration shown in FIG. 2, in which the insulating film 2
The electrodes 33 buried in the electrodes 2 and 27 are of a so-called offset type that overlaps only a portion of the channel region.

According to this configuration, the effect shown in FIG. 2 is obtained, and the remaining portion of the channel region and the gate electrode 23 opposite thereto
Since an electric field 34 is formed directly between the pinch-off region 31 and the pinch-off region 31, the efficiency of carrier injection from the pinch-off region 31 can be further promoted by this electric field.

In this case, the electric field 34 can induce a channel 35 in the remaining portion of the channel region, so by changing and controlling the electric field 34, the field effect transistor 21 can be turned on and off more reliably than in the configuration shown in FIG. Off operation can also be controlled.

FIG. 4 shows another modification of the configuration shown in FIG. 2, in which a through hole 36 is provided across the thickness of the electrode 33.
In this way, an electric field 37 is directly formed between the electrode 23 and the opposing portions of the substrate 24 facing the through hole 36, so that a channel 38 is induced in the region of the substrate 24 facing the through hole 36 by this electric field 37. At the same time, a pair of pinch-off regions 39 and 39' may be formed at both ends thereof, respectively.

Therefore, the hot carriers in regions 39 and 39' are
Since the carriers are directly accelerated by the carriers, the injection speed and efficiency of the carriers can be further promoted.

Furthermore, FIG. 5 shows a modification of the configuration shown in FIG. 3, in which the electrode 3
4 has a configuration with both an offset structure similar to that shown in FIG. 3 and a through hole 36 similar to that shown in FIG. It also has the same effect.

Although I did not specifically mention FIGS. 2 to 5, in order to make the potential of the pinch-off region in these configurations suitable for reaching the buried second gate electrode, It is also effective to make the impurity concentration of the substrate in the pinch-off region and its vicinity higher than in other parts.

Next, an embodiment in which the storage transistor according to the above writing method is applied to an arbitrary address write/read memory (random access memory) will be described together with equivalent circuits shown in FIGS. 6 to 11.

In FIG. 6, 41 shows a unit cell among a large number of memory cells of an arbitrary address write/read memory, and the unit cell 41 has a "1" write/storage transistor Q1 and a "0"
Write transistor Q2 and address selection transistor Q
It is assumed that at least the transistors Q1 and Q2 are formed on the same semiconductor substrate.

The transistor Q1 is the field effect transistor 7 of FIG. 1, and has a source S1, a drain d, and a gate g, which correspond in sequence to the source region 3, drain region 2, and polycrystalline layer 6 of FIG.

The transistor Q2 is a field effect transistor 21 according to the present invention shown in FIG. 2, and has a source s1 and a drain corresponding to the source region 26, drain region 25, first gate electrode 28, and second gate electrode 23 in FIG. Area 1
has a gate g1 and a second gate g2.

The drain d of the transistor Q1 is connected to the source (or drain) of the transistor Q3, the drain (or source) of the transistor Q3 is connected to the address selection line X, and the source S of the transistor Q1 is connected to the common ground line G.

Also, the source S of the transistor Q2 is connected to the source (or drain) of the transistor Q3, and the drain d of the transistor Q2 connects the drain (or source) to the address selection line
The gates are connected to the sources (or drains) of transistors Q4 connected to the "O" write address selection line E, and the gate g1 of option 1 is connected to the transistor Q4 within the insulating film.
The second gate g2 is connected to the "0" write address selection line E.

Further, the gate of the transistor Q3 is connected to the "1" write and information read address selection line W.

In such a configuration, when writing "1" information to the transistor Q1, a voltage X whose absolute value is larger than the drain-to-substrate breakdown voltage HH of the transistor Q1 is applied to the line also gives a voltage vw with a large absolute value.

When such a bias condition is applied, the voltage Vw causes the transistor Q3 to conduct, and through this, the voltage Vx is applied to the drain d of the transistor Q1.

Therefore, as described above with reference to FIG. 1, avalanche breakdown occurs between the drain d and the substrate of the transistor Q1, thereby charging the gate g and the first gate Fg+ of the transistor Q2 connected thereto.

In this case, when the substrate is n-type, a negative charge is applied to the gate of the transistor Q1 and hence to the gate g1 of the transistor Q2.
When they are p-type, they are charged with positive charges.

Accordingly, transistors Q2 and Ql are then rendered conductive, with their respective gates maintaining their charged states.

Thus transistor Q1. "1" information is written in Q2.

Next, when writing "0" information using the transistor Q2, apply a voltage H to the line
Apply a moderately high voltage.

Transistor Q4 is then fully conductive, through which voltage Vx on line X is applied to the drain d of transistor Q2 through Q4, causing transistor Q2 to be in a pinch-off condition, as described above with respect to FIG. , the carrier flowing through that channel is the first game F
gt is therefore charged to the gate of transistor Q1.

The charge of the carrier at this time has the opposite sign to that of the charge charged to the gates of transistors Q2 and Ql when writing the above-mentioned "1" information.
(Therefore, Q2) is then rendered non-conductive.

Thus transistor Q1. rOJ information is written to Q2.

In this way, "1" or rO stored in transistor Q1
When reading J information, voltage H is applied to line W.

In this way, transistor Q3 becomes conductive, but at the time of this conduction, when "1" is written in transistor Q1, since transistor Q1 is in a conductive state, a voltage is passed through line X - transistor Q3 - Q1 - line G. Current flows, while '
When "0" is written, transistor Q1 is non-conductive, so no current flows through it.

Therefore an external circuit (not shown) connected between lines X and G
By detecting the presence or absence of current at this time,
The memory contents are read.

Unit cell 41 in the above write or read mode
The bias conditions are summarized in Table 1.

FIG. 7 shows another embodiment of the unit cell 41, in which case the source S of the transistor Q2 and the source (or drain) of the transistor Q3 are disconnected from each other and connected to the line G in the same manner as in FIG. It has the following configuration.

Therefore, although corresponding parts are shown with the same reference numerals, in the case of FIG. 6, when writing "O", based on the charge to the first gate g1 of the transistor Q2, this charge is passed until the transistor Q1 becomes non-conductive. A current is made to flow through the source S of the transistor Q2, but in the case of FIG. 7, on the other hand, the gate g+ can be sufficiently charged through the line G.

8 and 9, transistors Q2 and Q4 of FIGS. 6 and 7 are replaced with a single transistor Q5, in which case transistor Q5 is replaced by a single transistor Q5. The field effect transistor 21 has the so-called offset structure described above.

In this case, except that the drain d of the transistor Q5 is directly connected to the line X, the configurations are similar to those in FIGS. 6 and 7, respectively.

In these configurations, as described above with reference to FIG. 2, when the voltage at the second gate g2 is 0, the transistor Q5 is cut off because the channel 35 (FIG. 3) is not induced; When the voltage is close to the voltage HH, the channel 35 becomes conductive.

Therefore, transistor Q5 is similar to transistors Q2 and Q4.
Both of the functions (FIG. 6 or FIG. 7) can be achieved, and the structure of the unit cell as a whole can be simplified by reducing the number of transistors by one.

In these cases, the bias conditions shown in Table 1 may be applied.

In the configurations of FIGS. 6 to 9 described above, if the channel lengths of transistors Q2 and Q5 are made longer than the channel length of transistor Q1, and the current at the time of writing "0" is limited to a small value in advance, , the power consumption of the unit cell 41 as a whole can be miniaturized.

FIG. 10 shows yet another embodiment of the unit cell 41.

In this case, the unit cell 41 includes an address selection and current limiting transistor Q7, and a write and write transistor Q7.
6.

Transistor Q7 is a conventional insulated gate field effect transistor, and transistor Q6 is a field effect transistor 21 with an offset structure as described above with respect to FIGS. 3 and 5.

The source S of the transistor Q6 is the drain (or source)
is connected to the source (or drain) of the transistor Q7 connected to the common address selection line W, and the drain d is connected to the common address selection line E.

On the other hand, the second gate g2 of the transistor Q6 is connected to the common address selection line EY, and the gate of the transistor Q7 is connected to the common address selection connection line Y.

In this configuration, bias conditions as shown in Table 2 are applied when writing "1" information to transistor Q6, when writing "O" information, and when reading out information.

In this way, when writing "1", the transistor Q.

An avalanche breakdown occurs between the source S and the substrate, and as a result, a "1" write is performed by charging the gate g1 with the injected carriers, and a "0" write is performed by applying a voltage of a dog value to the line EY. The transistor Q6 is pinched off, and as a result, the injected carriers cause the gate Fgx
Further, reading is performed by making transistor Q7 conductive, and as a result, depending on whether or not current flows through transistor Q6, if current flows, "1" information is transmitted, and if it does not, "O" information is transmitted. It is something to read out.

According to the configuration shown in FIG. 10, the number of transistors is only two, so that the unit cell 41 can be further simplified.

FIG. 11 shows still another embodiment of the unit cell 41. In this case, a transistor Q having the same channel type as the transistor Q3 is connected in parallel, the gate of the transistor Q9 is connected to the W line, and the gate g2 of the transistor Q6 is connected in parallel with the transistor Q3. It has the same structure as that shown in FIG. 10, except that the gates of Q3 and Q3 are connected to the Y line, and the line EY is omitted.

In such a configuration, information is written to the transistor Q6,
Alternatively, the bias conditions for reading this are set as shown in Table 3.

Here, in writing "1" when the voltage Vw of the line W is applied to the source S of the transistor Q6, the voltage Vy of the Y line and therefore the voltage of the second gate g2 is H
-H
It is designed to increase by an amount corresponding to a fraction of H.

Then, a voltage 7 of H or HH is applied to the line Y of all the units connected to the common line W except for the unit that should write "1", and the specified address is The arrangement is such that a voltage of O or a voltage of the opposite sign Y is applied only to the line Y.

Therefore, when writing "1", the transistor Q9 becomes conductive, and through this the voltage Vw of the line W is applied to the source S of the transistor Q6.
The voltage ``Y'' of the long line Y applied to the second gate g2 is applied to the second gate g2, and 11'' is written into the transistor Q6.

Also, when writing "0", the voltage on the line Y is applied to the transistor Q.
6 and Q8 are made conductive, and the voltage vF of line E is set to H.
state to obtain a pinch-off state of transistor Q6, and further reading makes transistor Q8 conductive, resulting in a pinch-off state of transistor Q6.

Depending on whether or not current flows, if current flows, "1" is read out, and if it does not, "0" is read out.

The above array configuration unit cells are capable of electrical rewriting one bit at a time, but those that do not require this are address selection transistors Q3, sQ4-Q? ,Q
s, Q9 can be made unnecessary as described above.

As described above, according to the present invention, it is possible to obtain a semiconductor memory that combines the high speed of readout inherent in semiconductor memory and the non-volatility of storage, which has conventionally been put into practical use only by magnetic memory. , to fabricate such a memory, conventional silicon gate technology or molybdenum gate technology is used, without the need for any other special technology,
It can be easily manufactured at high density.

Furthermore, according to the present invention, writing and rewriting can be performed at a lower voltage than conventional methods, and the speed of writing and rewriting can be controlled by the amount of carrier supplied. This method has the advantage of being easier to use than the other methods.

In the above explanation, the stored content is rlJ rOJ digital information, but it is clear that it can be used to store nonvolatile analog information.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a field effect transistor for explaining a conventional information writing method, and FIG. 2 is a cross-sectional view of a storage field effect transistor for explaining an example of a nonvolatile memory writing/rewriting method according to the present invention. 3 to 5 are sectional views showing the configuration of a memory field effect transistor for realizing the method of the present invention, and FIGS.
FIG. 6 is an equivalent circuit diagram showing an example of a memory unit cell including the storage field effect transistor shown in FIGS. In the figure, 21.45.70... Memory field effect transistor, 22... Gate insulating film, 23...
...Second gate electrode, 24...Semiconductor substrate, 25...Drain region, 26...
Source region, 27...Insulating film, 28...
・First gate electrode, 29.47...depletion layer,
30, 35. 38... Channel, 31° 39.
39'...Pinch-off area, 36...
Through hole, 41.50...Memory unit cell, Q
1 to Q14...transistor.

Claims (1)

[Claims] 1 One type of carrier supplied to a channel induced on the semiconductor surface in contact with an insulating film is converted into a hot carrier by a high electric field formed within the semiconductor surface, and a carrier is formed between the semiconductor surface and the insulating film in contact with it. A method for writing in a nonvolatile memory, characterized in that writing is performed by injecting the hot carriers into the insulating film beyond an energy barrier.