JPS6252956B2 - - Google Patents

Description

[Detailed description of the invention]

Semiconductor memories have become capable of large-scale integration (hereinafter referred to as LSI) due to the fact that stored information can be retrieved easily and at high speed as electrical signals, and with the development of integrated circuit (hereinafter referred to as IC) technology. Due to its improved reliability, it has recently been used as a high-speed memory device for electronic computers. However, unlike magnetic memories, semiconductor memories have the disadvantage that when the supply of bias electrodes is cut off, the stored contents disappear (hereinafter referred to as volatility). In order to obtain a semiconductor memory that does not have this drawback, research has been carried out on the memory function of semiconductor glasses such as chalcogenide glass, but this has not yet reached a practical stage. In addition, as a non-volatile semiconductor memory, in the field of silicon semiconductor ICs, MNOS field effect transistors having a structure of metal (M), silicon nitride film (N), silicon oxide film (O), and silicon (S) are used. However, in this case, the silicon oxide film (SiO ₂ ) must be made thin enough to allow carriers on the semiconductor surface to tunnel, so pinholes are likely to occur in the silicon oxide film, and the storage mechanism is likely to be trapped. Because of this, there is a risk that productivity and reproducibility may be degraded due to the position, and for this reason, it has not been put to practical use in electronic computers. However, in the field of semiconductor memory other than these,
There is a read-only memory (hereinafter referred to as ROM) that takes advantage of the high bit density and high speed of semiconductor memory to read fixed storage contents. This ROM
There are two types of configuration methods, one of which is to provide fixed information to the glass mask used for photo-etching when making an IC. The other is that when making an IC, it is made uniformly regardless of the content to be stored.
This method then electrically writes information according to the content to be stored. Three methods of the latter method are known.
That is, the first method is to fuse the wiring with a current pulse, the second method is to use the memory characteristics of alumina traps, and the third method is to use the memory characteristics of alumina when no channel current flows. Due to avalanche breakdown of the junction between the drain and the semiconductor substrate, a carrier having the same shape as the semiconductor substrate is injected into the oxide film, and this carrier charges the polycrystalline silicon thin film layer embedded in the oxide film to write information. This is how it was done. The present invention relates to a new writing/rewriting method that is an improvement on the third method among these three methods, and first, the conventional method will be explained in more detail with reference to FIG. In this case, as shown in FIG. 1A, a drain region 2 and a source region 3 having a conductivity type opposite to that of the substrate 1 and having a high impurity concentration, a gate silicon oxide film 4, and a silicon A field effect transistor 7 consisting of a silicon polycrystalline layer 6 buried between oxide films 4 and 5 is formed. In this field effect transistor 7, when the drain voltage is increased, a depletion layer 8 spreads from the drain region 2 into the substrate 1, but especially in the portion 9 below the silicon polycrystalline layer 6, an arrow appears. As shown, the electric field is concentrated and becomes higher than other parts of the depletion layer 8, and finally reaches a critical electric field for avalanche. At this time, this part 9 has an electron 10 as shown in FIG. 1B.
An electron-hole pair of the hole 11 is generated, and if the substrate 1 is, for example, an n-type, the electron 10 is moved by the arrow 12 due to the electric field.
As shown in FIG. 2, it is accelerated in the direction of the oxide film 4, thereby obtaining high energy and being injected into the oxide film 4. The electrons 10 injected in this manner pass through the oxide film and reach the silicon polycrystalline layer 6, charging it negatively. On the other hand, the hole 11 is moved by the arrow 1 due to the electric field.
3 to the drain region 2. In this way, information can be written by obtaining a charged state of the silicon polycrystalline layer 6, and on the other hand, information once written in this way can be erased in principle by irradiating the field effect transistor 7 with ultraviolet rays or X-rays. Can be done. However, when such a semiconductor memory is used in an actual device, it is generally housed in a package and fixedly wired inside the device's casing. It is actually extremely difficult to take out the data each time and irradiate it with X-rays, and furthermore, it is practically impossible to selectively rewrite only arbitrary bits in the memory. Therefore, the present invention takes the above-mentioned points into consideration, and provides a non-volatile memory that can not only write information but also rewrite information even if the package is installed in a device. write·
The present invention provides a rewriting method, a new writing/rewriting method that has never existed before, and a storage device that implements this method. The basic feature of the present invention is to form a high electric field region in a semiconductor substrate, and select one of two types of carriers having different signs depending on the information to be written, and place it in a high energy state. By injecting energy into the insulating film from the surface of the semiconductor substrate at an accelerated rate beyond the energy barrier formed by the insulating film and the semiconductor substrate, different states of charge are obtained, thus erasing or erasing the memory contents. It was made so that it could be rewritten. In addition, in the present invention, as a first new method for injecting carriers in a semiconductor substrate into an insulating film, hot carriers are obtained in the pinch-off (high field velocity saturation) region of a channel of a field effect transistor and then injected. Adopt a method to do so. Furthermore, in the present invention, as a second method for injecting carriers into an insulating film, two types of junctions are formed in a semiconductor substrate, and carriers obtained by sequentially causing avalanche deposition in these junctions are used. A method of injecting is adopted. The features of the writing/rewriting method according to the present invention will become clear from the detailed description below in conjunction with the drawings. First, an example of the first storage method according to the embodiment of the present invention shown in FIG. 2 will be described. In this case, the storage field effect transistor 21 has a second gate electrode 23 on an insulating film 27 made of a silicon oxide film. The structure is similar to that of the field effect transistor 7 shown in FIG. 1 except for the provision. In FIG. 2, 22 is a gate insulating film, 24 is a semiconductor substrate, 25 is a drain region, 26 is a source region, 27 is an insulating film continuous with the gate insulating film 22, and 28 is the gate insulating film 22 and the semiconductor substrate. Insulating film 2
The first gate electrode buried between the electrodes 7 and 29 represents a depletion layer, respectively. In order to inject carriers in the substrate 24 into the gate insulating film 22 of the field effect transistor 21, it is necessary to give the carriers enough energy to cross the barrier between the substrate 24 and the insulating film 22. For this reason, in the case of FIG. 2, the field effect transistor 21 is put into a pinch-off state in order to obtain a charged state of 1 on the gate electrode 28, thereby making the carrier a hot carrier near the drain side of the channel, which is connected to the insulating film. Inject into 22. On the other hand, in order to obtain a different charging state of the gate electrode 28, the drain voltage is increased to cause avalanche breakdown at the portion of the surface of the substrate 24 below the gate electrode 28 in contact with the drain region 25, thereby causing the case shown in FIG. Similarly, carriers generated in the depletion layer 29 of the substrate 24 are injected into the insulating film 22. In this case, the sign of the carrier charge injected by the former is opposite to that of the latter, and therefore the gate electrode 28 in the above-mentioned first charged state is converted to another charged state with the opposite sign. be able to. Therefore, it is possible to erase the information once written to the transistor 21 (i.e., the gate electrode 28 is in a state of charge of 1) and write the opposite information (i.e., the gate electrode 28 is in a different state of charge); The opposite is also possible. The above is an overview of the method of the present invention with respect to FIG. 2, and next, it will be described in more detail along with the configuration for realizing this method. In FIG. 2, first, a potential is applied to the gate electrode 23 to generate an electric field as shown by the arrow between the gate electrode 23 and the buried gate electrode 28, and a potential based on this electric field is applied to the electrode 28. On the other hand, a channel 30 is induced in the substrate 24, and a pinch-off region 31 is formed near the drain region 25 side of the channel 30. Therefore, an electric field as shown by the arrow is generated between the electrode 28 and the substrate 24. In this state, there is approximately a current continuity relationship in the channel 30 between the carrier density n _p at the end of the channel 30 on the source region 26 side and the carrier density n _p in the pinch-off region 31. Since it is considered that n _p v _p = n _p v _p = I/q, n _p ≫ n _p (here, v _p is the carrier velocity at the side edge of the source region 26, and v _p is the carrier velocity at the side edge of the pinch-off region 31. It is clear that there is a relationship between the carrier speed and the channel current (I is the channel current), so that v _p ≫ v _p . This means that in the pinch-off region 31, the carriers in the channel 30 have the highest energy of the carriers in the crystal. In this specification, the term "pinch-off region" has a broad meaning as a channel region in which the carrier velocity of the channel is close to velocity saturation and has become a so-called hot region. Therefore, the potential of the region 31 is higher in the case of a p channel or lower in the case of an n channel than the potential of the electrode 28 buried in the insulating film 22, even if the absolute value of the drain voltage is large.
On the source side of the pinch-off region and the pinch-off region 31, the carriers are drawn by the electric field between the channel 30 or the pinch-off region 31 and the electrode 28, are injected into the insulating film 22, are accelerated, and are injected into the electrode 28. will reach,
Eventually, the first gate electrode 28 is charged to the same polarity as the carrier in the channel region 30. As a result, the gate threshold voltage seen from the second gate of the transistor changes more in the direction of enhancement, so the voltage of the second gate electrode is set between the gate threshold voltage before writing and the gate threshold voltage after writing. If this value is set, the information of the transistor at one address in the array configuration can be read out without a complicated unit cell configuration. Next, in this charged state, the second gate electrode 2
3 is removed to make it, for example, the same potential as the substrate 24, and a voltage higher than the breakdown voltage between the drain region 25 and the substrate 24 is applied. Thus, an avalanche of charge occurs between the drain region 25 and the substrate 24, which causes a charge having the opposite sign to that of the carrier charge previously injected from the channel 30, due to the electric field between the electrode 28 and the breakdown point. The carriers are accelerated in the direction of the electrode 28 and injected into the insulating film 22, and the electrode 28 is eventually charged to the opposite polarity to the previously charged state. Regarding FIG. 2, according to the first method described above, information can be written or rewritten once written as desired by simply changing the bias conditions of the memory field effect transistor as a memory element. This can be done reliably, and the information once written can be retained without applying a bias to the element. Therefore, even when a large number of memory unit cells having storage transistors according to the first method are incorporated into an actual device, it is extremely easy to select desired bits and write or rewrite information individually. obtain. Further, according to the configuration shown in FIG. 2 for realizing the first method, since the electrode 23 is provided, the pinch-off region 3
When carriers are injected from the first gate electrode 28, a potential can be applied to the electrode 28 to accelerate the injected carriers.
Therefore, it is possible to obtain a memory field effect transistor that can sufficiently charge the battery and has good performance as a memory element. Furthermore, since the number of hot carriers is proportional to the channel current, the higher the channel current value, the faster the first
can charge the gate electrode. The channel current is also supplied by avalanche precipitation from the substrate, but since the bias condition of the second gate electrode 23 is such that a large current can flow between the source and drain, it is necessary to flow the current between the source and drain. This also speeds up charging. FIG. 3 shows a modification of the configuration shown in FIG. 2, and in this case,
The electrodes 33 embedded in the insulating films 22 and 27 are
It has a so-called offset configuration in which it overlaps only a portion of the channel area and the remaining area. According to this configuration, the effect shown in FIG. 2 is obtained, and since an electric field 34 is directly formed between the remaining portion of the carrier region and the portion of the gate electrode 23 facing thereto, this electric field Accordingly, the efficiency of carrier injection from the pinch-off region 31 can be further promoted. Furthermore, in this case, the channel 35 can be induced by the electric field 34 in the remaining portion of the channel region, so by changing and controlling the electric field 34, the field effect transistor 21 can be turned on and off more reliably than in the configuration shown in FIG. Off operations can also be created. FIG. 4 shows another modification of the structure shown in FIG. 2, in which the electrode 33 is provided with a through hole 36 across its thickness, so that the electrode 23 and the substrate 2
Since an electric field 37 is directly formed between the opposing portions of the substrate 24 facing the through hole 36, a channel 38 is induced in the area of the substrate 24 facing the through hole 36, and a channel 38 is induced at each end position of the channel 38. A pair of pinch-off regions 39 and 39' may be formed. Therefore, the hot carriers in regions 39 and 39' will be directly accelerated by the electric field 37, which can further enhance the carrier injection rate and efficiency. Furthermore, FIG. 5 shows a modification of the configuration of FIG. 3, in which the electrode 34 has an offset structure similar to that shown in FIG. 3 and a through hole 36 similar to that shown in FIG. , and thus has the same effects as described above with respect to FIGS. 3 and 4, respectively. Although I have not specifically mentioned FIGS. 2 to 5, in order to make the potential of the pinch-off region in these configurations suitable for reaching the buried second gate electrode, especially The impurity concentration of the substrate in the pinch-off region and its vicinity is
It is also effective to make it larger than other parts. Next, an embodiment in which the storage transistor according to the first storage method described above is applied to an arbitrary address write/read memory (random access memory) will be described together with equivalent circuits shown in FIGS. 6 to 11. In FIG. 6, numeral 41 indicates a unit cell among a large number of memory cells of the arbitrary address write/read memory, and the unit cell 41 has a "1" write/storage transistor _Q1 and a "0" write transistor _Q2. and,
It is assumed that it has an address selection transistor Q ₃ and a "0" write address selection transistor Q ₄ , and that at least transistors Q ₁ and Q ₂ are formed on the same semiconductor substrate. The transistor Q ₁ is the field effect transistor 7 shown in FIG. 1, and has a source s, which corresponds to the source region 3, drain region 2, and polycrystalline layer 6 in sequence in FIG.
It has a drain d and a gate g. The transistor Q ₂ is a field effect transistor 21 according to the present invention shown in FIG. , a drain d, a first gate g ₁ and a second gate g ₂ . The drain d of transistor _Q1 is a transistor
The drain (or source) of the transistor Q ₃ is connected to the address selection line X, and the source s of _the transistor Q ₁ is connected to the common ground line G. Also transistor
The source s of Q ₂ is connected to the source (or drain) of transistor Q ₃ , and the drain d of transistor Q ₂ connects the drain (or source) to address selection line X and the gate to "0" write address selection line E. The first gate g1 is connected to the source (or drain) of the transistor _Q4 connected to each other, while the first gate _g1 is connected to the gate g of the transistor _Q1 within the insulating film, and the second gate _g2 is connected to the "0" write address selection. Connected to line E. Further, the gate of the transistor _Q3 is connected to the "1" write and information read address selection line W. In such a configuration, "1" is applied to transistor _Q1 .
When writing information, connect the drain of transistor Q ₁ to line X. A voltage V _X having an absolute value larger than the inter-substrate breakdown voltage HH is applied, and a voltage V W having an absolute value larger than the voltage _HH is applied to one line W. When such a bias condition is applied, the voltage V _W causes the transistor Q ₃ to conduct, and through this, the voltage V _X is applied to the drain d of the transistor Q ₁ . Therefore, as described above in FIG. 1, avalanche breakdown occurs between the drain d and the substrate of the transistor _Q1 , and the gate g and the first gate _g1 of the transistor _Q2 connected thereto are charged with charge. be done. In this case, the gate of the transistor Q ₁ and the gate g ₁ of the transistor Q ₂ are charged with negative charge when the substrate is n-type, and with positive charge when the substrate is p-type.
Transistors Q ₂ and Q ₁ are therefore rendered conductive thereafter with their respective gates maintaining their charged states. Thus the transistor
"1" information is written to Q ₁ and Q ₂ . Next _, when writing "0" information using transistor _Q2 , apply voltage H to line give. Transistor Q ₄ is then fully conductive _, through which _the voltage _{V 2} is in a pinch-off state, and the carrier flowing through its channel charges the first gate g ₁ and thus the gate of transistor Q ₁ . The carrier charge at this time has the opposite sign to that of the charge charged to the gates of transistors Q ₂ and Q ₁ when writing the above-mentioned "1" information, and therefore, the sign of the charge charged to the gates of transistor Q ₁ (and therefore Q ₂ ) is then brought into a non-conducting state.
In this way, "0" information is written into transistors Q ₁ and Q ₂ . “1” stored in transistor _Q1 like this
Alternatively, when reading "0" information, voltage H is applied to line W. In this way, transistor Q ₃ becomes conductive, but at the time of this conduction, when "1" is written in transistor Q ₁ , transistor Q ₁ is in a conductive state, so that the line X - transistor Q ₃ - Q ₁ - Current flows through line G, whereas when a ``0'' is written, no current flows through transistor Q ₁ as it is non-conducting. Therefore, by detecting the presence or absence of current at this time by an external circuit (not shown) connected between lines X and G, the stored contents are read out. Table 1 summarizes the bias conditions of the unit cell 41 in the above writing or reading mode.

[Table] FIG. 7 shows another embodiment of the unit cell 41, in which case the source s of the transistor _Q2 in FIG.
It has the same configuration as if the connection to the source (or drain) of transistor _Q3 was removed and connected to line G. Therefore, although corresponding parts are shown with the same reference numerals, in the case of FIG. 6, when writing "0", based on charging to the first gate _g1 of transistor _Q2 ,
Current is made to flow through the transistor Q ₁ to the source s of the transistor Q ₂ until it becomes non-conductive, but in the case of Fig. 7, on the other hand,
The gate _g1 can be sufficiently charged through the line G. 8 and 9 replace transistors Q ₂ and Q ₄ of FIGS. 6 and 7, respectively, with _a single transistor Q ₅ ; It consists of the field effect transistor 21 of the so-called offset structure described above in FIG. In this case, the structure is similar to that of FIGS. 6 and 7, respectively, except that the drain d of the transistor _Q5 is directly connected to the line X. In these configurations, transistor Q ₅ is the second
As mentioned above with respect to the figure, when the voltage on the second gate g ₂ is 0, the channel 35 (FIG. 3) is not induced, resulting in a cutoff state, while when the voltage on the gate g ₂ is close to the voltage HH, the channel 35 It becomes conductive. Therefore, transistor _Q5 can perform both the functions of transistors _Q2 and _Q4 (FIG. 6 or FIG. 7), and the structure of the unit cell as a whole can be simplified by reducing the number of transistors by one. In these cases, the bias conditions shown in Table 1 may be applied. In the configurations shown in FIGS. 6 to 9 described above, the channel lengths of transistors Q ₂ and Q ₅ are
By making the channel length longer than the channel length of _Q1 and limiting the current at the time of writing "0" to a small value in advance, the power consumption of the unit cell 41 as a whole can be minimized. FIG. 10 shows yet another embodiment of the unit cell 41. In this case, unit cell 41 has an address selection and current limiting transistor _Q7 , and a write and storage transistor _Q6 . Transistor Q ₇ is a conventional insulated gate field effect transistor, and transistor Q ₆ is an offset structured field effect transistor 21 as described above with respect to FIGS. 3 and 5. The source s of the transistor Q ₆ is connected to the source (or drain) of a transistor Q ₇ whose drain (or source) is connected to the common address selection line W, and whose drain d is connected to the common address selection line E. On the other hand, the second gate _g2 of the transistor _Q6 is connected to the common address selection line EY, and the gate of the transistor _Q7 is connected to the common address selection connection line Y. In such a configuration, "1" is placed in transistor _Q6 .
Bias conditions as shown in Table 2 are given for writing information, writing "0" information, and reading out information.

[Table] In this way, when writing "1", the transistor
Avalanche deposition between the source s and the substrate of Q ₆ occurs,
As a result, "1" is written by charging gate _g1 with the injected carrier, and "0" is written.
Writing is done by applying a large voltage to line EY, pinching off transistor Q ₆ and charging gate g ₁ with the resulting injected carrier, and reading is done by applying a large voltage to line EY, pinching off transistor Q ₆ and charging gate g 1 with the resulting injected carrier.
As a result, depending on whether current flows through transistor Q ₆ or not, if it flows, "1" information is transmitted.
If there is no flow, "0" information is read respectively. According to the configuration of FIG. 10, the number of transistors is only two, so that the unit cell 41 can be further simplified. FIG. 11 shows still another embodiment of the unit cell 41. In this case, a transistor _Q9 of the same channel type is connected in parallel with the transistor _Q3 , and the gate of the transistor _Q9 is connected to the W line.
It has the same configuration as the configuration shown in FIG. 10, except that the gate g ₂ of Q ₆ and the gate of Q ₃ are connected to the Y line, respectively, and the line EY is omitted. In this configuration, the bias conditions when writing information to or reading information from the transistor _Q6 are as shown in Table 3.

[Table] Here, when the transistor Q ₆ is written to "1" with the voltage V _W of the line W applied to its source s, the voltage V _Y of the Y line and therefore the voltage of the second gate g ₂ becomes 0. The avalanche breakdown voltage at the source junction in the case of H to HH is made larger by an amount corresponding to a fraction of H to HH compared to the case of . Then, a voltage V Y of H or HH is applied to the line Y of all the units connected to the common line W except for the unit to which "1" should be written, and the voltage V _Y of H or HH is applied to the line Y of all the units connected to the common line W. A voltage V _Y of 0 or the opposite sign is applied only to the line Y of . Therefore, when writing "1", the transistor _Q9 becomes conductive, and through this the voltage V _W of the line W is applied to the transistor Q9.
The voltage V Y applied to the source s of Q ₆ and on the line _Y is applied to the second gate g ₂ to write "1" into the transistor Q ₆ . Furthermore, when writing "0", transistors Q ₆ and Q ₈ are made conductive by the voltage V _Y on the line Y, and the voltage V _E on the line E is made H to obtain a pinch-off state of the transistor Q ₆ . ₈ is made conductive, and depending on whether or not a current flows through the transistor _Q9 , "1" is read out if current flows, and "0" is read out if no current flows. According to the first memory method, 2
In order to reach the seed carrier as needed,
Depending on the information to be written, carrier injection occurs either by avalanche breakdown of the drain-to-semiconductor substrate or source-to-substrate junction, or from a pinch-off region of the channel on the semiconductor surface. Writing to non-volatile memory
It became clear that rewriting could be done. Also second
The storage transistors and unit cells for realizing this storage method have been described with reference to FIGS. 11 to 11. Next, the second storage method according to the present invention will be described in detail. The second write/rewrite method sequentially charges two types of charges to a substance embedded in an insulator, and creates two types of junctions with different impurity concentrations or materials under the embedded substance. , two different types of carriers are respectively injected into the insulator by avalanche deposition of these junctions. An example of a storage field effect transistor implementing such a method is shown at 45 in FIG. The transistor 45 has a conduction type source region 26 and a drain region 25 of opposite sign to the semiconductor substrate 24,
Similar to the structure shown in FIG. 1, the first gate electrode 28 is embedded between the gate insulating film 22 on the substrate 24 and the insulating film 27 continuous thereto. In this case, a region 46 having a conductivity type different from that of the source region 26 and having a high concentration of impurity is formed in the source region 26. On the other hand, the impurity concentration of the source region 26 is lower than that of the gate electrode 28.
The thickness is selected to be low so that the depletion layer 47, which is thicker than the thickness of , spreads between the region 26 and the depletion layer 47 . In the above configuration, if avalanche occurs in the region near the surface of the substrate under the gate electrode 28 at the junction between the drain region 25 and the substrate 24, it will occur in the same manner as described above with reference to FIG. Carriers from the substrate 24 are injected into the insulating film 22 from that region, thereby charging the electrode 28 to a state of charge of 1. In this charging state, the surface of the region 26 of the gate electrode 28 has changed in a direction in which an inversion channel is difficult to be induced, and as will be described later, a second gate electrode is provided on the first gate electrode with an insulating film interposed therebetween. As seen from this second gate electrode in the case, region 46, substrate 2
The threshold voltage of the field effect transistor whose source and drain are the surfaces of 4 is changing more in the direction of enhancement. On the other hand, if avalanche occurs in the region 48 under the electrode 28 at the junction between the source region 26 and the region 46 formed therein, the source will flow from this region 48 into the insulating film 22. Carriers in region 26 (whose charge is of opposite sign to that of the carriers injected from substrate 24) are injected, thereby charging electrode 28 to another state of charge. In this charged state, the substrate surface under the gate electrode 28 has changed in a direction in which an inversion channel is difficult to be induced, and as will be described later, a second gate electrode is provided on the first gate electrode with an insulating film interposed therebetween. In this case, the gate threshold voltage seen from the second gate has changed to the enhancement side, so the threshold voltage when no writing is performed is designed as enhancement, and this threshold voltage and the avalanche breakdown in region 48 are By setting the voltage of the second gate electrode between the subsequent gate threshold voltage, the transistor at one address in the array configuration can be read out without a complicated unit cell configuration. By obtaining different states of charge in this manner, information can be written even with this field effect transistor 45, and the state of charge of one of the electrodes 28 can be rewritten to another state of charge (or vice versa). By charging the battery, the stored contents can be rewritten as needed. Therefore, the same effects as the above-mentioned first method can be obtained also by this second method. In the configuration shown in FIG. 12, even if the region 46 is formed of a material different from the semiconductor substrate 24 and the region 26 by a heterojunction, a shotgun junction, etc., the same effect as in the above case can be obtained. It's obvious that you can get it. Further, FIG. 13 shows an embodiment in which an emitter junction and a collector junction of a transistor are used as two types of pn junctions. In the figure, the buried electrode 28 is a part 109 of a junction (referred to as an emitter junction) between the emitter region 106 and the base region 105 that is in contact with the semiconductor surface through the gate insulating film 22;
Part of the surface of base region 105 and base region 10
Part 1 of the junction between 5 and the collector region 102 (referred to as collector junction) in contact with the semiconductor surface
08, and the buried electrode 28 is buried in an insulating film 27 connected to the gate insulating film 22. The emitter region 106 is reverse biased with respect to the base region 105 and the surface portion 109 of the emitter junction
By causing avalanche breakdown in the base region 105, majority carriers (holes in the npn transistor, electrons in the pnp transistor) are injected into the insulating film 22,
Charge the embedded electrode 28. By reverse biasing the base region 105 with respect to the collector region 102 and causing avalanche breakdown at the surface portion 108 of the collector junction, the majority carriers in the collector region 102 are injected into the insulating film 22 and the buried electrode 28 is Charge in the direction of opposite sign. These two charging states are made to correspond to information "1" or "0", respectively, and a junction that causes avalanche breakdown is selected depending on the information to be stored or written. The method of detecting information is to determine whether it is "1" or "0" based on the magnitude of the collector current when a constant base current is passed. This takes advantage of the fact that the current amplification factor of bipolar transistors is highly dependent on the surface condition of the base region. In other words, the fact that the state of the surface of the base region below the buried electrode 28 depends on the charged state of the buried electrode 28 is used. When the implanted electrode is more positively charged, the
In an npn transistor, the current amplification factor is small, and therefore the value of the collector current is also small compared to other charging states. The opposite is true for pnp transistors. In the embodiment shown in FIG. 13, at least the emitter region 106 under the buried electrode 28 and the base region 1
05. The collector region 102 needs to be formed so that the impurity concentration decreases in this order. The depletion layer spreads more toward the base region at the emitter junction and toward the collector at the collector junction, respectively.
This is because the carrier needs to be injected from there. However, in the portion other than under the buried gate electrode 28, the collector contact 107 and the collector buried layer 1
01, the impurity concentration may be higher than that of the base region 105, or if a region with a higher impurity concentration, such as the layer 101, is provided below the base region, the region 106 is used as the collector, and the regions 101 and 1
02 can be used as an emitter. In this case, the impurity concentration relationship is reversed at the surface below the first gate electrode 28. Note that 104 is a region for base contact and for blocking a channel (which may occur on region 105);
3 is a separation layer, and 100 is a substrate. When a channel is formed on the surface of region 105, region 105 is used as a channel forming region, and regions 106 and 10
It operates as a storage field effect transistor with one of the transistors 2 as a source and the other as a drain. Also the 12th
Similarly in the figure, since a channel may be formed on the surface of the region 26 as described later, in this case, the region 26 is used as a channel forming region, and a field effect transistor with one of the region 46 and the substrate 24 as a source and the other as a drain is formed. operates as Although FIG. 13 shows an isolated transistor structure, the isolation layer 103 and the collector buried layer 1
Even if there is no 01 and the collector region 102 is constructed from the substrate, for example, in FIG. 12, with the region 46 as the emitter, the region 26 as the base, and the substrate 24 as the collector, it is possible to sufficiently function as a memory element. be. Next, an embodiment in which the storage transistor according to the storage method described above with reference to FIG. 12 is applied to an arbitrary address write/read memory will be described with reference to FIGS. 14 to 18. In FIG. 14, 50 indicates one of a number of memory unit cells in the memory, and unit cell 50
has an address selection transistor Q ₁₁ , a storage transistor Q ₁₀ , and a current limiting transistor Q ₁₂ . As shown in FIG. 15 corresponding to FIG. 14, the transistor Q ₁₀ has a drain d, a source s, and a gate g ₁ corresponding to a drain region 25, a source region 26, and a first gate electrode 28 in this order.
In this case, transistor Q ₁₂ forms a region 51 of a conductivity type different from that of transistor Q ₁₀ in source region 26 (FIG. 15), and this region 51
It is a field effect transistor having a drain d, a region 46 as a source, and a gate electrode 53 on a gate insulating film 52 as a gate. As is clear from the above, the configuration shown in FIG. 15 has a transistor in the source region 26.
It has the same configuration as in FIG. ₁₂ , except that Q12 is configured. The drain d of the transistor _Q10 is a transistor whose drain (or source) is connected to the common write line W and whose gate is connected to the common address selection line Y.
It is connected to the source (or drain) of _Q11 , and the source s is connected to the common ground line G. Alternatively, the drain d of the transistor Q ₁₂ formed and connected as a source in the source s of the transistor Q ₁₀ and its gate g are connected to the common erase line E. In the configuration shown in FIG. 14, bias conditions as shown in Table 4 are applied to the unit cell 50.

[Table] In Table 4, H ⁺⁺ is area 46 (Figure 15)
indicates a voltage higher than the breakdown voltage at the semiconductor surface of the junction of transistor _Q10 , ^H- indicates a negative voltage whose absolute value is greater than the breakdown voltage at the drain junction of transistor Q10, and ^H- indicates a voltage whose absolute value is greater than the breakdown voltage at the drain junction of transistor _Q10 . It exhibits a negative voltage that is less than the breakdown voltage of the drain junction. Also in Table 4, transistors Q ₁₀ and Q ₁₁
is a p channel and _Q12 is an n channel, but if the signs of these channels are reversed, the voltage V
The signs of _W , V _E and V _Y may be reversed. In this way, when writing "1", transistor Q ₁₁
conducts, through which voltage V _W on line W is applied to the drain d of transistor Q ₁₀ , causing an avalanche breakdown at its drain junction and placing transistor Q ₁₀ in the "1" charging state. In this way, "1" information is written into transistor _Q10 .
On the other hand, when writing "0", the transistor Q ₁₂ becomes conductive, and the source region 26 (15th
The application of the voltage V _E on line E to region 46 in FIG. 1 causes avalanche breakdown at the junction between regions 26 and 46, causing transistor Q ₁₀ to be in a "0" state of charge. These states of charge are maintained as they are until they are switched to other states of charge. Also, during reading, transistor Q ₁₁ is turned on, but in this case, since the voltage applied to the W line is small, transistor Q ₁₀ is turned on.
If no avalanche breakdown occurs at the drain junction of Q and as a result current flows through transistor _Q10 , then
It can read "1" and if no flow, it can read "0". In this way, even with the memory unit cell based on the second write/rewrite method, the same effects as described above regarding the first method can be obtained. Although the gate of transistor _Q12 is connected to line E in FIG. 14, it is clear that the gate may be connected to another separately provided address selection line instead. . Figure 16 is a modification of Figure 15, in which case the first
A diffusion layer 54 having a higher surface impurity concentration than the substrate 24 or the source region is provided around the source region 26 in FIG. In this way, the same effects as those of the configuration shown in FIG. 15 can be obtained, and the possibility of formation of a parasitic channel can also be effectively avoided. In this case, contact may be made from the diffusion layer 54. Another embodiment of a unit cell 50 according to the method of the invention described above with respect to FIG. 12 will now be described with reference to FIG. In this case, the unit cell 50 includes a memory transistor _Q13 and an address selection and current limiting transistor.
Q ₁₁ and Q ₁₄ . In fact, a large number of unit cells 50 can be integrated on a common semiconductor substrate 60 as shown in FIG. 18 to form an integrated circuit. Transistor Q ₁₃ has a similar configuration to field effect transistor 45 of FIG. 12, except that region 46 within source region 26 is electrically connected to substrate 60 via an extension 61 thereof. Transistor _Q11 has its source region as a transistor
It is common to the drain region 25 of _Q12 and consists of a drain region 62, a gate insulating film 63, and a gate electrode 64. Further, the transistor Q ₁₄ includes a drain region 65 formed at one edge of the source region 26 of the transistor Q ₁₃ , a source region 66 , a gate electrode 67 , and a gate insulating film 68 . The drain d of transistor _Q13 is a transistor
Source s to the common “1” write line W via Q ₁₁
is the common ground/write line E through transistor _Q14 .
The gates of transistors _Q11 and _Q14 are connected to common address selection lines Y and EY, respectively. The bias conditions shown in Table 5 are applied to the unit cell 50 having the above-described structure.

[Table] In this way, when writing "1", the transistor
Write `` <sub>1</sub> '' to transistor Q <sub>13</sub> through Q 11, and when writing ``0'' write ``0'' through transistor Q ₁₄ , and when reading
When _Q11 and _Q14 are both in a conductive state, if current flows through transistor _Q13 , "1" information can be read out, and if not, "0" information can be read out. In this case transistors Q ₁₁ and Q ₁₄ are transistors Q ₁₃
limits the current flowing to the drain junction of and the junction of region 46. As described above, according to the configurations of FIGS. 12 to 18, a memory unit cell can be obtained which can fully implement the second method described above with reference to FIG. In the configurations shown in FIGS. 12 to 18, a second gate electrode similar to, for example, the second gate electrode 23 in FIG. 2 may be provided on the insulating film 27 of the transistor 45 and _Q12 . In this case, in addition to the above-mentioned effects, the electric field generated by the gate electrode accelerates carriers generated by avalanche deposition, thereby increasing the writing speed. In the configurations shown in FIGS. 12 to 19, as shown in the figures, the region 26 is designed to have a larger area in the portion facing the first gate electrode than the region 25, and the region 4
When information is rewritten by avalanche of the junction between 6 and 26, the potential of the first gate follows the potential of region 26, so that writing can be performed efficiently. Although not specifically mentioned above, in the memory device according to the present invention, other transistors are formed on the same semiconductor substrate on which the memory field effect transistor having the first gate electrode 28 is formed. In the case where a memory unit cell is constructed using a transistor _Q13 having a buried first gate electrode 28, for example, as shown in FIG.
The thickness of the gate insulating films 63 and 68 of the other address selection transistors _Q11 and _Q14 , which do not have embedded gate electrodes, is made thicker than the thickness of the gate insulating film 22 of FIG. In this way, the breakdown voltage of the drain junctions of the other transistors _Q11 and _Q14 can be made higher than the breakdown voltage of the transistor _Q13 having the first gate, thereby making it possible to obtain a memory unit cell with stable operation. . As a result of an experiment using the field effect transistor 70 shown in FIG. 19 according to the method of the present invention, the relationship shown in FIG. 20 was obtained. In this case, the semiconductor substrate 24
is made of n-type silicon with an impurity concentration of 5×10 ¹³ /cm ³ , and the surface impurity concentration near the junction between the source region 26 and the region 46 is approximately 10 ¹⁶ /cm ³ , and the gate insulating film (SiO ₂ ) The thickness of 22 is about ₁₀₀₀ Å, and the insulation film (SiO ₂ )
The thickness l ₂ of 27 is approximately 1000 Å, and the channel length L is approximately 10 μ.
Then, the voltage of the buried gate electrode (Si) is
The time required for the voltage to change from 0V to the equivalent of -4V in the case of writing "1" and from -4V to the equivalent of 0V in the case of writing "0" is measured, and the results are sent to the second gate 23 (A ^l ) and the terminal voltage V _GS of the source region 26 (P) versus time t. In FIG. 20, the reference numeral 1 indicates the drain terminal D.
and the curve obtained when the source terminal S is grounded, a positive bias is applied to the substrate terminal B, and the reverse direction current at the junction between the source region 26 and the region 46 is 100 μA. A negative bias is applied to the drain terminal D, a slight negative bias is applied to the source terminal S, and the substrate 24 and the drain region 25 are
The curves obtained when the reverse current between the junctions was set to 10 μA are shown. From this measurement result, firstly, it is possible to write and rewrite either "1" or "0" information, and furthermore, these memories are non-volatile;
Second, by providing the second gate electrode 23, it was demonstrated that the writing time could be significantly speeded up, and third, it was demonstrated that the writing time became smaller in inverse proportion to the avalanche current of the junction causing breakdown. It was done. As described above, according to the present invention, it is possible to obtain a semiconductor memory that combines the high speed of readout that semiconductor memory inherently has and the nonvolatile memory that has conventionally been put into practical use only with magnetic memory. When manufacturing such a memory, it is possible to easily manufacture it at high density using conventional silicon gate technology or molybdenum gate technology without requiring any other special technology. In the above explanation, the stored content is digital information of "1" and "0", but it is clear that it can also be used to store non-volatile analog information. In addition, claim 1 refers to FIG.
3, 16, 18, and 19 correspond, the first semiconductor region is 24,102, the second semiconductor region is 26,105, and the third semiconductor region is 4.
6, 106, and the first gate are 28, respectively. In addition, claims 2 and 4 describe the general flow of each of the above-described embodiments and FIGS.
5 and 19, and claim 3 also applies to FIGS. 12 and 15.
16, 18, and 19, the first semiconductor region is 24, the second semiconductor region is 26, the third semiconductor region is 46, and the fourth semiconductor region is 24. is 25, the first gate is 28, and the second gate is 23. Also,
Claim 5 corresponds to FIGS. 18 and 19, Claim 6 corresponds to the description on page 17 of the specification, and Claim 7 corresponds to the statement on page 17 of the specification. 12, 13, 15, 16
18 and 19, and claim 8 corresponds to each of the aforementioned figures corresponding to claim 7 and FIGS. 2 to 5.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a field effect transistor for explaining a conventional information writing method, and FIG. 2 is a memory showing an embodiment of the present invention and for explaining an example of a nonvolatile memory storage method according to the present invention. FIGS. 3 to 5 are cross-sectional views showing structures of memory field-effect transistors according to various embodiments of the present invention, and FIGS. FIG. 5 is an equivalent circuit diagram showing an example of a memory unit cell configured including the storage field effect transistor shown in FIG. 5; FIG. 12 is a sectional view showing a storage field effect transistor according to another embodiment of the present invention; 14 is a sectional view showing the structure of a storage bipolar transistor according to another embodiment of the present invention, FIG. 14 is an equivalent circuit diagram showing an example of a memory unit cell configured including the storage field effect transistor of FIG. 12, and FIG. Figure 15 and 1st
6 is a cross-sectional view showing the structure of the memory unit cell shown in FIG. 14 formed on the same semiconductor substrate, FIG. 17 is an equivalent circuit diagram showing another example of the memory unit cell shown in FIG. 14, and FIG. A and B are the first
A plan view and a sectional view taken along the line B-B of the memory unit cell shown in FIG.
9 and 20 are diagrams showing experimental results according to an example of the method of the present invention. In the figure, 21, 45, 70... Storage field effect transistor, 22... Gate insulating film, 23... Second gate electrode, 24... Semiconductor substrate, 25... Drain region, 26... Source region, 27... Insulating film, 28 ...first gate electrode, 29,47...depletion layer, 30,3
5, 38... Channel, 31, 39, 39'... Pinch-off region, 36... Through hole, 41, 50... Memory unit cell, _Q1 to _Q14 ... Transistor.

Claims (1)

[Claims] 1. A first semiconductor region, a second semiconductor region provided in the first semiconductor region so that its surfaces coincide with each other to form a first junction, and the second semiconductor region a third region provided in the region such that its surfaces coincide with each other to form a second joint; a surface near the first joint of the first region; a surface of the second region; 1. A field effect transistor for storage, comprising: an insulating film provided across a surface near a junction of two parts; and a first gate electrode provided in the insulating film. 2. In the memory field effect transistor according to claim 1, the first
A field effect transistor for storage, characterized in that a second gate electrode is provided on the gate electrode. 3 a first semiconductor region and a second semiconductor region provided in the surface of the first semiconductor region so as to form a first junction;
a third region provided in the surface of the second semiconductor region so as to form a second junction; a surface near the first junction of the first region;
an insulating film provided across the surface of the region and the surface near the second junction of the third region; a first gate electrode provided in the insulating film; and the first gate electrode. extending over the surface of the first semiconductor region, and providing a fourth region in the surface so as to be spaced apart from the second semiconductor region and form a third junction under the first gate electrode. A memory field effect transistor characterized by: 4. In the memory field effect transistor according to claim 3, the first
A field effect transistor for storage, characterized in that a second gate electrode is provided on the gate electrode. 5. In the storage field effect transistor according to claim 3, the third region is
A field effect transistor for storage, characterized in that it is formed in a state connected to a semiconductor region. 6. In the field-effect transistor for storage according to claim 3, a fifth region having an impurity concentration higher than the impurity concentration near the junction is provided near the junction surface between the second semiconductor region and the first semiconductor region. A field effect transistor for storage, characterized in that it is provided with. 7 A drain region and a source region formed on a semiconductor substrate, a gate insulating film attached to the surface of the semiconductor substrate and an insulating film continuous thereto, and an embedded region between the gate insulating film and an insulating film continuous thereto. the semiconductor substrate under the first gate electrode;
A field effect transistor for storage, characterized in that a second junction is provided between the semiconductor substrate and the drain or source region and has a different impurity concentration relationship or material composition than the first junction. 8. A drain region and a source region formed on a semiconductor substrate, a gate insulating film attached to the surface of the semiconductor substrate and an insulating film continuous thereto, and an embedded region between the gate insulating film and an insulating film continuous thereto. a second gate electrode is provided on the first gate with an insulating film interposed therebetween; A field effect transistor for storage, characterized in that a second junction having an impurity concentration relationship or material composition different from the first junction between the substrate and the drain or source region is provided.