JPS5833715B2 - semiconductor equipment - Google Patents

Description

Detailed Description of the Invention The present invention relates to a junction field effect transistor (hereinafter referred to as J-FET).
It relates to a semiconductor device having a configuration (abbreviated as ).

As shown in FIG. 1, a vertical J-FET in which a source and a drain are arranged in the thickness direction of a semiconductor substrate and exhibits triode characteristics is known.

This vertical J-FET is, for example, an N-type high concentration semiconductor layer 1.
On top of this, a semiconductor layer 2 having the same conductivity type as this but with a sufficiently low impurity concentration and a resistivity of, for example, 50Ω is provided, and a net-shaped P-type gate region 3 is formed on this semiconductor layer 2, for example. A source region 4 having a relatively high concentration of N type is formed by selective diffusion and has a relatively high concentration of N-type at a position opposite to the network of the gate region 3 forming a net shape, and this region 4 and the region 3 are electrically insulated. A thick 5in2 film 5 is preferably deposited on the gate region 3.

6s is a source electrode, 6g is a gate electrode, and S, G, and D are source, gate, and drain electrode terminals.

Drain-source current ID5 with respect to drain-source voltage VDS of the vertical J-FET with such a configuration
(7J gate voltage ■IDS V with G as a parameter
The DS characteristics are as shown in FIG. 2, exhibiting triode characteristics.

In the present invention, for example, although the vertical J-FET structure is used, the gate voltage (2) is particularly high.

The purpose of the present invention is to provide a semiconductor device whose resistance value changes with respect to a change in IDS VDS at each gate voltage.
The purpose is to provide a novel semiconductor device exhibiting these characteristics.

An example of a semiconductor device according to the present invention will be described in detail with reference to FIG.

In the present invention, a drain region 11 having a high concentration of, for example, N-type is provided, and a drain region 11 having the same conductivity type as the drain region 11 but having a sufficiently low impurity concentration, for example, 40 to 60 Ω. A low concentration region 12 with a thickness of about 100 μm is provided, and on top of this, regions 11 and 12 are formed with a high concentration, for example, a specific resistance of 2.2Ω, compared to the region 12 having the same conductivity type.
・A high concentration region 13 of α is formed to have a thickness of about 4 μm, a gate region 14 having a net shape is formed in this region 13, and a gate region 14 having the same conductivity type as this region 13 is formed on the region 13 facing within the mesh. A source region 15 having a sufficiently high concentration is provided, and a thick insulating layer 16 made of, for example, SiO2 is provided on the gate region 14 to electrically isolate the source region 15 and the gate region 14.

A common saw-in electrode 17s is ohmically deposited on each source region 15.

Further, an electrode lead-out portion having a relatively wide area is provided at the periphery of the gate region 14, and the gate electrode 17g is ohmically attached thereto.

Thus, a channel portion 18 sandwiched between the source region 15 and the drain region 11 by the gate region 14 is formed in sections.

In this case, the shape of the portion of the gate region 14 facing the channel portion 18 is such that the cross-sectional shape along the arrangement direction of the source region 15 and the drain region 11 is a curved surface that is convex toward the channel portion 18 side, for example, a circular cross-section.

Furthermore, the gate region 14 of the low concentration region 12 and the high concentration region 13
As shown in FIG. 4, when the drain-source voltage VDS is at or near zero, the arrangement for
By deepening the gate voltage in the negative direction with respect to the source, the gate junction J
When the channel 18 is pinched off by the depletion layer from
In the voltage range of , the end a on the drain side of the pinched-off portion of the depletion layer exists in the region 13.

In a high voltage range in the operating range of the drain-source voltage VDS, a similar pinch-off of the depletion layer straddles the low concentration region 12 as shown by the dashed line in the same figure, that is, the drain of the pinch-off portion The side end b1 is located in the low concentration region 12.

When such a configuration is adopted, the characteristics of the VDS ID5W property with respect to the gate voltage ■G are as shown in FIG.
As a variable resistance element, its characteristics at each gate voltage (G) showed linearity, and its conversion rate was also found to be excellent.

Next, in order to facilitate understanding of the semiconductor device according to the present invention, an example of its manufacturing method will be further explained with reference to FIG.

First, as shown in FIG. 6A, a semiconductor such as Si substrate constituting the N-type drain region 11 is provided, and a semiconductor such as Si layer constituting the low concentration region 12 is epitaxially grown on this substrate. A semiconductor such as a Si layer constituting a similar N-type high concentration region 13 is epitaxially grown thereon.

Then, a mask layer 20 made of, for example, SiO2 is formed on this semiconductor layer 13, and a mask layer 19 made of, for example, Si3N4, which can serve as an oxidation mask, is formed thereon.

Further, a mask layer 21 such as 8102 which can serve as a selective etching layer for this mask layer 19 is formed on the entire surface, and a window 22 is formed in accordance with the pattern of the gate region.

This window 22 is formed by photo-etching the mask layer 21 to form a window in a desired pattern. Then, using this mask layer 21 as an etching mask, the mask layer 19 made of Si3N4 is etched, and then the mask layer 19 below this is etched.
0 is removed by etching.

Next, as shown in FIG. 6B, these mask layers 19 to
Using 21 as a mask, P type impurities are selectively diffused into the region 13 at a relatively high concentration to form the gate region 14.

Thereafter, as shown in FIG. 6C, the mask layer 20 made of 5i02 below the mask layer 19 is over-etched to further widen the periphery of the window 22, and a wider window 23 is formed below the periphery of the window 22. 5i02 is formed on the gate region 14 with a width slightly larger than that by thermal oxidation treatment.
A thick insulating layer 16 is formed.

After that, as shown in the sixth diagram, the mask layers 19, 20, etc. are removed by etching, and the area 1 where the insulating layer 16 is not formed is removed.
A source region 15 is formed on the source region 15 by diffusing an N type impurity having the same conductivity type as the source region 3 at a high concentration.

Further, if a common source electrode 173 is formed on the region 15, a window is opened in a part of the insulating layer 16 on the region 14 by photoetching, and a gate electrode 17g is formed there, the result shown in FIG. A semiconductor device according to the present invention is constructed.

The reason why the device of the present invention having such a configuration exhibits characteristics as a variable resistance element is considered to be caused by the following phenomenon.

First, the source-drain voltage VDS and ■.

In a range in which both are small, the spread of the depletion layer does not lead to pinch-off of the channel portion 18, and the resistance value is determined depending on the impurity concentration between the source and drain with good linearity and exhibiting a required low resistance value.

Further, in this region, the voltage amplification rate μ is small.

Then, with the drain-source voltage VDS kept small in this way, the gate voltage V.

When increasing in the negative direction with respect to the source, the channel portion 18 is pinched off, but at this time, this pinching is done in the region 13 as explained in FIG. 4, so this portion The degree of spread of the depletion layer between the source and drain is small even if the gate voltage is controlled, so it is difficult to pinch-off between the source and drain5, and even if pinch-off occurs, the depletion layer between the source and drain ■ The thickness of each gate voltage is thin and therefore does not exhibit saturation characteristics.

The resistance value between the source and drain changes depending on the voltage, and the resistance value, that is, the IDS/Ds characteristic has good linearity.

In addition, in the range where the source-drain voltage VDS is dog, the depletion layer from the junction J is pinched off in the low concentration region 12 as shown by the chain line in FIG. The spread of the layer becomes a dog■.

The resistance value changes greatly in response to a change in , the voltage amplification factor μ suddenly becomes dog, and on the other hand, the electric field potential inside the channel due to the increase in drain voltage increases due to the rapid increase in the thickness of the depletion layer between the source and drain. Even if the influence on the current suddenly decreases and ■Ds increases, the current will suddenly flow between the source and drain, and it will not exhibit triode characteristics and will maintain a high resistance value. It is believed that there is.

As described above, the semiconductor device according to the present invention is a vertical J-
It can be easily manufactured using a manufacturing method similar to that used to form FETs, and it is also possible to obtain a resistance value change with excellent linearity and a high rate of change. .

In the above example, the present invention is of an N-channel configuration, but it can also be a P-channel configuration. In the figure, the conductivity type attached to each part may be selected to be the opposite conductivity type.

In the above-described example, the semiconductor region 13 is formed by eviaxial growth, but it is obvious that various modifications can be made, such as forming it by ion implantation in some cases.

[Brief explanation of the drawing]

FIG. 1 is an enlarged sectional view of a conventional vertical field effect transistor, FIG. 2 is a characteristic curve diagram thereof, FIG. 3 is an enlarged sectional view of an example of a semiconductor device according to the present invention, and FIG. 4 is an explanatory diagram thereof. , FIG. 5 is a characteristic curve diagram thereof, and FIG. 6 is a process chart showing an example of its manufacturing method. 11 is a drain region, 15 is a source region, 14 is a gate region, 18 is a channel portion, 12 is a low concentration region, 13 is a high concentration region, 16 is an insulating layer, 17s and 17g are a source electrode and a gate electrode, S, D , G are source, drain, and gate terminals.

Claims (1)

[Claims] 1. A source region of a first conductivity type provided facing the first main surface of the semiconductor substrate, a drain region of the second conductivity type provided facing the second main surface of the semiconductor substrate, the source region and a gate region of a second conductivity type that separately forms a plurality of first regions of a first conductivity type that serve as channel portions between the drain regions; and a gate region of a first conductivity type disposed in contact with the drain region side of the first region. The impurity concentration of the first region is selected to be lower than that of the source region and higher than that of the second region. A depletion layer responsive to the region covers the first region to close the channel, and in a high voltage range, the depletion layer extends to the second region to close the channel, so that the source-drain voltage-current characteristic is linear. A semiconductor device characterized in that it exhibits.