JPS5834852B2 - Enzanshiyorihoushiki - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an arithmetic processing method in a so-called exponent display type computer that expresses numerical data using an exponent part and a mantissa part and performs arithmetic processing.

In general, reconnaissance accuracy in a computer is determined by relative accuracy, and in function calculations, calculations are performed using approximation formulas appropriate for calculating the function. Since the calculations are repeated many times, the accuracy of the solution is greatly influenced by whether or not the number of significant digits in the result of each calculation process is one digit higher.

Also, functional calculations, such as logarithm calculation trigonometric functions 1. When performing inverse trigonometric functions, hyperbolic functions, exponential calculations, etc., the calculation (1-X) (where O≦X×1) appears relatively frequently in the calculation process.

On the other hand, in an exponential display type calculator, for example, a computer that stores a numerical value (0,0009956) as data in the form of [9,9560000 (mantissa part) XIO' (exponent part)] and processes this (1
-X) ((0≦x<11)) If the operation is performed using the subtraction flow normally used in computers, the subtraction is performed after digit alignment of the operand and the operand, so it is unavoidable. The number of significant digits of the operation result is reduced by the number of digits by which the contents of the register were shifted to the right in the digit matching step.

For example, if a computer has an 8-digit display, the arithmetic register has a mantissa part 1 that stores the significant figure part of the input data, and a decimal place G of the input data, as shown in FIG. 1a. It consists of an exponent part 2 that stores exponent data indicating the scale for the exponent, and an exponent sign part 3 that stores sign information for determining whether the exponent is positive or negative.

For example, if the stored content of the index sign section 3 is (0) (binary information), it represents "+", and if it is [1], it represents "-".

In addition, the mantissa part 1 has a storage capacity for 9 digits, and the mantissa data is stored for the lower 8 digits, and the MSD of the most significant digit, that is, the 9th digit, is carried during the operation, that is, from the operation of the 8th digit. This is provided as a backup in case of a borrow or carry.

Therefore, 1-X((MX<1), ('x=0.
99912345) ), the operand (1,00
00000) is stored in the form of (1,0000000X10°), and the value of the operator X, for example (0,99912345), is stored in the second register 4b as [: 9.999123
It is stored in the register 4b in the form of 45x10-ri.

In other words, taking register 4b as an example, the mantissa part 1 has (99
912345), the index part 2 indicates the index (IOJ [01
], and [1] indicating that the exponent is "-" is stored in the exponent sign section 3.

After the recording, the first and second registers 4 a
In order to align the decimal point positions of the numerical data stored in y 4 b, the content of the exponent part of the second register 4b is changed from [01] to (0, 0) as shown in FIG. 1C, and the data of the mantissa part is Shift right to 1 and lower it by 1 digit (09991234) to 1
.about., i-x, that is, (1-0,9991234) is calculated, and the result (0,0008766) is obtained as shown in FIG. 1d.

Then, as shown in Figure 1e, (8,766X], 0 4
) into exponential form.

Then, based on this operation of (], -X), for example, logarithm calculation Functional calculations such as the following are performed.

In this way, in the conventional exponential calculator (1 - As the digits are lowered, the lower digits are sequentially truncated due to the shift operation, and the number of effective precision digits for the true value of the subtraction result is reduced. It has a disadvantage that when it is used many times to perform various calculations and obtain the calculation results, the accuracy of the calculation results decreases significantly.

The present invention has been made in view of the above points, and when performing the calculation of 1-X, even if X is smaller than [1], high accuracy can be obtained without causing loss of significant numbers. An object of the present invention is to provide an arithmetic processing method that improves the accuracy of arithmetic results in functional calculations.

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 2, 10 is a shift register, and as explained in FIG. 1a, the mantissa part 11. Exponent part 12, exponent sign part 1
The output signal is applied to one input terminal of an AND circuit 15 via a 4-bit delay circuit 14, and the output of this AND circuit 15 is sent via an OR circuit 16 to shift 1 to registers. It is reduced to 10.

In addition, the output signals of shift 1 to register 10 are the mantissa part timing + failure signal T1 that specifies the mantissa part 11 which becomes the "1" signal only during the period when the content of the mantissa part 11 of the shift register 10 is output from the shift register 10. AND circuit 1
7, and the output signal of the AND circuit 17 is applied as the signal X to be operated on to the X input terminal of the adder circuit 18.

Furthermore, the output signal of the shift register 10 is an exponent sign section timing designation signal that specifies the exponent sign section 12, that is, a signal in which the contents of the exponent sign section of the shift register 10 become P1''' only during the period from shift 1 to output from the register 10. T
3 and a 1-X command to execute the (X-1) operation issued by a control section (not shown) to the AND circuit 19.

The output signal of the AND circuit 19 from L to L is sent to the judgment circuit 20.
sent to.

This judgment circuit 20 determines whether the content of the exponent sign section 13 is [1] or [O] when the 1-X instruction is captured, that is, the operand placed in the shift register 10 is smaller than [1]. If it is determined that it is smaller than [1], then
Outputs a 1″ signal.

The output signal of this judgment circuit 20 is applied as a subtraction signal to the adder circuit 18, and at the same time, a timing signal that specifies the most significant digit MSD of the mantissa part of the shift register 10, that is, the contents of the most significant digit MSD of the mantissa part is output from the shift register 10. It is applied to the AND circuit 21 together with the signal TM which is l'' only at the timing.

The output of the AND circuit 21 is added to the adder circuit 18 as an operand [1].

The adder circuit 18 performs a calculation of 1-X when applied to each input terminal, and adds the result of the operation to one input terminal of an AND circuit 23 via an OR circuit 22.

The output signal of the AND circuit 23 is sent to the register 10 to shift 1 via the OR circuit 16.

Further, the output signal of the judgment circuit 20 is sent to the decimal point code generation circuit 24 as an operation command.

This decimal point code generation circuit 24 is
” signal is given by giving the decimal point code e.g. (
101) and supplies it to one input terminal of the AND circuit 25.

A timing signal T2 that specifies the exponent part 12 and exponent sign part 13 of the shift register 10 is given to the other input terminal of the AND circuit 25, and a decimal point code is sent from the AND circuit 25 in synchronization with this timing signal T2. is output and added to the OR circuit 22.

Further, the output signal of the AND circuit 19 is sent to a delayed flip-flop circuit 27 via an inverter 26.

This delayed flip-flop circuit 27 reads an input in synchronization with the word clock pulse e, and outputs a signal in synchronization with the clock pulse φ2.

The clock pulse φe is output in synchronization with one word time, that is, every time the contents of the shift register 10 complete one cycle.

Further, the clock pulse φ2 has a sufficiently short period compared to φe.

Therefore, the output signal of the flip-flop 27 is 4
The signal is applied to the other input terminal of the AND circuit 15 via the bit delay circuit 28, and is further applied to the other input terminal of the AND circuit 23 via the inverter 29.

Next, the operation of the present invention configured as described above will be explained.

Now, for example, in the calculation process, the value of the calculation number X, for example (0,99912345) is (9,99912345X
10') into the shift register 10 via an input circuit (not shown), the shift register 1
0 has (99912
345), [01] is stored in the exponent part 12, and [1] is stored in the exponent sign part 13.

On the other hand, since the output of the AND circuit 19 is initially "0" and the output of the inverter 26 is 1"', the flip-flop circuit 27 (this 1"1" signal is read).

The output of this flip-flop circuit 27 is applied to the AND circuit 15 via a 4-bit delay circuit 28, and its gate is opened.

Therefore, the information placed in the shift register 10 is
4-bit delay circuit 14, AND circuit 15, OR circuit 1
6 and is held in a circular manner in the shift register 10.

When performing a 1-X operation, a 1-X instruction is given to the AND circuit 19.

When this 1-X command is given, the gate of the AND circuit 19 is opened by the exponent sign part timing signal T3,
The contents of the exponent sign section 13 read from the shift register 10 are output from the AND circuit 19.

The contents of the exponent sign section 13 outputted from the AND circuit 19 are sent to the judgment circuit 20, which judges whether the arithmetic number X is smaller than [1].
If the content of is [1], it is determined that the content of the arithmetic number
1).

The AND circuit 21 also has an MSD timing designation signal T.
Since M is given, the AND circuit 21 outputs a [1] signal in synchronization with the MSD timing designation signal TM.

The output of this AND circuit 21 is sent to the adder circuit 18 as an operand [1].

Furthermore, the contents of the mantissa part 11 read from the shift register 10 (99,912,345
) is given via the AND circuit 17.

Therefore, the adder circuit 18 is connected to Doo as shown in FIG.
oooooo.

-99912345=00087655).

In other words, the contents of the operand X are left as they are without being downgraded, and the operation 1-X is executed as if the operand [1] were incremented by one digit to the MSD digit.

On the other hand, when the content [1] of the exponent sign section 13 is output from the AND circuit 19, the output of the inverter 26 becomes 0'', and an O'' signal is read into the flip-flop circuit 27 in synchronization with the word clock pulse φe.

The "O" signal read into the flip-flop circuit 27 is then outputted in synchronization with the clock pulse φ2 that arrives with a delay of half a bit, and the gate of the AND circuit 15 is closed in the delay circuit 28 with a delay of 4 bits, that is, one digit. , the circulation operation of the shift register 10 is prohibited.

Also, at this time, the gate of the AND circuit 23 is opened at the timing when the output of the inverter 29 is 1'', that is, the LSD of the shift register 10 is output from the adder circuit 18, so the calculation result of the adder circuit 18 is transferred to the OR circuit 22. , the shift register 1 via the AND circuit 23 and the OR circuit 16.
It is input to 0.

Since the input information to the shift register 10 is delayed by 4 bits in the adder circuit 18, it is placed in the mantissa part 11 of the shift register 10 at the same timing as when the shift register 10 is in circular operation.

Further, the decimal point code generation circuit 24 operates when the determination circuit 20 outputs the "1" signal, and the decimal point code (
101) is generated.

This decimal point code (101) is the exponent timing T2V
c is synchronously outputted from the AND circuit 25, further inputted to the shift register 10 via the OR circuit 22, AND circuit 23, and OR circuit 16, and the exponent part 12 and the sign part 13
The number is placed in .

As a result, as shown in FIG. 3C, the operation result of the adder circuit 18 (0008765
5), [01] in the exponent part 12, [1] in the exponent sign part 13
] are set respectively.

On the other hand, after reading the "°0" signal, the flip-flop circuit 27 maintains its state for one word time until the next word clock pulse φe is applied, and closes the gate of the AND circuit 15. However, at the time when the next word clock pulse φe is applied, there is no 1-X instruction, so the output of the AND circuit 19 becomes °゛0″0″ Impark 26 becomes Q111, so the next word clock pulse Read the ``1'' signal in synchronization with the pulse φe,
Because the clock pulse φ2 arrives with a delay of half a bit,
″Outputs a signal.

When the flip-flop circuit 27 outputs the ``1'' signal, the gate of the AND circuit 23 is closed and the gate of the AND circuit 15 is opened.

Therefore, the information placed in the shift register 10 is circulated and held again via the delay circuit 14, AND circuit 15, and OR circuit 16.

The contents of the mantissa part 11 of the shift register 10 are carried up until the effective value reaches the most significant digit of the display, as shown in FIG. Increase the memory content of.

In the example shown in FIG. 3, the contents of the mantissa part 11 are carried up by three digits, and the contents of the exponent part 12 are set to [04].

These controls are performed by a computing unit leg (not shown).

By the above calculation operation, (8,7655X1.0'
), which is (1-X) or (1-
0,99912345).

Furthermore, when performing the calculations of ] and -[, if the value of the calculation number X is [1] or more, the calculation operation is performed according to the general calculation flow according to the judgment result of the judgment circuit 20.

FIG. 4 shows another embodiment of the present invention, in which the AND circuit 21 in FIG. 2 is omitted and the adder circuit 18 is omitted.
An AND circuit 31 is provided between the AND circuit 22 and an MSD timing signal is applied to the AND circuit 31 via an inverter 32 to perform gate control and cut the borrow signal output from the adder circuit 18. It is something.

That is, in the embodiment shown in FIG. 2, the operand [1] is given to the adder circuit 18 at the timing of specifying the MSD when calculating -X.
In the embodiment shown in FIG. 4, the AND circuit 21 is omitted and (0
-X) is performed, and the borrow signal generated by this calculation is cut by the MSD timing signal TM, and the same result as the embodiment shown in FIG. 2 can be obtained.

Further, in FIG. 4, the AND circuit 31 is provided to perform the borrow cut, but if the adder circuit 18 itself has a borrow cut function, the AND circuit 31 may not be provided.

Furthermore, in the embodiments shown in FIGS. 2 and 4, the case where the decimal point code generation circuit 24 is provided is shown.
When calculating X, the exponent part 12 and the exponent sign part 13
The decimal point code generation circuit 24 can be omitted by returning the contents to the input side of the shift register 10 and storing them in circulation.

Further, in each of the above embodiments, the 4-bit delay circuit 14,
28 is provided, but when the calculation result of the adder circuit 18 is input to the shift register 10, if the timing is adjusted by removing 4 bits of the shift clock pulse of the shift register 10, the delay circuit 14
, 28 may not be provided, and various applications are possible without departing from the gist of the present invention.

As described above, according to the present invention, when performing the calculation of 1-X, even if X is smaller than []], the calculation precision can be improved without causing a loss of digits.

Furthermore, since there is no need for a step to lower the number of digits during calculation, the number of calculation steps is reduced, and the calculation speed can be improved.

Furthermore, it is extremely advantageous because the calculation can be performed without requiring a register for storing operands.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the contents of an arithmetic register to explain a conventional arithmetic processing method, Fig. 2 is a block diagram showing an embodiment of the present invention, and Fig. 3 is a diagram to explain the operation of the embodiment. FIG. 4 is a block diagram showing another embodiment of the present invention. 10...Shift register, 14,28...
...4-bit delay circuit, 18...adder circuit,
20... Judgment circuit, 24... Decimal point code generation circuit.

Claims (1)

[Claims] 1 A storage means in which an arithmetic number X is stored, and an arithmetic number
a determination circuit for determining whether the operation number X is smaller than 1; a means for adjusting the decimal point position of the operation number An arithmetic processing method comprising: means for performing an arithmetic operation on 1-X after the decimal point adjustment of the arithmetic number is completed by the means.