JPS5835407B2 - Channel selection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a channel selection device that uses a volatile memory as a storage element for channel selection signals, and is a channel selection device that does not require a battery to keep the volatile memory always in operation. The aim is to provide station equipment.

In a tuning device that stores the tuning voltage of an electronic tuner in the form of a binary signal in a digital memory and reads it out, if a non-volatile EPROM is used as the digital memory, it will be possible to receive each station sequentially when used at home. It is necessary to perform an operation to memorize the voltage, and EPROM is also expensive and has reliability problems, so it is currently not widely used.

Also, in the case of EPROM, write. Even in MNOS, the erasing time is long at 100 m SeC each, and the time required for rewriting is also considerably long.

On the other hand, volatile memory has a writing and erasing time of ioo~500ns.
It is preferable to EPROM because it is sufficiently short as ec, but it has the disadvantage that it requires a constant supply of power, so a battery must be built into the receiver.

Therefore, the present invention aims to shorten the write time using volatile memory and eliminate the need for batteries by writing data every time the power is turned on. A DC voltage corresponding to the channel is supplied, and the DC voltage corresponding to each receiving channel is stored in a volatile memory in the form of a binary signal, and the stored contents are read out in response to a channel selection command signal to generate the channel selection voltage. An automatic writing circuit is provided that operates each time the power switch is turned on, and the operation of this automatic writing circuit causes the tuning voltage generation circuit to be automatically swept when the power is turned on. The present invention is characterized in that a binary signal corresponding to each reception channel is written into the volatile memory.

When performing the automatic sweep, the tuner's AG
The time constant of at least one of the C circuit and the local AFC circuit is shortened to increase the sweep speed.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

1 is an electronic channel in which a DC voltage is applied to a variable capacitance diode as a tuning element to control the tuning frequency; 2 is a video intermediate frequency amplification circuit; 3 is a video detection circuit; 4 is a synchronous separation circuit; 5 is a deflection output The circuit 6 is a tuning voltage generating circuit for the tuner 1, and 7 is a volatile memory circuit for storing the tuning voltage as a 13-bit signal, which includes a volatile memory, an encoder, a selector, and a counter.

The volatile memory here is CMO8 static RAM.
think of.

8 is a channel selection button, and it is assumed that there are 12 buttons.

Reference numeral 9 denotes an automatic write circuit of the present invention, which writes data of all receivable channels to the volatile memory circuit 7 only once when the power switch 14 is turned on, that is, when a voltage appears at the output of the main power supply circuit 13. This is the circuit for writing.

Reference numeral 10 denotes a tuning detection circuit, which generates an output pulse when an audio carrier is detected by the audio carrier detection circuit 17 and a video carrier is detected by the video carrier generation circuit 18, and drives the automatic writing circuit 9 to perform writing. Let's do it.

After writing is completed, the channel selection voltage is swept until the next channel is received.

11 is AGC and tuner local AFC and VIF,
This is an RF AGC time constant switching circuit.

Reference numeral 12 denotes a manual write switch, and when this switch 12 is closed, the writing state can be set.

13 is a main power supply circuit that outputs various DC voltages and supplies them to various parts.

Reference numeral 14 denotes a power switch, which is usually provided on the front of the television set.

15 is a plug connected to a 100 volt AC; 16 is a video output circuit; the output of this circuit is supplied to a color cathode ray tube 19 to obtain a color image.

1 to 19, except 9 to 12 and '17 and 18 are the same as a normal color television with an electronic tuner.

Next, the automatic writing operation will be explained with reference to FIG.

First, when the power switch 14 is turned on, DC voltage is supplied to the volatile memory circuit 7, and the volatile memory circuit 7 is brought into a memorizable state.

At the same time, a pulse appears at the output of the ON detection circuit 21D of the automatic write circuit 8, and the monostable multi-by-break 21M
trigger.

The output of this monostable multi-bi break 21M is 100
ns to 1 μsec is sufficient.

There is a delay of ΔT from when the power switch 14 is turned on until the monostable multi-by-break 21M generates an output.

The output of the monostable multi-bi break 21M is inverted by the NOR gate 22, the flip-flop 23 is set,
The Q of this flip-flop 23 becomes a high level, and the Q of this flip-flop 23 becomes a low level.

On the other hand, when there is no output in the audio carrier detection circuit 17 and the video carrier detection circuit 18, the outputs of the level conversion circuits 30 and 31 of the tuning detection circuit 10 are at a low level, and the NA
The output of ND gate 132 is at high level.

Therefore, the output of the monostable multi-by-break 33M is also at a high level.

Therefore, when the tuning is out of tune, the output of the tuning detection circuit 10 is at a high level.

At this time, the NAND gate 24 becomes conductive.

Since a positive horizontal pulse is applied to this NAND gate 24, if the power switch 14 is turned on at time To, To+ΔT=T.

From then on, the H pulse is passed, and the 13-bit binary counter 25 starts counting the H pulse.

As 25, for example, 4 integrated circuit elements 5N74LS93 are used.
It is sufficient to connect the two in series and supply the output 213 to the clear terminal of the pinary count circuit 5 and the NA and ND gates 28.

Now, since H pulses exist approximately every 63.5 μsec, the time required for the binary counter 25 to count 213 H pulses is 63.5 x 10-6 x 1024 x 8 = 0.3
It will be 2 seconds.

With an ordinary TV's electronic tuner, you can switch the band to the VHF low band.

Since it is divided into high band and UHF band, theoretically it is possible to write all channels in 0.52 x 11.6 seconds.

Now, with the output of the NOR gate 22, the flip-flop 34
, 35 are cleared, the output of the AND gate 36 becomes high level (the outputs of AND gates 37 and 38 are low level), and the Q output of the flip-flop 23 causes the selector 39 to Instead of the output of the tuner 8, the outputs of the AND gates 36 to 38 are supplied to the tuner.

Therefore, after time T1-T+ΔT, first, three channels of the VHF low band are swept.

The output of the binary counter 25 is output from the AND gate 26A~
The signal is supplied to the volatile memory 7a and the digital-to-analog converter 29 through 13 gates of 26M.

Volatile memory 7a is a CMOS memory having 16-bit parallel input/output terminals.

Since the number of input pulses is expressed in binary in the 13-bit output of the binary counter 25, 29 is a digital-to-analog converter that generates a DC voltage proportional to the total number of pulses.

When the number of pulses O is OV and 213 pulses are 32V, there are 1 to 3 channels between them.

For convenience, if we assume that the capacitance of the variable capacitance diode of tuner 1 changes linearly with respect to DC reverse bias, then 20
Three channels, 1, 2.3, are received every 48H.

Channels 1 and 3 are received in the Tokyo area.

1 channel is received 2048H, that is, 0.13 seconds after time T1 (referred to as T2), and the NA of the tuning detection circuit 10 is
The output of the ND circuit 32 becomes low level and drives the monostable multivibrator 33M.

The pulse width of this multi-by-break 33M is approximately 2μse.
c, the NAND gate 24 is cut off during this period.

At the same time, the output of the negative logic AND gate 33G causes the W/R terminal of the volatile memo 'J7a to become low level.
The output of the binary counter 25 at that time is written in 13 bits to the volatile memory 7a.

The write address of the volatile memory 7a is written to the counter 27c.
The output of the monostable multi-by-break 33M is the first number, which is the same address as in the case of the first position of the channel selection box 8.

Next, when the output of the monostable multi-by break 33M returns to high level, the counter 25 starts counting again and T
After 2048H from 2, the channel becomes 2, but since the output of the NAND gate 432 of the tuning detection circuit 10 does not change, after another 2048H, it is tuned to the 3rd channel, and the output of the monostable multi-bi break 33M becomes low level for about 2μsec again. Volatile memory 7 to binary counter 25
The output of is written.

Since the output of the monostable multi-by-break 33M is the second, the write address becomes the same address as in the case of the second position of the channel selection button 8.

Note that the selector 27S is controlled by the Q of the flip-flop 23 and supplies an address obtained by counting the output of the monostable multi-by-break 33M to the volatile memory 7a.

The time to finish writing for 3 channels is 2048H+2
μsec+ 4096H+2 μSec'-=; 0.
39 seconds, and after 2048H, the binary counter 2
The 213 output of No. 5 becomes high level, clears the volatile memory 25 (time T4), and sets the flip-flop 34.

Therefore, the Q of the flip-flop 34 becomes high level,
Q becomes low level, and the output of AND gate 37 becomes high level.

Flip-flop 34 is connected to the J terminal of flip-flop 35.
Since the Q output of is added, the flip-flop 35 is not set at this time, but is set by the next set signal.

Therefore, the band switching of the tuner 1 becomes the VHF high band.

Since the VHF high band has 9 channels from 4 to 12, one channel is received approximately every 820 hours.

That is, at T5, 820H after T4, it is tuned to channel 4, and the output of the flip-flop 33M becomes low level.
As before, the output of the binary counter 25 is written to the address corresponding to the third position of the channel selection button 8.

In Tokyo, VHF high band has 5 channels of 4, 6 degrees, 8, 10, and 12, so the writing time increases by 10 μsec, resulting in 8192H+1. Oμ5ec0.52 seconds (Tlo
), the writing ends.

The same goes for the next UHF band, 81.9 from TIO.
Writing ends after 2H+2N μsec (N is the number of selectable stations).

Even if there are 4 stations in the UHF band, the time is 0952 seconds.

Therefore, in total, writing is completed in 0.52+2Nμ5eC (n is the number of receivable stations).

The time required to write both VHF and UHF is y819
2X3X63.5#1.56 seconds.

When writing is completed, the output of the AND gate 38 is at a high level, the output 213 of the binary counter 25 is at a high level, and after sweeping to the highest UHF channel "62", this output appears, and the output from the NAND gate 28 is at a high level. The output of becomes low level and clears the flip-flop 23.

Therefore, NAND gate 24 is blocked and 26A-26
M is also blocked.

26A to 26M are the so-called Tri-State (Try-
state) (a gate that takes three states of 0, 1, and high impedance), the output terminal becomes high impedance.

The Q of the flip-flop 23 becomes high level, and both the selector 39 and the selector 27S enter the read state.

Note that the channel selection button 8 generally has 12 positions, and as mentioned above, VHF low band is written as 2 channels, VHF high band as 5 channels, and UHF band as 4 channels, up to the 11th position, and the remaining 1 There is a surplus of channels, but there is no need to use them.

This concludes the explanation of the main parts of the embodiment of the present invention, but some supplements will be added about each part.

An example of 26A to 26M is an integrated circuit element 5N7412.
6 or DM8094.

An example of the selector 39 is the integrated circuit SNγ4. LS15
There are 7.

Integrated circuit 5 as an example of monostable multibibreak 33M
There is 1/2 of N74LS123 or SN74121.

27C is a write address counter that counts the leading edge of a negative write pulse when it appears at the monostable multi-by-break 33M output.

Therefore, as mentioned above, one channel of VHF has address 0.
001, and the third channel is 0010, VHF
The 12th channel is 0111.

On the other hand, since the Q of the flip-flop 23 at the Se terminal of 27S is at a low level, the output of 27S becomes the A input, that is, the output of 27C.

Therefore, a 13-bit binary signal corresponding to one channel is written to address 0001 of volatile memo 'J7a.

On the other hand, 40L, 40H, and 40U in FIG. 2 are the same AND gates as 26A to 26M, as shown in FIG.

The channel selection voltage is written in l101-13 of the volatile memory 7a, 1 is written in 14-16 corresponding to ■ paste, H, and U, and AN is read out when it is VHF1 channel in Ilo.
Since the output of the D gate 36 is at a high level, 1 is written to l1014.

That is, when the write address is 0001 and ooio, l1
1 is supplied to 014 and written.

For channels 4 to 12 of VHF, 1 is supplied to l1015 and written.

In the case of U, 1 is supplied to l1016 and written.

Next, when the writing of U is completed and a positive pulse is generated in the output of the pinary counter 25, the flip-flop 23 is cleared, and the terminal Se of the selector 27S becomes high level, and the output of the selector 27S becomes the output of the encoder 27E, that is, the channel selection box. This is the channel position specified by 8.

The encoder 27E is an encoder that converts decimal numbers 1 to 12 into binary 4 bits.

Since Q of flip-flop 23 is high level, gate 23G
The output becomes high level, and the volatile memory 7a enters the read state.

The output of the selector 39 also becomes the B input.

If you press the third button on the channel selection button 8, the encoder 27E
The output of is 0011, and the output of volatile memory 7 is ■10
Binary signals corresponding to the V I-I P 4 channels appear at 1 to 13, and only 15 of 11014 to 16 becomes 1, instructing the tuner 1 to use the VHF high band.

Note that the outputs of the gates 26A to 26M and 40L to 40U have high impedance.

The device/analog converter 29 is supplied with the outputs of l101 to 13 of the volatile memo 'J7a, and control voltages corresponding to 4 channels are obtained as outputs of the device/analog converter 29 and supplied to the tuner, which converts the 4 channels. Receive.

An example of the digital-to-analog converter 29 is shown in FIG.

In Figure 3, 29C is a 13-bit high-speed comparison circuit, 29
A is a 13-bit high-speed synchronous counter, 29F is a high-speed flip-flop, and 29G is a gated oscillator of approximately 150 MHz.

29I is an integrating circuit that generates a DC voltage proportional to the input pulse width.

In FIG. 4, φ1 is a horizontal synchronizing signal, and t1 to t2 are approximately 635 μSec.

The pulse width of the gated oscillator 29G output is approximately
The bulk is 6.7nSeC.

Therefore, even if you count 213 = 8192 outputs of the 1.5X10”-8 oscillator 29G, it will be approximately 5
The time is 4.6 μsec, which falls within the IH interval.

In FIG. 4, tl is the first horizontal synchronizing signal after tl, and the beginning of φ2 is a pulse with a width of 6.7 nSeC from tl.

That is, at t, the flip-flop 29F is set and the output of the oscillator 29G is generated.

At this time, the output of the counter 25 in FIG. 2 is 000000000.
0001, and when the output of the first 29G is counted by 29A, 29C detects the coincidence of both forces and resets 29F.

Therefore, oscillator 29G stops oscillating.

Therefore, the width of the Q output of the flip-flop 29F is the width of the oscillator 29
One pulse of G is approximately 6.7 n5ec.

In the next IH, the width of φ2 becomes 6.7X 2 ns, which widens by one pulse every H1.

In the case of VHF low band, at the 2048th H, the pulse width is 6.6 x 2048#13.65 μsec, which is 3
An output of 2/4=8V is obtained as the output of the integrating circuit 29I.

The same applies below. Here, the pulse width was changed by H1 bit every H1 bit, but by applying fH/, which is the frequency of the horizontal synchronizing signal divided by 1/10, to the NAND gate 24 and flip-flop 29F, the frequency of the oscillator 29G was changed to 4 fsc = 14.318
It may also be 18 MHz (or around 18 MHz), in which case the aforementioned write time will be approximately 15.6 seconds.

In this case, the digital-to-analog converter 29 is a common low-voltage Schottky type (Low Power 5C).
Hottky type) TTL can be used.

Next, considering the case of readout display, if the data read from the volatile memory a is 1000000000000, that is, 4096, the comparator circuit 29C outputs a coincidence output at the 4096th oscillator 29G, and the flip-flop 2
Since 9F2 is reset, the output of the integrating circuit 29I is TX32.
= 16V, and 1 is tuned to VHF low band 2 channels, so if you are in the Osaka area you can receive 2 channel signals.

The same applies to others. Next, the time constant switching circuit for AGC and AFC will be explained.

FIG. 5 shows an example of local AFC of a tuner. When the Q of the flip-flop 23 is at a high level, that is, during writing, the level of the Q output of the flip-flop 23 is converted by the DC level adjustment circuit 11D, the field effect transistor FET11F is made conductive, and the integration is performed. The time constant is made smaller.

Note that the time constant can be easily adjusted by inserting a series resistor on the source S or drain D side of the FET 11F.

When writing is completed, FET 11F is cut off, the time constant becomes the product of the value of resistor 11R and the value of capacitor 1C, and normal operation is performed.

The time constant of AGC can also be switched using a similar circuit configuration.

To shorten the time required for tuning, AGC circuit, AFC circuit
It is sufficient to switch at least one time constant of the circuit.

Even when the manual switch is operated, the same output as that of the multi-by-break 21M appears in the output shown in FIG. 20, and the same operation as automatic writing is performed.

As described above, according to the present invention, when sweeping reception channels to detect a channel in which a television signal is present and writing a binary signal of the channel selection voltage of that channel to a volatile memory, during automatic sweeping, Since the time constant of the tuner's AGC circuit or local AFC circuit is switched to shorten, the sweep speed can be increased, and each time the power switch is turned on, the time constant is changed to shorten.
Since the receivable frequencies can be written into the memory in seconds), a volatile memory can be used, and there is no need to provide a battery to keep the volatile memory always in operation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a channel selection device according to an embodiment of the present invention, FIG. 2 is a specific block diagram of the same device, and FIG. 3 is a more specific block diagram of a part of the same device. FIG. 4 is a waveform diagram for explaining the device, and FIG. 5 is a specific circuit diagram of a portion of the device. 1... Tuner, 6... Tuning voltage generation circuit, 7... Volatile memory circuit, 8...
・Tuition selection button, 9... Automatic writing circuit, 13...
...Main power supply circuit, 10... Tuning detection circuit,
11... Time constant switching circuit, 21D...
ON detection circuit, 21M... monostable multi-bi break, 23... flip-flop, 24...
...NAND gate, 25...Binary counter, 26A...26M...AND gate,
7a... Volatile memory, 27S, 29...
...Selector, 27C...Counter, 2γE.
... Encoder, 34, 35 ... Flip-flop, 36, 37, 38, 40L40H, 40U
...and gate.

Claims (1)

[Claims] 1 A tuner that uses a variable capacitance diode as a tuning element, a tuning voltage generation circuit that supplies the variable capacitance diode of this tuner with a DC voltage corresponding to each receiving channel, and a tuning voltage generation circuit that supplies the DC voltage corresponding to each receiving channel to a binary value. A volatile memory circuit stores the signal state in a volatile memory and supplies a predetermined storage signal to the channel selection voltage generation circuit in response to a channel selection command signal, and a volatile memory circuit that starts operation every time the power switch is turned on and When the switch is turned on, the tuning voltage generation circuit is set to an automatic sweep state, and a writing circuit writes a binary signal of the tuning voltage corresponding to each receiving channel obtained during this automatic sweeping into the volatile memory; When the generator circuit is in automatic sweep mode, the tuner's AGC circuit and local AF
A channel selection device comprising: a switching circuit that makes the time constant of at least one of the C circuits shorter than that in other states.