JPS5816766B2 - Channel selection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a channel selection device in which a volatile memory stores a channel selection voltage in the form of a binary signal, and includes a built-in battery so that the volatile memory is always in a memorized state. The purpose is to make it possible to obtain the sawtooth wave voltage, which is not necessary and is required when storing data in a volatile memory, by a simpler means.

In a tuning device that stores the tuning voltage of an electronic tuner in the form of a binary signal in a digital memory and reads it out, if a non-volatile EFROM is used as the digital memory, when used in a general home, each station can be received sequentially and then read out. EPROM requires an operation to memorize the voltage, and EPROM is expensive and has reliability problems, so it is currently not widely used.

Furthermore, in the case of EPROM, the writing and erasing times are long at 100 msec each even in MNOS, and the time required for rewriting is also considerably long.

On the other hand, volatile memory takes 100 to 500 ns to write and erase.
It is preferable to EPROM because it is sufficiently short as ec, but it has the disadvantage that it requires a constant supply of power, so a battery must be built into the receiver.

Therefore, the present invention aims to shorten the write time using volatile memory and eliminate the need for batteries by writing data every time the power is turned on. The DC voltage corresponding to each receiving channel is stored in a volatile memory in the form of a binary signal, and the stored contents are read out in response to a channel selection command signal and sent to the channel selection voltage generation circuit. An automatic write circuit is provided which operates each time the power switch is turned on, and by the operation of the automatic write circuit, a sawtooth wave voltage is generated from the channel selection voltage generation circuit when the power is turned on.
The tuner is set to an automatic sweep state, and the tuner is configured to write a binary signal corresponding to each receiving channel obtained during the automatic sweep into the volatile memory, and the i-toothed wave is supplied as a binary signal to the volatile memory. A staircase wave voltage is generated based on the upper few bits of the output of the binary counter, and a sawtooth wave that repeats at a constant period is created based on the remaining lower few bits.
The feature is that this sawtooth wave is combined with the above-mentioned staircase wave.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

1 is an electronic tuner in which a direct current voltage is applied to a variable capacitance diode which is a tuning element to control the tuning number and wave number; 2 is a video intermediate frequency amplification circuit; 3 is a video detection circuit; 4 is a synchronous separation circuit; 5 is a deflection circuit. An output circuit 6 is a tuning voltage generating circuit for the tuner 1, and 7 is a volatile memory circuit for storing the tuning voltage as a 13-bit signal, which includes a volatile memory, an encoder, a selector, and a counter.

The volatile memory here is CMO8 static RAM.
think of.

8 is a channel selection button, and it is assumed that there are 12 buttons.

9 is an automatic write circuit of the present invention, which writes data of all receivable channels to the volatile memory circuit 7 only once when the power switch 14 is turned on, that is, when a voltage appears at the output of the main power supply circuit 13. This is a circuit that allows you to

Reference numeral 10 denotes a tuning detection circuit, which generates an output pulse when an audio carrier is detected by the audio carrier detection circuit 17 and a video carrier is detected by the video carrier generation circuit 18, and drives the automatic writing circuit 9 to perform writing. Let's do it.

After writing is completed, the channel selection voltage is swept until the next channel is received.

11 is AGC and tuner local AFC, and VIP
, RF AGC time constant switching circuit.

Reference numeral 12 denotes a manual write switch, and when this switch 12 is closed, the writing state can be set.

13 is a main power supply circuit that outputs various DC voltages and supplies them to various parts.

14 is a regular TV with a power switch. It is provided on the front of the John set.

15 is a plug connected to a 100 volt AC; 16 is a video output circuit; the output of this circuit is supplied to a color cathode ray tube 19 to obtain a color image.

1 to 19, except for 9 to 12 and 17.18 are the same as a normal color television with an electronic tuner.

Next, the automatic writing operation will be explained with reference to FIG.

First, when the power switch 14 is turned on, DC voltage is supplied to the volatile memory circuit 7, and the volatile memory circuit 7 is brought into a memorizable state.

At the same time, a pulse appears at the output of the ON detection circuit 21D of the automatic writing circuit 8, and the monostable multivibrator 21M
trigger.

The output of this monostable multivibrator 21M is 100m
5 to 1 μsec is sufficient.

There is a delay of ΔT from when the power switch 140 is turned on until the monostable multivibrator 21M generates an output.

The output of the monostable multivibrator 21M is inverted by the NOR gate 22, the flip-flop 23 is set,
The Q of this flip-flop 23 is a high level, and the q is a low level.

On the other hand, when there is no output in the audio carrier detection circuit 17 or the video carrier detection circuit 18, the output of the tuning detection circuit 100 level conversion circuit 3031 is at a low level, and the NAN
The output of D gate 32 is at a high level.

Therefore, the output of the monostable multivibrator 33M is also at a high level.

Therefore, when the tuning is out of tune, the output of the tuning detection circuit 10 is at a high level.

At this time, the NAND gate 24 becomes conductive.

Since a positive horizontal pulse is applied to this NAND gate 24, the power switch 14 is at time T.

If it is input at
A 13-bit binary counter 25
starts counting H pulses.

As 25, for example, 4 integrated circuit elements 5N74LS93 are used.
It is sufficient to connect the two in series and supply the output 213 to the clear terminal of the binary counter 25 and the NAND gate 28.

Now, since the H pulse exists every 63.5 μsec,
The time required for the binary counter 25 to count 213 H pulses is 63.5xlO-6x1.024x8=0.52 seconds.

With an ordinary TV's electronic tuner, you can change the band to VHF.
Since it is divided into low band, bi-band, and UHF band, ideally all channels can be written in 0.52 x 3 in 1.6 seconds.

Now, the output of the NOR gate 22 causes a 7-lip flop 34
Since 35 is cleared, the output of AND gate 36 becomes high level, and (AND gates 3γ and 38 are at low level).

) The output from the flip-flop 230 causes the selector 39 to
Instead of the output of tuner 8, the outputs of AND gates 36 to 38 are supplied to tuner 1.

Therefore, after the time T,=T+ΔT, the three channels of the VHF low band are first swept.

The output of the binary counter 25 is an AND game) 26A~2
The signal is supplied to the volatile memory 7a and the digital-to-analog converter 29 through 13 6M gates.

The volatile memory 'J7a is a CMOS memory having 16-bit parallel input/output terminals.

Since the output of the binary counter 25013 bits represents the number of input pulses in binary, 29 is a digital/analog converter that generates a DC voltage proportional to the total number of pulses.
It is a converter.

If the number of pulses 0 is Ov and 213 pulses is 32V, there are channels 1 to 3 between them.

For convenience, if we assume that the capacitance of the variable capacitance diode of tuner 1 changes linearly with respect to DC reverse bias, then 20
1.2.303 channels will be received every 48H.

Channels 1 and 3 are received in the Tokyo area.

204.8H or 0.13 seconds after time T1 (referred to as T2), the "1" channel is received, and the tuning detection circuit 10
The output of the NAND circuit 32 becomes low level and drives the monostable multivibrator 33M.

The pulse width of this multivibrator 33M is approximately 2μse.
c, the NAND gate 24 is cut off during this period.

At the same time, the W/R terminal of the volatile memory 7a becomes low level due to the output of the negative logic AND gate 33G, and the output of the binary counter 25 at that time is 13 bits and is written to the volatile memory 7a. be included.

The write address of the volatile memory 7a is written to the counter 27c.
, and the output of the monostable multivibrator 33M is at the same address as when the channel selection button 8 is in the first position.

Next, when the output of the monostable multi-by break 33M returns to high level, the counter 25 starts counting again.
After 2048H from T2, the channel becomes "2", but
Since the output of the NAND gate 32 of the tuning detection circuit 100 does not change, after another 2048H, it is tuned to the "3" channel, and the output of the monostable multivibrator 33M becomes low level again for about 2 μsec, and the volatile memory 7 is pinned. The output of counter 25 is written.

Since the output of the monostable multivibrator 33M is the second, the write address becomes the same address as in the case of the second position of the channel selection button 8.

Note that the selector 27S is controlled by q of the flip-flop 23 and supplies an address obtained by counting the output of the monostable multivibrator 33M to the volatile memory 7a.

The time until the end of writing for "3" channel is 2048H
+2 μsec+4096H+ 2μs e c 0.
39 seconds, and after 2048H, the binary counter 2
5's 213 output becomes high level, volatile memory 25
be clearly set as time T1) and flip-flop 3
Set 4.

Therefore, the Q of the flip-flop 34 becomes high level,
Q becomes low level, and the output of AND gate 37 becomes high level.

Since the Q output of the flip-flop 34 is applied to the terminal of the flip-flop 35, the flip-flop 35 is not set at this time, but is set by the next set signal.

Therefore, the band switching of the tuner 1 is VHF biband.

VHF bi-band has 4 to 1209 channels, so
One channel is received approximately every 820 hours.

That is, at T4 or T after 820H, it is tuned to channel 4, and the output of flip-flop 33M becomes low level.
As before, the output of the binary counter 25 is written to the address corresponding to the third position of the channel selection button 8.

Since VHF bi-band has 5 channels of 4.6.8° and 10.12 in Tokyo, the writing time increases by 10 μSeC, and the writing ends in 8192H+10 μ5ec=0.52 seconds TIO.

The same goes for the next UHF pad, 8192 from TIO.
Writing ends after H+2n.

If UHF band μSeC Even if there are 4 stations, the time is 0.52 seconds.

Therefore, the total is 0.52+2n (n is the received μS
Writing ends at eC (number of possible stations).

The time required to write both VHF and UHF is approximately 819
It is 1,56 seconds in 2X3X63.5.

When writing is completed, the output of the AND gate 38 is at a high level, the output 213 of the binary counter 25 is at a high level, and after sweeping to the highest UHF channel "62", this output appears and the output of the NAND gate 28 becomes a low level. and clears the flip-flop 23.

Therefore, NAND gate 24 is blocked and 26A-26
M is also blocked.

26A to 26M are so-called tri-stays) (Tri
-5tate) (a gate that takes three states of 0, 1 and high impedance), and when cut off, the output terminal becomes high impedance.

The Q of the flip-flop 23 becomes high level, and both the selector 39 and the selector 27S enter the read state.

In addition, the tuning button 8 generally has 12 positions, and as mentioned above, the low band of VNF has 2 channels, and the VHF
The bi-band S channel novel UHF band is written as 4 channels, up to the 11th channel, and there is one channel left over, but there is no need to use it.

This concludes the explanation of the main parts of the embodiment of the present invention, but some supplements will be added about each part.

An example of 26A to 26M is an integrated circuit element 5N7412.
6 or DM8094.

An example of the selector 390 is an integrated circuit 5N74LS157.
There is.

Integrated circuit 5 as an example of monostable multivibrator 33M
% or SN of N74LS123? There is 4121.

27C is a write address counter that counts the leading edge of a negative write pulse when it appears at the output of the monostable multivibrator 33M.

Therefore, as mentioned above, one channel of VHF has address 0.
001, and the third channel is 0010, VHF
The 12th channel is 0111.

On the other hand, the Se terminal of 27S is connected to the Q of flip-flop 23.
Since the signal is at a low level, the output of 27S becomes the A input part, and becomes the output of 27C.

Therefore, address 0001 of volatile memory 7a contains 1
A 13-bit binary signal corresponding to a channel is written.

On the other hand, 40L 40H40U in FIG. 2 is the same AND gate as 26A to 26M, as shown in FIG.

In the volatile memory 7a, the channel selection voltage is written in 101 to 13, and 14 to 16 correspond to V(7)L, H, U.
When writing and reading Ilo, when it is VHF1 channel, the output of AND gate 36 is high level, so 11014
1 is written to.

In other words, 11 for write addresses 0001 and 0010.
11'' is supplied to 014 and written.

For VHF channels 4 to 12, press "1" to 11015.
is supplied and written.

In the case of U, "1" is supplied to 11016 and written.

Next, when the writing of U is completed and a positive pulse is generated in the output of the binary counter 25, the flip-flop 23 is cleared, and the terminal Se of the selector 27S becomes high level, and the output of the selector 27S becomes the output of the encoder 27E, that is, the selection This becomes the channel position specified by station button 8.

The encoder 27E converts decimal numbers 1 to 12 into binary 4-pit numbers.

It is an encoder. Since the Q of the flip-flop 23 is at a high level, the output of the gate 36G is at a high level, and the volatile memory 7 enters the read state.

The output of the selector 39 also becomes the B input.

If you press the 803rd channel selection button, the encoder 27E
The output of is 0011, and the output of volatile memory 7 is I/(
Binary signals corresponding to the four VHF channels appear in H-13, and only 15 out of 11014-16 becomes 1, instructing the tuner 1 to bi-band VHF.

Note that the outputs of the gates 26A to 26M and 40L to 40U have high impedance.

The output of 101 of the volatile memory 7 is supplied to the digital-to-analog converter 29, and a control voltage corresponding to four channels is obtained as an output of the digital-to-analog converter 29, which is supplied to the tuner 1 to receive the four channels.

An example of a digital-to-analog converter 2901 is shown in FIG.

In FIG. 3, 29C is a 10-bit comparison circuit, 29A is a 10-bit synchronous counter, 29F is a flip-flop, and 29G is a gated oscillator that oscillates at approximately 18ME (z).

Further, in FIG. 4, ψ1 is a horizontal synchronizing signal, and the period from tl to t2 is approximately 63.5 μsec.

The pulse width of the output of oscillator 29G is It is.

Therefore, even if 210=1024 outputs of the oscillator 29G are counted, it will take approximately 56.9 μsec, and 210 outputs can be counted within the IH.

tl in FIG. 4 is the first horizontal synchronizing signal after T1 mentioned above, and the beginning of ψ2 is a pulse with a width of about 556 nsec from tl.

That is, the flip-flop 29F is set at t, and the oscillator 29G oscillates.

At this time, the output of the binary counter 25 is 000000
0000001, and the output pulse of oscillator 29G is 1
After counting, the comparator circuit 29C detects a match between both inputs,
Reset flip-flop 29F.

Therefore, oscillator 29G stops oscillating.

Therefore, the width of the Q output of the flip-flop 29F is the width of the oscillator 29
One pulse of G is approximately 55.6 nsec.

In the next IH, the width of φ2 becomes 2×55.6 n5ec, which increases by one pulse every H1.

Therefore, up to 1023H, the voltage shown in FIG.
9820 obtained at both ends.

A field effect transistor 2981 is connected in parallel to the capacitor 2908.
The Q output of the flip-flop 29F is added to the gate of the transistor 2981.
becomes conductive, and the output voltage of capacitor 2908 becomes as shown in FIG. 6B.

The length of the horizontal axis of the sawtooth wave in FIG. 6B gradually increases toward the right.

The voltage applied to capacitor 2982 via diode 2910 increases little by little.

Figure 6A shows a horizontal pulse.

Considering the period from time t1 to 1024H, capacitor 2
The voltage obtained at 982 is as shown in FIG. 5B.

When the voltage reaches 1024H, the field effect transistor 2983 becomes conductive, and the charge in the capacitor 2982 is discharged to return to its original state, resulting in a sawtooth wave.

Until 1023H, the counter 25 outputs O1■ to the 2° to 29 outputs, and the 210 to 213 outputs are 0, and the Q output of the flip-flop 29F increases by 1 bit every H, so this output is output via the resistor 2901. is transmitted to the base of transistor 29020.

Transistor 2902 performs a switching operation, is conductive while the Q output of flip-flop 29F is at a high level, and the collector of transistor 2902 is approximately at ground potential.

Resistors 2903 and 2904 are set to values such that when transistor 2902 is conductive, transistor 2906 operates in class A.

2905 is a feedback resistor and may be omitted. 2907 is an integrating resistor, 2908 is an integrating capacitor, and as will be described later, when all the transistors 2916 to 2976 are off, that is, from t1 to just before 1024H in FIG. 5, the sawtooth wave voltage in FIG. 5B is A resistor of 29,000 is obtained across the board.

At the 1024th H, the binary counter 25 reaches 210.
The output becomes 1, the 1 output of the decoder 29D becomes low level, and the transistor 2914 becomes conductive.

That is, the resistors 2911 and 2912 are determined to have such values as to cut off the transistor 2914 when one output of the decoder 29D is at a high level.

The diode 2913 will be described later.

The decoder 29D is an integrated circuit SN 7442 or 5.
N74LS42 is suitable.

When transistor TR2914 conducts, resistor 2915
The collector current of transistor 2914 flows through the transistor 2914, the base potential of transistor 2916 decreases, and the
916 becomes conductive and connects to the resistor 2900, 1024H in FIG.
A voltage shown at ~2048H is generated.

On the other hand, the Q output of 29F again expands by 1 bit every H, and the sawtooth voltage shown in FIG. It will look like the dotted line.

The same goes for the rest, and from the 2048th H, the binary counter 2
211 output of 5 becomes 1, and (2) of decoder 29D
The output becomes a low level and (1) the output becomes a high level.

However, through diode 2913, transistor 2
The collector current of 914 flows into the (2) output of decoder 29D.

Similarly, every 1024H, (3) of the decoder 29D
, (4), (5), (6), and (7) become low level in sequence, and accordingly, the diodes 2923 to 2963 become conductive one after another, and the transistors 29142924...
・2974 is conductive, and in 7168H to 8192H, transistors 2914 to 2974 are all conductive and resistor 2900 is conductive.
The staircase wave voltage shown in FIG. 5A, which is generated in FIG. 5A, is at the highest level.

Therefore, the dotted waveform shown in FIG. 5A is applied to the tuner 1.

Next, when reading data from the volatile memory 7a, 1
During the output of 3 bits, the upper 3 bits are applied to decoder 29D to determine which step in FIG. 5A.

If the output from volatile memory 7a is 100100000
0000 and 8 channels of VHF.

The decoder 29D (4) output becomes low level, and the resistor 2
v4 is generated at 900, and the voltage added thereto is equivalent to 512 bits of the pulse of the gated oscillator 29G.

In the present invention, since the sweep voltage is divided into a staircase wave and a sawtooth wave, the digital-to-analog converter 29 can be converted into a normal TTL
(or Lowpower Schottky).

If all sawtooth waves are used without dividing, the comparator circuit 29
C. The counter 29A has become 13 bits, and the gated oscillator 29G cannot count 8192 pulses during IH unless it is oscillated at a frequency 23 or 8 times higher. Therefore, the voltage change during sweep writing becomes slower. Write speed decreases.

If the frequency is increased eight times (approximately 150 to 160 MHz), there is a drawback that normal TTL cannot be used.

The present invention is revolutionary in that it eliminates these drawbacks.

As described above, according to the present invention, it is possible to write to the memory every time the power is turned on, so a volatile memory can be used, and the disadvantage of using a volatile memory is the battery. It is also a concern to have it built-in.

Furthermore, the sawtooth wave voltage applied to the tuner can be generated using not only a sawtooth wave generation circuit (i.e., a staircase wave created based on the output of the upper few bits of the binary counter, but also a staircase wave created based on the output of the lower several bits of the binary counter). Since the circuit that generates the sawtooth wave is used, the circuit that generates the sawtooth wave can be easily and inexpensively realized.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a channel selection device in an embodiment of the present invention,
Fig. 2 is a concrete block diagram of the main parts of the device, Fig. 3 is a circuit diagram of the main parts of the device, and Figs. 4, 5, and 6 are waveform diagrams for explaining the device. It is. 1... Tuner, 6... Tuning voltage generation circuit, γ... Volatile memory circuit, 8...
・Tuition selection button, 9... Depression writing circuit, 10...
... Tuning detection circuit, 13 ... Main power supply circuit, 1
4...Power switch, 25. Song/binary counter, 29D...Decoder, 2913-296
3...Diode, 2911-2974.29
16-2976... tune transistor, 2900...
...Resistance, 1a... Volatile memory, 29C...
... Comparison circuit, 29A ... Counter, 29
G: Oscillator, 29F: Flip-flop, 2902.2906: Transistor, 29o82982: Charge/discharge capacitor.

Claims (1)

[Scope of Claims] 1. A tuner using a variable capacitance diode as a tuning element, a tuning voltage generation circuit that generates a DC voltage according to each channel and supplies this DC voltage to the variable capacitance diode of the tuner, and the above-mentioned tuner. Volatile memory stores binary signals corresponding to DC voltage, and starts operation every time the power is turned on.
Binary signals corresponding to each channel generated from a plurality of output terminals of the binary counter are sequentially stored in the volatile memory, and in order to perform this storage, the channel selection voltage generation circuit is controlled to control the variable capacitance. and a write circuit that applies a sawtooth wave voltage to the diode, and as a means for generating the sawtooth wave, a decoder decodes the upper bits of the binary signal obtained at the plurality of output terminals of the binary counter, The obtained signal is used to generate a step wave voltage with a thick voltage at a constant period, and the remaining lower few bits in the binary signal are used to generate a sawtooth wave voltage that returns to the original state at the constant period. 2. A channel selection device characterized by using means for generating the step wave voltage and the sawtooth wave voltage. 2. Diodes are connected between a plurality of output terminals of the decoder with the same polarity, respectively. The channel selection according to claim 1, characterized in that both terminals of the plurality of diodes and the connection point of each diode are connected to a control terminal of a switching circuit connected between one load resistor and a power supply terminal. Device.