JPS583618B2 - Sadou Parsuichi Henchyousouchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a differential pulse position modulation device that transmits a digital quantity of M values by the interval between adjacent pulses, and in particular, to avoid intersymbol interference or to provide a margin for the operation timing of circuit elements. This invention relates to a pulse position modulation device in which the minimum interval between pulses is R time slots in order to increase the pulse position.

For M-value differential pulse position modulation, one word period is divided into M time slots, and the result βi is obtained by adding the input digital signal and the pulse position βi-1 of the previous word by the modulus M.
and the pulse position are sent out in correspondence with each other.

That is, the calculation result is made to correspond to the pulse position.

A device that performs the above calculations is realized, for example, as shown in FIG.

That is, the matching circuit 4 compares the M-value digital amount applied to the input terminal 1 and the contents of the counter 3 that counts the clock signal applied to the terminal 5 by the timing generation circuit 2, and when the two match, the matching circuit 4 Outputs a pulse as a detection signal.

This pulse passes through the inhibit circuit 7 and is supplied to the output terminal 8 and the reset terminal 6 of the counter 3, setting the content of the counter 3 to O.

The inhibition circuit 7 allows only the first pulse of the pulses supplied from the matching circuit 4 within one word period defined by the word pulse of the other output of the timing circuit 2 to pass.

As described above, one pulse is supplied to the output terminal 8 during one word period, and the interval between adjacent pulses in the pulse train is defined as 0, which is the interval when pulses occur successively. It takes a value up to 2M=2.

The above operation will be explained with reference to the time chart shown in FIG.

Here, M=8, and one word is divided into eight time slots from 0 to 7.

First, βi-1=0, that is, the content of counter 3 in the first time slot of the first word in the figure is 0.
When αi=3, a pulse is generated as the pulse sequence P1 in the third time slot.

Immediately, the counter is reset to 0, and g in the counter 3 is incremented for each time slot in order of 1, 2, 3, . . . as shown in B1 of the figure.

The content of the counter becomes 3 again within the same word, but at this time, the generation of P1 is prohibited by the prohibition circuit 7, and the content of the counter 3 continues to increase, and when the content reaches 8, the counter 3 returns to 0. .

Therefore, in the fifth time slot of the next word, the content B1 of the counter becomes 2, which coincides with αi, a pulse is generated and the counter 3 is reset to zero.

In other words, the result of the calculation for αi=2 and βi-1=3 is expressed by the pulse position.

P1 in the third and fourth words of Figure 2
Since pulses are generated continuously (interval=0), which may cause inconvenience, conventionally, this has been avoided by the following method.

That is, an extra time slot in which no pulse occurs is added to one word.

This will be explained with reference to the pulse sequence P2 of FIG. 2 generated in this way and the corresponding content B2 of the counter 3.

Here, one word is constructed by adding four extra time slots in addition to the eight time slots in which signals are generated.

Since the number of time slots in which each pulse of pulse sequence P2 occurs is exactly the same as the number of time slots in which pulses in P1 occur, No pulse is generated.

This operation is realized by fixing the four time slots following the generation of a pulse to 0 and counting as 1, 2, and 3 starting from the fifth time slot, as shown at B2 in FIG.

In other words, the clock pulse applied to terminal 5 in Figure 1 is applied to terminal 8.
This is prohibited only during the four time slots immediately after the pulse is generated.

Such extra time slots may of course be inserted at any position within the word, or may be distributed within the word.

However, in order to provide an extra time slot, a counter is required to set the period during which clock pulses are inhibited as described above, and for example, to add 7 extra time slots, a hexadecimal counter is required. It takes.

Therefore, the advantage of the differential pulse position modulation method, which allows PPM communication with a simple circuit, is somewhat reduced.

An object of the present invention is to provide differential pulse position modulation that eliminates the need for a counter to create the above-mentioned extra time slots, or allows the number of stages of such a counter to be freely selected to increase the degree of freedom in logic design. The goal is to provide equipment.

According to the present invention, when applying a signal to one of M time slots and transmitting pulses as in the past, an M-adic binary counter is used, and the interval between adjacent transmission pulses is at least R. One word is configured into M+R time slots so that the number of time slots is not less than the number of time slots.

Therefore, the stop period of the pinary counter is not R but less than R-1 time slot and includes zero, that is, the counter does not need to be stopped at all.

The embodiment of the differential pulse position modulation device according to the present invention has the same configuration as that shown in FIG. .

In such a configuration, the input digital amount αi and the number γi indicating the pulse position have the following relationship.

Here, γi-1 is the pulse position one word before, R is the number of additional time slots where no pulse occurs, and the difference between the period of counter 3 and one word period is expressed in the number of time slots. be.

Also, demodulation is performed using the following formula.

Next, one period of counter 3 in Fig. 1 is divided into 8 time slots.
The operation of an embodiment in which one word has 12 time slots will be explained with reference to the time chart of FIG.

P3 indicates the output pulse train in this embodiment, and B3 indicates the contents of the counter 3.

Let αi=3 in the first word and B3=0 in the first time slot.

Counter 3 sequentially increments its contents to 1, 2, 3, and αi
When γi = 3, a pulse is generated and applied to terminals 6 and 8, and counter 3 is reset and continues counting 1, 2, 3, etc.
In the next word, a pulse occurs in the first slot where αi is equal to the value 2 for the first time.

This is equivalent to expressing the result of an operation as a pulse position.

Since the result of modulo 8 addition does not yield a number greater than 8, counter 3 is reset when an output pulse occurs, after which output pulses are inhibited until the next word, and counter 3 is reset at the beginning of each word. Since 0 to 7 are always counted from the 8th time slot to the 8th time slot, an output pulse is never generated in the 4 time slots from the 8th to the 11th within a word.

In this way, the minimum interval between pulses can be arbitrarily set without performing any operation to stop the operation of the counter 3.

In some cases, it may be necessary to stop the operation of the counter 3 in order to provide a margin for the operation timing of the logic elements of the demodulator.

On the other hand, the number R of time slots to be added to the number M of time slots in which pulses can occur in one word is determined by the relationship between the clock frequency, word frequency, and the number of bits of the input amount αi based on the configuration of the timing circuit. It is limited to a certain extent.

For this reason, R is often larger than the required counter stop period.

At this time, if the required counter stop period is S and the period during which the counter is actually stopped is U, then U can be selected as the pattern that provides the most desirable circuit configuration under the following restrictions.

At this time, the following relationship holds between the input amount αi and the pulse position δi.

Demodulation is It is obtained by

An embodiment based on this principle is shown in FIG.

In the figure, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and 11 is a circuit that inhibits clock pulses to the M-ary counter 3 for a period of U time slots immediately after the pulse is generated at the terminal 6. It is.

Only one pulse is generated at the terminal 8 in one word period determined by the timing circuit 2, that is, in the M+R time slot,
No pulses occur in the last R time slots of each word.

Further, the counter 3 stops operating during the U time slot immediately after the pulse is generated at the terminal 8.

As explained above, since it is no longer necessary to match the minimum interval R of output pulses with the counter stop period U, the degree of freedom increases in the timing and configuration of each logic circuit, and when U=0, the conventional R=0 The only difference from the modulation circuit is the length of one word period, and the minimum pulse interval R can be achieved without increasing the circuit scale at all.
You can choose any number greater than or equal to 1.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional differential pulse position modulation device in which the minimum pulse interval is 0, and FIG. 2 is a block diagram showing an example of a differential pulse position modulation device in which the minimum pulse interval is 0 according to the conventional method. A time chart for explaining the operation and the operation of the device in which the minimum pulse interval is 4 according to the present invention and the stop period of the counter is 0. Fig. 3 shows an example in which the counter stop period is shorter than the minimum pulse interval according to the present invention. FIG. 1: Input terminal, 2: Timing circuit, 3: M-ary binary counter, 4: Match circuit, 7: Inhibition circuit, 8: Output terminal.

Claims (1)

[Claims] 1. A coincidence between the inside of the M-ary binary counter that counts the clock signal supplied from the timing generation circuit and the M-value input digital amount is detected, and the detection signal issued upon detection of this coincidence causes the M-ary binary counter to The M-adic pinary counter is reset and performs the summation of the previous word's calculation result and the input digital quantity, and this calculation result is applied to one of the M signal time slots in the word to generate a pulse. In a differential pulse position modulation device that transmits a digital quantity with an interval of M values between adjacent pulses, and in which one word consists of M+R time slots so that the minimum pulse interval is not less than R time slots. , a differential pulse position modulation device comprising means for stopping the M-adic pinary counter for a period equal to or less than R-1 time slot (including zero) in response to the detection signal.