JPS5836381B2 - shared memory controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a shared memory control method in a multiprocessor system that includes a plurality of processors and distributes processing to each processor.

In multiprocessor systems, multiple processors and main memory are connected by a common bus to share the main memory, but there are problems of contention and priority.

Conventionally, when one processor is using main memory, other processors have stopped executing their processes.

Furthermore, when bus requests are received from two or more processors at the same time, the priority order cannot be determined, resulting in unstable operation.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a shared memory control method that can improve the operating rate of a processor and ensure stable operation.

Embodiments of the present invention will be described in detail below with reference to the drawings.

Figure 1 shows two microprocessors (called MPUs)
A multiprocessor system is shown.

Subscripts A and B are added to distinguish each MPU, their peripheral devices, and each control signal, respectively.

Each MPUIA and IB are internal memory lJ2A and 2B, respectively.
are connected by data, address, and control buses.

Furthermore, the two MPUIAs and IBs are connected via common data, address, and control buses via a shared memory (main memory) 6 and bus gates 7A and 7B.

Each MPUIA, IB includes selection switches 3A, 3B and comparison circuits 4A, 4B, respectively.

The selection switches 3A and 3B are used to set the address range of the shared memory 6 used by each MPUIA and IB.

The comparison circuits 4A, 4B output bus request signals (A.-, B-, BUS-) when the address designated by each MPUIA, 1B is included in the address range set by the selection switches 3A, 3B. REQ) respectively.

For example, when the selection switch 4A is set to 4000, when the MPU 1A specifies one of the addresses 4000 to 4FFF, a bus request signal (A-BUS-REQ) is output from the comparison circuit 4A.

This bus request signal is input to the bus control circuit 5.

When the bus control circuit 5 receives a bus request signal, it outputs a bus enable signal (A or B-BUS-EN) if the shared memory 6 is not used by another MPU.
B), and if shared memory 6 is in use, the memory
It outputs a ready signal (A or B-MRDY) and also outputs two bus request signals (A-BTS-R
If EQ) (B-BUS-REQ) are input at the same time, determine the priority and assign the bus to the one with the higher priority.
It outputs an enable signal and a memory ready signal to the other.

For example, the bus request signal (A-BUS-R
If the shared memory 6 is not being used by the MPUIB, the bus enable signal (A
-BUS-ENB).

This bus enable signal (ABUS-ENB) opens the bus gate 7A, allowing the MPUIA to access the shared memory 6.

If the shared memory 6 is in use by MPUI B,
A memory ready signal (A-MRD) is sent from the bus control circuit 5.
Y) will be output and one MPU will be placed on temporary standby.

In other words, execution is stopped by stopping the internal clock while holding the address and data for shared memory access.

As will be understood from what will be described later, when the MPUIB finishes using the shared memory 6, the bus control circuit 5 outputs a bus enable signal (A-BUS-ENB), allowing the MPUIA to use the shared memory 6. become.

FIG. 2 shows details of the bus control circuit 5, and FIG. 3 shows its operation.

The bus control circuit includes D flip-flops 11a and 1lb that determine the priority order of bus request signals, an RS flip-flop 12 that receives the outputs of these D flip-flops 11a and 1lb, and is composed of two NAND circuits, and a D flip-flop 11a and 1lb that determine the priority order of bus request signals. NAND circuit 1 which receives the outputs of 11a and llb and the bus request signal as inputs.
3a, 13b, and logic circuits 14a, 1 that generate a memory ready signal and a bus enable signal from the outputs of the NAND circuits 13a, 13b and the RS flip-flop 2.
4b.

Each of the logic circuits 14a and 14b includes two NOR circuits (
Negative logic NAND circuit) 15a, 16a, 15b, 16b
Consisting of

D flip-flop lla, 1lb data input terminal D
Each bus request signal (A-, BBUS-R
EQ) is input.

Clock input terminal T of one D flip-flop 11b
The clock pulse CK is input to the D flip-flop 11a, and the NOT circuit 1 is input to the clock input terminal T of the other D flip-flop 11a.
The clock pulse CK, which is an inverted version of 7, is input.

These D flip-flops 11a and 1lb take in the signal input to the data input terminal D at the rising edge of the clock pulse input to the clock input terminal T.

Since clock pulses with inverted phases are input to the clock input terminals T of the D flip-flops 11a and Ilb, it is assumed that the bus request signals (A-BUS-REQ) are input to both flip-flops 11a and Ilb at the same time. Either bus request signal is selected depending on the phase of the clock pulse input to terminal T.

When both D flip-flops 11a and 11b are reset, their outputs Q are at the L level, so the outputs Q and Q of the RS flip-flop 12 are both held at the H level in the initial state.

Referring to FIG. 3, for example, the bus request signal (
When A'-BUS-REQ) (H level) is input, the D flip-flop 11a is set at the falling edge of the clock pulse CK, and its output Q becomes H level.

Therefore, the output Q of the RS flip-flop 12 becomes L level.

Since the output of the NAND circuit 13a also becomes L level, NO
An H level bus enable signal (A
One BUS-ENB) outputs.

Since the output Q of the RS flip-flop 12 is H, the answer is NO.
The output of the R circuit 16a remains at the L level.

Furthermore, since the output of the NAND circuit 13b is at H level, the outputs of logic circuit 14b are both at L level.

In this state, the bus request signal (B-BUS・REQ)
) is input, the D flip-flop 11b is set at the rising edge of the clock pulse CK, and its output becomes H level.

Therefore, the output of the NAND circuit 13b becomes L level.

However, the output Q of the RS flip-flop 12
Since remains at L level, its output Q is held at H level.

Therefore, there is no change in the output of the logic circuit 14a.

When the output of the NAND circuit 13b goes low, the memory ready signal (B-MRDY) at the high level is output from the NOR circuit 16b.

When the bus request signal (A-BUS-REQ) stops and goes to the L level, the D flip-flop 11a is reset at the falling edge of the clock pulse CK, and its output Q goes to the L level.

Therefore, the RS flip-flop 12 is inverted and its output Q becomes H level and Q becomes L level.

Therefore, the bus enable signal (A-BUS-
ENB) and memory ready signal (B-MRDY) go low and stop, and a bus enable signal (B-BUS-ENB) at high level is output.

Bus request signal (B-BUS-REQ) is L
When it stops, the output Q of the D flip-flop 1lb goes to the L level at the rising edge of the clock pulse CK, so the outputs Q and Q of the flip-flop 12 both go to the H level, returning to the initial state.

Also, since the output of the NAND circuit 13b becomes H level,
The bus enable signal (B-BUS・ENB) goes to L level and stops.

Both bus request signals (A-, B-BUS・REQ)
are input at the same time, if the clock pulse CK rises at the next time, first the D flip-flop 1l
b is set and its output Q becomes H level.

As a result, the output Q of the RS flip-flop 12 becomes L level, and the output of the NAND circuit 13b also becomes L level, so that a bus enable signal (BBUS-ENB) is output from the NOR circuit 15b.

Then, at the next fall of the clock pulse CK, the D flip-flop 11a is set, and the output of the NAND circuit 13a becomes L level, so that the memory ready signal (A-MRDY) is output from the NOR circuit 16a.

However, the output Q of the RS flip-flop 12 is low.
Since the output Q is held at the L level, the bus enable signal (A-BUS-
ENB) is not output.

When only the bus request signal (B-BUS-REQ) goes to L level, the D flip-flop 1lb is reset at the rising edge of clock pulse CK and its output goes to L level, so the output Q of RS flip-flop 12 goes to H level. As a result, the output Q of flip-flop 12 becomes L level.

Therefore, the bus enable signal (B-BUS-EN
B) and memory ready signal (A-MRDY) fall, bus enable signal (A-BUS-ENB)
rises to H level.

After this, the bus request signal (A-BUS・REQ)
When the signal goes to L level, it goes to D at the falling edge of clock pulse CK.
Since the flip-flop 11a is reset, the output Q of the RS flip-flop 12 becomes H level, and the bus enable signal (A-BUS-ENB) stops.

Conventionally, the bus request signal was directly input to the RS flip-flop 12, so if the bus request signals were input at the same time, the RS flip-flop would become unstable or oscillate, but in this invention, as described above, Since the priority order of the D flip-flops 11a and 11b is determined by shifting the timing, the RS flip-flop 12 is reliably set or reset and stable operation can be ensured.

FIG. 4 shows a bus leg circuit used in a multi-system with four MPUs.

Therefore, there are four bus request signals (A--D-BUS-REQ) as input signals, which are input to the data input terminals D of separate D flip-flops 113-11d, respectively.

When these bus request signals are output at the same time, their priority is determined by the output of the ring counter 21.

The ring counter 21 counts the output of the oscillation circuit 22 and periodically and sequentially generates outputs at its four output terminals.

The output of this ring counter 21 is the D flip-flop 1.
It is input to clock input terminals T of 1a to 11d, respectively.

Therefore, when a plurality of bus request signals are input at the same time, the output of the ring counter 21 among the D flip-flops 11a to 11d is input first.
The flip-flop is set earliest, and the MPU corresponding to that D flip-flop is given highest priority.

The circuit 20 that maintains this priority order has four inputs.
It is composed of NAND circuits 20a to 20d.

These NAND circuits 20a to 20d have corresponding D
The output Q of the flip-flop and the outputs of three other NAND circuits are input.

The outputs of these NAND circuits normally go to H level, and when the output Q of the corresponding D flip-flop goes to H level, the output of that NAND circuit goes to L level.

Since this L level output is input to the other three NAND circuits, even if the output Q of the other D flip-flop becomes H level, the output of the other NAND circuits will be L level.
level is prohibited.

Then, when the D flip-flop with the highest priority is reset and the output of the NAND circuit that outputs the L level signal becomes H level, the output of the NAND circuit corresponding to the D flip-flop set next becomes L level. become.

In FIG. 4, the NAND circuits 13a and 13 of FIG.
A circuit corresponding to the D flip-flops 11a to 11d is provided instead, and the outputs Q of the D flip-flops 11a to 11d are connected to the NOR circuit 1.
It is input to one input terminal of 5a to 15d and 16a to 16d.

The output of the corresponding NAND circuit is input to the other input terminal of the NOR circuits 15a to 15d, and when this output and the output Q of the corresponding D flip-flop are both at L level, the bus signal at H level is input. An enable signal is output.

The other input terminals of the NOR circuits 16a to 16d have an OR
NAND circuits 20a to 2 via circuits 17a to 17d
The outputs of three other non-corresponding NAND circuits among 0d are input.

Therefore, the corresponding D flip-flop is set and its output Q becomes L level, and the other 3 uncorresponding
If the output of any one of the two NAND circuits is at L level (therefore, a bus enable signal is being output), a memory ready signal is output from that NOR circuit.

Thus, the present invention is applicable to multiprocessor systems having any number of processors.

If there is no limit to the execution stop time of a processor having a memory ready signal, the number of processors can be increased without limit.

As explained in detail above, according to the present invention, in a multiprocessor system in which a plurality of processors are connected to a shared memory and a common bus, when two or more memory request signals are issued, the priority order is determined reliably. This enables a stable common bus connection.

Further, since other processors are temporarily put on standby only in the case of competition due to simultaneous requests from a plurality of processors, the operating rate of the processors can be improved.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing a multiprocessor system consisting of two processors, Figure 2 is a block diagram showing details of the bus control circuit, and Figure 3 is a time block diagram showing the operation of the circuit in Figure 2. FIG. 4 is a block diagram showing an example of a bus leg circuit in the case of four processors. IA, IB...Microprocessor, 3A, 3
B...Selection switch, 4A, 4B...
... Comparison circuit, 5 ... Bus control circuit, 6 ...
...Shared memory, 7A, 7B...Bus gate, 11a-11d...D flip-flop (priority determining circuit), 12...RS flip-flop (holding circuit) ), 14a to 14d...logic circuit, 20...holding circuit, 21...
ring counter.

Claims (1)

[Scope of Claims] 1. In a multiprocessor system including a plurality of processors and a shared memory connected to them via a common bus, a shared memory request signal output from each processor is received and communication between that processor and the shared memory is performed. The bus control circuit includes a bus control circuit that controls the connection of the bus, and the bus leg circuit includes a priority determination circuit that determines the priority level when shared memory request signals are simultaneously output from multiple processors; a holding circuit that holds the determination result of
A shared memory control device comprising a logic circuit that outputs a signal to connect a prioritized processor to the shared memory and a signal to put other requested processors on standby based on the output of the holding circuit. 2. The shared memory supporting device according to claim 1, wherein the priority order determining circuit determines the priority order according to the order of pulse signals that are repeated at a constant cycle. 3 An address setting circuit that determines the address range of the shared memory used by each processor for each processor compares the address range set by this address setting circuit with the address specified by each processor, and if they match, requests for shared memory are made. The shared memory control device according to claim 1, further comprising a comparison circuit that outputs a signal.