JPS6149712B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a priority control system for use of a common bus in a multi-processor system in which a plurality of processors are connected in parallel to a common bus. Microprocessors generally require a long processing time because their processing speed is slow compared to the bus usage time, and because they are inexpensive, a large number of processors are used with a common bus. What is desired for such a multi-processor system is that the order of use of a common bus by a large number of processors is properly controlled, and that the system allows for easy addition and modification of processors (in other words, a common bus for each processor is required). If a bus control circuit is installed, it will be necessary to install a new signal line between the added processor and the bus control circuit when adding a processor, which will complicate the work, but without a common bus control circuit. In other words, the task becomes easier as it is only necessary to connect the processors in parallel to a common bus.Therefore, a system without a common bus control circuit (in other words, a system that does not require a common bus control circuit is desirable), bus configuration For example, it is compact (few bus signal lines). Generally, in a multi-processor system that uses a common bus, some kind of control is performed on the right to use the bus for each processor in order to solve the problem of bus use contention among the processors. Conventionally, this type of bus usage right control method generally gives priority to each processor in bus usage, and processes bus usage requests from each processor in accordance with that priority.In practice, this method There were both series and parallel methods to achieve this. FIG. 1 shows a block diagram of the configuration of a conventional serial bus usage control system. Here, 1 to i are processors, with 1 having the highest priority and i
is set to the lowest. Figure 2 shows each processor (for example 1) in Figure 1.
FIG. 3A is a timing diagram showing the timing of a bus access request when the bus is idle, and FIG. 3B is a circuit diagram showing a bus access control circuit when two processors simultaneously request bus use. FIG. In these figures, is a signal that is active when there is no bus use request from the higher level, is a signal when there is no bus use request from the higher level for the lower level, is the signal that the bus is currently being used, BCLK is the bus clock, and REQ is not shown. END is a bus use end signal from the CPU, and ACK is a bus use permission signal to the CPU.As is clear from Figures 2 and 3A, The bus use request REQ is accepted when the bus is not in use (off) and there is no bus use request from the upper processor (on), and the flip-flop FF is set to signal the bus to indicate that the bus is in use (on). emits. Furthermore, when two processors (for example, 1 and 2) issue bus use requests at the same time, as can be seen from the timing diagram in Figure 3B, the bus use request from processor 1, which has a higher priority, is accepted, and processor 2 The request is made to wait until processor 1 finishes using the bus. Such serial bus usage control methods have the following drawbacks: (1) The number of processors that can be connected to the bus is limited by the signal propagation time and system bus speed; (2) The system configuration makes it difficult to use the motherboard, and the number of processors used is limited. (3) It is not easy to add or change processors. FIG. 4 shows a block diagram of the configuration of a conventional parallel bus usage control system. Here, 11 is a bus controller, and 1 to i are processors. Regarding the bus use signal, each processor is connected to the bus controller 11 via a common line, and receives the bus use request signals _{1 to i} and the bus use permission signal.
_1-i , each processor is connected to bus controller 11 via a separate line. Figure 5 shows the bus controller 1 in Figure 4.
1 is a circuit diagram showing the circuit configuration of No. 1, but it will be understood that as the number of processors connected to the controller increases, the number of circuit elements increases in proportion. FIG. 6 shows each processor (for example, i) in FIG.
It is a circuit diagram showing a bus use control circuit in
Figure 7A shows processor i in the bus idle state.
FIG. 7B is a timing diagram showing the timing of bus access requests from processors i and j, and FIG. 7B is a timing chart showing the timing when two processors i and j simultaneously issue bus use requests. The operation will be explained with reference to FIGS. 5, 6, and 7A. Bus usage request in processor i
Flip-flop _FF1 is set by REQi and bus use request signal BRQi is issued. Since the bus is idle (off) at this time, the bus controller 11 accepts the bus use request REQi and sends the bus use permission signal PMTi to the processor i.
send to When processor i receives this bus use permission signal PMTi, it sets flip-flop _FF2 to turn on the bus use signal and start using the bus. When the bus use is finished, the flip-flop is activated by the use end signal ENDi.
FF ₂ is reset to turn off the bus busy signal. As can be seen from FIG. 7B, if two processors i and j issue requests to use the bus at the same time,
Bus use permission signal to processor i with higher priority
Given PMTi, the processor turns on the bus busy signal and begins using the bus. Use of the bus by processor j with a lower priority is delayed until use by processor i with a higher priority is completed. This conventional parallel bus control method requires a large number of signal lines (2 x n + 1) for n processors, and due to restrictions on the number of signal lines, the number of processors per system is 3 to 4. is common, and its extension is difficult. The present invention has been made to eliminate the drawbacks of the prior art as described above, and therefore, an object of the present invention is to provide a multi-processor system with
To provide a priority control system for use of a common bus that can include a large number of processors that share a common bus, that allows easy addition and change of processors, and that has a compact bus configuration. The main point of the configuration of the present invention is that in a multi-processor system in which a plurality of processors are connected in parallel to a common bus, n bus use request lines are provided for the common bus, and r lines selected from among the n bus use request lines are provided. Assign a combination of (where n>r) to each processor,
Weighting is given to each bus request line assigned in advance to the combination, a priority is given to each processor using r combinations, and the status of the bus request lines other than those assigned is monitored to determine the priority. According to the above, the configuration is such that each processor can use a common bus. Therefore, bus usage rights can be controlled for a number of processors equal to the combination of nCr. Next, one embodiment of the present invention will be described in detail with reference to the drawings. FIG. 8 is a circuit diagram showing an embodiment of the present invention. In the same figure, the processor 2 includes a controller 21, a setting switch 22, and logic elements such as flip-flops, AND gates, and inverters. It is connected like this. The number of bus use request signal lines is ₁ to ₅ , n=5, and each processor has two bus use request lines (r=2). In this case, 5C ₂ = 10 allows up to 10 processors to be used, and setting switch 22
Priorities are set by switches S ₁ to S ₅ in . It is assumed that each of the switches _S1 to _S5 produces an "H" level output in the open state. The following table () shows the priority order according to the switch settings of _S1 to _S5 . In the example of FIG. 8, the priority is "7".

[Table] Figures 9A and 9B are basic time charts of the circuit operation in Figure 8. Figure A is when a request to use the bus occurs when the bus is in an empty state, and Figure B is when two processors simultaneously request the use of the bus. It shows when a usage request occurs. The basic operation will be explained with reference to FIGS. 8 and 9A. (1) Bus use request REQ from controller 21
Set flip-flop FF ₁ by . (2) If the bus is not in use (off), AND gate _A1 is open, so bus use request signals ₂ and ₅ are output. (3) At this time, a bus use request signal is sent from another processor.
If ₁ to ₅ are not output, the BG signal is output and flip-flop _FF2 is set. (4) By setting flip-flop FF ₂ , a bus in-use signal is turned on and output to the bus, and a bus use permission signal is sent to the controller 21.
Issue an ACK. (5) The controller starts using the bus and issues an end signal END when it finishes using it. (6) Flip-flop FF ₁ due to end signal END,
FF ₂ turns off, turns off the bus-in-use signal, and releases the bus. FIG. 10 is a circuit diagram for explaining priority control for use of a common bus by two processors each having a priority set. In the same figure, the processor 1 has switches S ₂ and S ₅ set in the setting switch 22, and the priority is 7 according to the table () above, whereas the processor 2
The switches S ₁₃ and S ₁₅ are set, and the priority is 9.
It is. Therefore, processor 1 has a higher priority than processor 2 in terms of bus usage priority. Now, processors 1 and 2 each issue a request to use the bus at the same time, so the signal RQEBL1 and
A case where RQEBL2 becomes logic "1" at the same time will be explained. At this time, ₁ : There is no output signal from all processors, and "H" (high) is output. ₂ : Processor 1 outputs “L” (low) through switch _S2 . ₃ : ₂ → switch S ₁₂ → AND circuit 16
₂ “L” comes and outputs logic “H”. ₄ : There is no output signal from all processors, and "H" is output. ₅ : Processor 1 outputs “L” through RQEBL1 → AND circuit 8 → inverter 4. BG ₁ : Output “H”. BG ₂ : Outputs “L” since ₂ is “L”. From the above, it can be seen that the signal BG1 of the processor ₁ is selected and the right to use the bus is given to the processor 1. FIG. 9B shows a time chart when bus use request signals are generated simultaneously from two processors 1 and 2, and as shown in the example of FIG. 10, only signal BG ₁ is logic. When the flag becomes "1", the use of the bus by the processor 1 ends, and the use of the bus by the processor 2 is made to wait until the bus is released by turning off the bus in use signal. FIG. 11 is a circuit diagram showing the main parts of another embodiment of the present invention, and the difference from the embodiment shown in FIG. 8 is that the priority setting switch 22 is configured as a short-circuit type instead of a switching type. This is the point. Further, the setting of the priority order can be made clear by encoding it and obtaining a fixed mark output using a decoder. Although FIG. 12 is the same diagram as FIG. 8, a very compact control circuit can be realized by using a PROM (8×256) or the like for the configuration within the broken line R. The effects of this invention are as follows. This invention makes it possible to realize a bus usage control system using a large number of processors with a small number of bus signal lines, and this bus configuration is characterized by the following characteristics of microprocessors: (1) The processing speed is slow compared to the bus usage time. This bus configuration is suitable for the following reasons: (2) it is inexpensive and can be used in large quantities; (3) it has low performance and requires processing functions in a distributed manner. Furthermore, as explained with reference to FIG. 12, by configuring the inside of the broken line portion R using PRoM (8×256) or the like, it is possible to organize the control circuit into a very compact control circuit. Also, since a fixed mark code is used to set the priority order, it is possible to check for setting errors and poor connections. Also, since the signal on the bus is a fixed mark code, it is possible to inspect the bus for defects. In the case of the PRoM configuration shown in Figure 12,
The check circuit can also be incorporated into PRoM. Further, according to the priority control method for using a common bus according to the present invention, it is not necessary to provide a common bus control circuit, so there is an advantage that it is easy to add or change processors to the system.

[Brief explanation of the drawing]

1 is a block diagram showing the configuration of a conventional serial bus control system, FIG. 2 is a circuit diagram showing a bus right control circuit in each processor in FIG. 1, and FIG. 3A is a block diagram showing the configuration of a conventional serial bus control system. Figure 3B is a timing diagram showing the timing of requests to access the bus when the bus is in an empty state. Figure 3B is a similar timing diagram when two processors issue requests to use the bus at the same time. 5 is a circuit diagram showing the circuit configuration of the bus controller in FIG. 4; FIG. 6 is a circuit diagram showing the bus usage control circuit in the processor shown in FIG. 4. , FIG. 7A is a timing diagram showing the timing of access requests to the bus when the bus is in an empty state in FIGS. 8 is a circuit diagram showing an embodiment of the present invention. FIG. Figure 9B is a timing diagram of various signals when two processors simultaneously issue bus usage requests, and Figure 10 shows priority control for common bus usage by two processors, each with its own priority set. A circuit diagram for explaining, FIG. 11 is a circuit diagram showing main parts of another embodiment of the present invention, and FIG. 12 is a circuit diagram similar to FIG. 8 for explaining realization of a compact control circuit. , is. (Explanation of symbols), 1, 2, ...i: Processor,
11: bus controller, 21: controller,
22: Setting switch.

Claims (1)

[Claims] 1. In a multi-processor system in which a plurality of processors are connected in parallel to a common bus, n bus use request lines are provided for the common bus, and a combination of r lines selected from among the n lines (however, n>r ) is assigned to each processor, weighting is given to each bus request line to give priority to each processor using r combinations, each processor monitors the status of bus use request lines other than those to which it has been assigned, A priority control method for common bus usage in a multiple processor system, characterized in that a common bus usage request is sent to an assigned bus usage request line in accordance with the priority.