JPS5836787B2 - display address generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a display address generation device for supplying an address of display data to a refresh memory in a rask scan type display.

Rask scanning type displays generally have their own timing generation system for controlling the deflection of the CRT and the display position.

Figure 1 is for explaining this, 10 is a reference clock generator, 20 is a dot counter that specifies the number of horizontal dots per character, and 30 is a column address counter that specifies the number of character slots per scanning line. , 40 is a raster address counter that defines the number of rusks (number of vertical dots) per line, and 50 is a row address counter that defines the number of rows per frame.

In a rask scan type display having such a timing generation system, the memory address for refreshing the display is introduced from the column address counter 30 and the row address counter 50, and the column and row addresses are used to input the memory address to the address converter 60. The column and row coordinate addresses are converted into continuous one-dimensional addresses, and the output thereof is provided to the refresh memory 70.

The refresh memory 70 stores the contents of the specified address (
Character code is memorized.

) and provides its output (character code signal 75) to the character generator 80.

In addition to this, the character generator 80 also includes a rask address counter 4.
A rask address 45 is given from 0, and in response to the character code input, a character pattern 85 for each rask address is output and applied to a parallel-to-serial converter 90.

The parallel-to-serial converter 90 converts the character pattern into a serial video signal 95 and supplies it to the CRT display 100, whereby the characters are displayed on the CRT display 100.

Here, the address converter 60 will be explained.

For convenience of explanation, it is assumed that the number of displayed characters per line is 80, the number of displayed lines per screen is 25, and a total of 2000 characters are displayed.

In order to express the number of display characters 80 per line, the column address signal 35 output from the column address counter 30 requires seven address lines.

(Because 26<80<27) By the way, if there are 7 address lines, it is possible to express addresses from 0 to 127,
To display 80 characters on one line, addresses 0 to 79 are sufficient, and the remaining addresses 80 to 127 are not used, so the refresh memory is wasted.

The address converter is provided to eliminate such waste, and the general formula for address conversion is as follows.

When such address conversion is performed, 2
,000 characters, O ~ as shown in Figure 2B.
The address of address 1999 can be given to the refresh memory.

By the way, the dot counter 20, column address counter 30, raster address counter 40, row address counter 50, and address converter 60 shown in FIG. It only differs depending on the type.

Therefore, if the maximum count number of these counters is made programmable, and the display characters per line are also made programmable, there is an effect that the counter group and address converter can be provided as one type of standard circuit.

In this case, it is easy for those skilled in the art to make the counter group into N-ary programmable counters.

However, in the address converter 60 that realizes the general formula A=mY+X for address conversion, the number of display characters m per line is variable, so it takes one horizontal character time (usually several hundred ns to 1μ
S) It is difficult to satisfy the following conversion time and implement it with a reasonable amount of hardware.

An object of the present invention is to refresh when the maximum counts of the column address counter 30, raster counter 40, and row address counter 50 are programmable, and the number m of display characters per line and the number n of display lines per frame are programmable. To provide an effective address generation device that gives a suitable display address to a memory according to the number of display characters.

The feature of the present invention is that the address converter 6 shown in FIG.
Instead of 0, there is one latch register that switches and holds the start address of the refresh memory in each row at each row timing, and the contents of the latch register are preset at a timing according to the programmed contents, and each row is set based on that value. The purpose is to generate the refresh memory address necessary for display using the address and an address counter that counts the address for each rask address.

Further details of the invention will become apparent from the description below.

FIG. 3 shows a typical structure of a timing generation circuit in which a column address counter 30, a rask address counter 40, a row address counter 50, the number of display characters m per line, and the number n of display lines per frame are programmable. ing.

In FIG. 3, 30 is a column address counter, and a character clock 25 is introduced into its clock input OK.

The output 35 of the counter 30 is then sent to the coincidence detectors 32, 36.
is connected to one input of the

(The lowercase 7 in the output part of the counter 30 means that there are seven output lines.

34 is a latch register that sets the number m of display characters per line, 38 is a register that sets the maximum count number of the column address counter 30, and the outputs 33 and 37 are the match detector 32, 36.

The column address counter 30 is a counter capable of synchronous clearing, and when the address count progresses and its output 35 becomes equal to the value set in the latch register 38, the output HE of the coincidence detector 36 becomes low level. Since this is connected to the CLR input of the column address counter 30, the counter 30 is cleared in synchronization with the character clock 25.

When the column address counter 30 is cleared, the signal HE returns to high level, and the column address counter 30 then continues the same counting operation.

Furthermore, when the output of the column address counter 30 matches the number m of display characters per line set in the latch register 34, the match detector 32 outputs a match signal HD, which is inverted by an inverter 39 and output as a signal HD. be done.

The output HE of the coincidence detector 36 indicates the last column address on the scan line and is applied to the clock input OK of the rask address counter 40 for counting the rask addresses.

The maximum rask address is set in the latch register 44, and this output 43 and the output 45 of the rask address counter 40 are introduced into different inputs of the match detection 42, and when the two values match, a match signal R ,B are output.

Since RE is connected to the OLR input of the Rask address counter 40, the Rask address counter 40 is reset when the next clock HE arrives, and thereafter the counting operation up to the maximum Rask address is repeated.

Furthermore, the signal RE is introduced to the clock input OK of the row address counter 50, and the inverter 49 outputs the inverted signal RE.

Next, the maximum row address per frame is set in the latch register 54, and its output 53 and the output 55 of the row address counter 50 are introduced into the coincidence detector 52, and when the two become equal, a coincidence signal ■E is output. .

The signal VB is introduced into the OLR input of the row address counter 50, which defines its maximum count number, and is also introduced into the T terminal of the flip-flop 59, so that its Q
Set the output VR to "1".

Further, the number n of display lines per frame is set in the latch register 58, and its output 57 and the output 55 of the row address counter 50 are introduced into the coincidence detector 56, and when the two values become equal, A match signal VD is output, and this signal is introduced into the reset terminal R of the flip-flop 59, resetting its Q output VR to "O".

The signal VR, is 1 counted by the row address counter 50.
This is a signal that defines the row timing used for actual display, that is, the vertical display time, among the row addresses within the frame.

Figure 4 shows the signal time chart when the maximum column address is ``127'' and the number of display characters per line is 80, and Figure 5 shows the signal time chart when the maximum rask address is ``11''. and the maximum row address in Figure 6.
31'' and a signal time chart when the number of display lines is set to ``25''.

According to the above description and drawings, the column address counter,
It will be understood that it is possible to construct a display timing system in which the rask address counter, the row address counter, the number of displayed characters per line m, and the number of displayed lines per frame n are made programmable.The present invention has been explained above. The purpose of the present invention is to provide an address generator suitable for supplying a display address to a refresh memory that stores display data in a programmable display timing generation system.The details of the present invention will be made clear in the following description. Become.

FIG. 7 shows an embodiment of the address generation device of the present invention.

In the present invention, from the display timing generation system shown in the example of FIG. 3, the character clock signal 25, the HD signal indicating the timing of the first character of the horizontal retrace time, the HE signal indicating the last column address timing, and the last rask address are indicated. B
, E signal, and VR, signal indicating the vertical display time are introduced.

In FIG. 7, the first input of AND gate 200 has VR
The RE signal is connected to the second input, the HD signal is connected to the third input, and the output is connected to the latch register 300.
is connected to the T terminal of

The VR signal is also connected to the reset terminal MR of the latch register 300.
It is connected to the.

The first input of the AND gate 250 is connected to the VR signal, the second input is connected to the character clock signal 25, and the output thereof is connected to the clock input OK of the address counter 350.

Output Q of latch register 300. -QIO is the parallel power P of the address counter 350.

-P+o, output Q of address counter 350
.

~QIO is an address signal A of a refresh memory (not shown).

- data input D of latch register 300, as well as provided as A1o.

- Connected to D+o.

Since the VB signal is connected to the MR terminal of the latch register 300, the latch register 300 is reset when VR is at a low level, that is, within the vertical retrace time, and its output Q.

-Q,. are all zero.

The reset is released when VR becomes high level, and then the final rask address R, E and HD of each line of vertical display time
And gate 200 when becomes high level
is opened and output A of address counter 350.

−A1o is preset in the latch register 300.

Here, at the timing when BE is at a high level and HD is at a high level, the output of the address counter 350 is the start address of the refresh memory where the display data of the next row is stored.

Therefore, the latch register 300 functions as a start address assignment register that switches and holds the start address of each row of display data that is continuously stored row by row at each row display timing.

The address counter 350 is a counter capable of synchronous loading, and the HE signal generated at the last column address timing for each rask is connected to its load input LD. , when the character clock 25 is introduced to the clock terminal OK, the output of the latch register 300 at that time is loaded into the address counter 350.

That is, the address counter 350 is preset with the start address of display data in units of rows for each rask address, and addresses are counted based on that value.

In this way, the latch register holds the start address for each line, the address counter presets the start address for each rask address, and the character clock controls the address counting operation, resulting in horizontal and vertical display as shown in Figure 8. A predetermined memory address necessary for display at the time is generated.

FIG. 9 shows an operation time chart of FIG. 7.

From this figure, the interrelationships of various signals in the embodiment will become clear, and the manner in which display addresses are generated by the address counter will be understood.

In FIG. 9, the signal RE is an inverted signal of the signal RE shown in the time chart of FIG. 5, and is a signal indicating the timing of the rask address 11 of FIG.

The signal HR indicates the period during which the column address (0 to 79) used for actual display among the column addresses (0 to 127) generated by the column address counter 30 is generated, that is, the horizontal display time.

This is because column addresses O to 79 explain an example of displaying 80 characters in the horizontal direction.

In the case of 100 characters, the address generation period from 0 to 99 becomes the horizontal display time.

FIG. 10 shows a typical conventional example of a character position detection method using a light pen in a Rusk scanning display.The light pen 400 has a built-in light receiving element (not shown), and the light receiving output is transmitted through a cable 405. Quantization amplifier 4
10 and its output is connected to the latch register 420,4.
The latch resistor 420 is introduced into the T terminal of 30.
, 430 are each provided with a column address counter 30.
The output 35 of the row address counter 50 and the output 55 of the row address counter 50 are connected.

Now, when the light pen 400 is directed to a specific position on the CRT display screen, a strobe signal is obtained from the quantization amplifier 410 when the electron beam by rask scanning passes directly under the light pen 400, and the column address counter at that point is 30. The contents of the line address counter 50 are set in the latch registers 420 and 430, respectively, and the character position indicated by the light pen is obtained as a coordinate address.

FIG. 11 shows one example of application of the address generator according to the present invention.

In this application example, the strobe signal of the light pen allows
The output of the address counter 350 of the address generator of the present invention is set in the latch register 440 and used as the light pen detected character position address.

In the conventional character position detection method, character position information is obtained as a coordinate address, but the applied example of the present invention is characterized in that the detection result of the light pen directly corresponds to the address of the refresh memory.

In other words, the light pen is used when the detected character position is read by a computer and a unique function program is started at that address, or when the computer reads information about one character at the detected character position or a series of characters following it. This is often done by having the person read it.

In this case, if the light pen detection result is obtained as a coordinate address as in the past, program processing is required to convert it into a refresh memory address, but with the present invention, the address of the detection result can be directly obtained. A new advantage arises in that data in the memory can be read out as an address in the refresh memory.

As is clear from the above explanation, in the address generation device according to the present invention, the timing generation system of the display is programmable, and even though the number of display characters per line and the number of display lines per frame are programmable, the system is always programmed. Since the address signal necessary for the refresh memory can be generated under the following conditions, it is extremely effective in realizing standard packaging or LSI implementation of a display timing generation system.

[Brief explanation of drawings]

Figure 1 is a block diagram for explaining the basic timing generation system of a rask scanning type CRT display, and Figure 2A.
is a diagram showing the character position address of the OR, T display screen, the second
Figure B is a diagram showing the data arrangement in the refresh memory on the display screen of Figure 2A, and Figure 3 is a diagram showing the data arrangement in the refresh memory on the display screen of Figure 2A.
A typical configuration block diagram when the timing generation system of the display is made programmable, Figures 4 to 6 are signal time charts of the timing generation system of Figure 3, and Figure 7 is a diagram of the address generation device of the present invention. A block diagram showing one embodiment, FIG. 8 is a diagram showing address generation by the address generator of the present invention, FIG. 9 is an operation time chart of FIG. 7, and FIG. 10 is a diagram of the conventional light pen position detection method. FIG. 11 is a diagram showing a typical example, and FIG. 11 is a diagram showing an embodiment of the light pen position detection method according to the present invention. Explanation of symbols, 10...Reference clock generator, 2
0...Dot count, 30...Column address counter, 40...Rask address counter, 50...Row address counter, 60...
... Address converter, 70 ... Refresh memory, 80 ... Character generator, 90 ...
... Parallel-to-serial converter, 100... CRT display, 32, 36, 42, 52, 56... Coincidence detector, 34, 3B, 44, 54, 5B... ...Latch register, 39,49...Inverter, 59.
...flipflop, 200,250...
...And gate, 300...Latch register 350...Address counter, 400...
...Light pen, 405...Cable, 410
...Quantization amplifier, 420, 430, 44
0...Latch register.

Claims (1)

[Claims] 1 In a device that generates a display address in a raster scanning type display, it is initially set during the vertical retrace time, and at times other than the initial setting, at the timing of the first character of the horizontal retrace time at the last rask address of each line. By setting the output of the address counter, the latch register switches and holds the start address of the refresh memory where display data of each row is stored for each display row, and the character clock of the last column address timing of each rask address of each row. and an address counter that presets the output of the latch register in synchronization with and counts character clocks using the preset value as a base point, and outputs the output of the address counter to the refresh memory as the display address. display address generator.