JPH0682266B2 - Display address generator - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display address generating device in a bitmap display device.

2. Description of the Related Art As a conventional display address generator, for example, HD6348
4 ACRTC (Advanced CRT Controller) User's Manual (Hitachi, June 1984).

FIG. 3 is a block diagram of a graphic system using this conventional display address generator.
Is an intelligent CRT that includes a display address generator
A controller 2 is a frame memory for storing image data to be displayed on the CRT 3, 4 is a latch circuit for latching an address, 5 is a bidirectional driver, and 6 is read data (W word) for display access to the memory. A shift register 7 for generating a video signal in synchronization with the dot clock DCLK, and a frequency divider 7.

The operation of the display address generator in the conventional graphic system configured as above will be described with reference to FIG. The figure shows a case where an mx × my area is displayed on the CRT 3 in the frame memory 2 having a width given by PCH. The display address generator generates an address which is the display start address at the display start point and generates the address after the ATR memory cycle. Where ATR, address is Address = address + W 2, where W is the number of read words, Wn is the number of bits contained in one word, and n is the ratio of the memory cycle time to DCLK.
For example, 1 word 16bit (Wn = 16), W = 2, DCLK = 64MHz,
When memory cycle = 4MHz (n = 16) ATR = 2 Address = Address + 2 Thereafter, in the same horizontal scanning, in the display section (DISP = 1), the display address is updated by +2 and generated every two memory cycles.

An address is generated at the display start point in the next horizontal scan. Here, the address is the display start address (address) of the previous horizontal scan plus the image width PCH. After that, the address generation at the display start point of each horizontal scan is obtained by adding PCH to the address at the display start point of the previous horizontal scan, and the address update at each horizontal scan is set to W at every ATR memory cycle. It will be added.

Problems to be Solved by the Invention However, in the above configuration, the frame memory 2
When using a 2-port RAM and the width (PCH) is the same as the width of the CRT display screen, the first cycle of the display section of each horizontal scan is always for display, as shown in Fig. 4. Since the CRT display screen width is the same as the capacity of one line of 2-port RAM, it can be used very efficiently. When it is different from the capacity of the minute, it causes a decrease in memory usage efficiency. In Fig. 5, one line of 2 port RAM is 1
024 bits (1 word 16 bits 64 words) The width of the display screen is 864 bits. If the memory is used efficiently, it is necessary to generate display addresses aperiodically as shown in FIG. The conventional address generator cannot generate such an address.

In view of the above problems, the present invention provides a display address generation device in which a frame memory is configured with 2-port RAM, and the frame memory can be efficiently used even when the capacity of one line of the RAM and the width of the display screen are different. With the goal.

Means for Solving the Problems The present invention provides a display including first and second registers for holding a value indicating an access interval, a discriminator for subtracting the register value, an address register and an adder. It is an address generator.

The present invention has the above-mentioned configuration, and the value of the access interval register is reduced only in the display section, and the display address is updated when it becomes "0". Therefore, the display address can be updated at a constant interval over the scanning, The display readout of is irrelevant to the width of the CRT display screen.

Practical Example FIG. 1 is a block diagram of a display address generator according to an embodiment of the present invention. In FIG. 1, 10 is an address register for storing the display start address, 1
1st and 12th are the 1st and 2nd display access intervals
A second register, 13 is an interval register that receives the output of the first register 11 at the first timing and an output of the second register 2 at the second timing, and 14 is an output of the interval register 13 as an input. , A decrementer that outputs the value subtracted by "1" as the third input of this register, 15 is a third register that stores the display address update width, and 16 is the output of the address register 10 at the first timing A display address register, 17 is an adder for adding the output of the display address register and the output of the third register, and outputs the result as the second input of the display address register, and 18 is an AND gate.

The operation of the display address generating device of this embodiment configured as described above will be described below.

The vertical sync signal VSYNC is displayed on the interval register 1 before the display starts.
3. When the first storage signal is input to the display address register 16, the contents of the first register 11 are stored in the interval register 13 and the contents of the address register 10 are stored in the display address register 16. When entering the display section, the AND gate 18 counts down the content of the interval register 13 in synchronization with CLK. If the value of the interval register is “0”, the interval register 13,
The ZERO signal is input to the display address register 16 as the second storage signal, the interval register 13 stores the second register 12, and the display address register 16 stores the output of the adder 17. Thereafter, when entering the display section, the contents of the interval register 13 are counted down in synchronization with CLK and the above operation is repeated until the next vertical synchronizing signal is input.

As described above, according to this embodiment, it has the first and second registers 11 and 12 for storing the first and second display access intervals, counts down the access interval register only in the display section, and sets "0". "By updating the contents of the display address register every time, it is possible to access the display at regular intervals even when scanning is continued.

Further, by having the first register 11 independently of the second register 12, scrolling in the vertical direction becomes possible. In Fig. 2, the first register "10" and the second register "6"
4 "and display address generation when" 54 "is set in the address register.

As described above, according to the present invention, even when the 2-port memory is used as a frame memory, the memory can be effectively used regardless of the width of the CRT display screen, and the practical effect is large.

[Brief description of drawings]

FIG. 1 is a block diagram of a display address generator in one embodiment of the present invention, FIG. 2 is an operation diagram of the same embodiment, and FIG. 3 is a block diagram of a graphic system using a conventional display address generator. 4 and 5 are operation diagrams of the conventional display address generator. 10 ... Address register, 11 ... First register, 12 ...
... 2nd register, 13 ... interval register, 14 ... decrementer, 15 ... 3rd register, 16 ... display address register, 17 ... adder, 18 ... AND gate.

Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location G09G 5/36 G 9177-5G

Claims (1)

[Claims] 1. A first register for holding a display start address, a second register for holding an update width of a display address, and a third register for making an output of the first register a first input.
Register, an adder that adds the output of the second register and the output of the third register and uses the result as the second input to the third register, and a first display access interval indicating the first display access interval. A fourth register, a fifth register indicating the second display access interval, and an output of the fourth register as a first input, and an output of the fifth register as a second input. A register and a value obtained by subtracting the output of the sixth register as an input is output as a third input to the sixth register, and when the output becomes "0", the third and sixth registers are output. A decrementer for generating two input control signals, and a first for the third and sixth registers.
A display address generating device characterized in that a vertical synchronizing signal is used as an input control signal of the above, and a signal indicating a display section is used as a third input control signal for the sixth register.