JPS5837640B2 - Disconnection compensation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for detecting erroneous information caused by malfunction of transistors when a wiring for commonly supplying the output voltage of a drive circuit to a plurality of transistors is disconnected in a storage device or the like. This paper relates to a disconnection compensation method for separating positive information.

FIG. 1 shows an example in which a plurality of transistors are commonly driven by a drive circuit, and shows an example of a device configured with MOS field effect transistors formed on a P-type semiconductor substrate, for example.

In the figure, transistors 1 and 2 constitute a drive circuit, a common 1 drive wiring 8 is connected to the output terminal γ, and the gates of transistors 31, 3...3k are connected to this wiring 8. There is.

In such a configuration, when the input terminal 6 is at a high voltage, the transistor 2 is in a conductive state and the output terminal 7 of the drive circuit is in a conductive state.
Therefore, the common 1 drive wiring 8 is at zero voltage, and the transistors 3 to 3k are all in a cut-off state.

When the voltage at the input terminal 6 changes from a high voltage to zero voltage, the transistor 2 is cut off, the voltage at the wiring 8 becomes a high voltage, and the transistors 31 to 3k become conductive.

The transistors 31 to 3k function as switches that transmit information input to the terminals 4 to 4k to the terminals 51 to 5k.

In the conduction state of ~3k, terminal 41 is connected to terminal 5 ~5k.
~4k information is output.

Devices having these structures are frequently used in semiconductor integrated circuits.

For example, a constant speed read/write storage device (hereinafter referred to as R
In an AM type storage device), what is stored in terminals 4 to 4k? The information (stored in capacitors (not shown) connected to terminals 4 to 4k) is transferred to terminal 5, which functions as a word line and is controlled by the information on wiring 8 and connected to the bit line.
Output to 1 to 5k.

In addition, in a read-only memory device (hereinafter referred to as a ROM type memory device), the threshold voltages of the transistors 3 to 3k are changed in advance in accordance with "1" and "O" information, and the terminal 4
~4k is set to zero voltage.

When a voltage is applied to the word line 8, only the transistor with a low threshold voltage becomes conductive, and the corresponding bit line becomes zero voltage, but the transistor with a high threshold voltage remains cut off, and the bit line becomes conductive. Keep high voltage.

In this way, the difference in threshold voltages can be read out as "1" and "0" information.

In such a configuration, as the number of commonly driven transistors increases, the total length of the wiring 8 becomes very long.

When this is processed and formed using, for example, semiconductor integrated circuit manufacturing technology, disconnections often occur.

As an example of a situation that occurs when a wire breaks, it is assumed that a wire break as shown by 9 occurs between transistors 31-1 and 31 in FIG.

Since the transistors 3 to 31-1 are connected to the drive circuit through wiring 8, they perform normal switching operations in response to voltage changes at the input terminal 6, and transmit positive information to the terminals 5 to 51-1.
Output to.

However, the gates of transistors 31 to 3k are connected to wiring 8 and S
It becomes electrically floating from the output of the drive circuit,
It is not determined by a constant voltage state.

That is, not only do the transistors 31 to 3k not switch in response to the information at the input terminal 6, but it is also uncertain whether the transistors will be in a cut-off or conduction state, and the terminals 51 to 3k
The information appearing in 5k is completely unreliable.

On the other hand, there is a conventional method of separating a defective part caused by a disconnection and using only the good part that outputs correct information.

In that case, the output of the defective part is required to be always low voltage or always high voltage.

For example, information X・(j=1
, 2, ..., k) and another information Y. (j=1,
2, ..., k) and the logical sum X. When taking J + Yj, the terminals 51 to 51 connected to the disconnected part
If it is assumed that zero voltage is always outputted to 5k as a voltage corresponding to the logic "O jj", the information after calculating the logical sum is Y.

In other words, was the information from the disconnection part ignored and separated from the real information? Become.

Similarly, when taking the logical embeddings Xj and Yj of information
If the voltage is high enough to correspond to 1 H, the information after the logical loading is Y
j, and this also means that the information from the disconnection part has been separated.

Such a method is a very effective means for improving reliability by duplicating devices, etc.

However, in the conventional device as shown in FIG. 1, the wire breakage is electrically floating, making it difficult to maintain a constant voltage.

Even if the voltage is constant, it is completely impossible to predict whether the desired information as described above will always be output.

Therefore, in such a circuit, erroneous information caused by a disconnection cannot be isolated, and when a disconnection occurs, the entire circuit must be discarded as defective, even if some parts are operating correctly.

In order to eliminate these drawbacks, the present invention provides a circuit that sets the voltage of the disconnected portion to a desired voltage when a portion of the wiring that commonly supplies the output voltage of the drive circuit to a plurality of transistors is disconnected. This makes it possible to convert and output the erroneous information output from the disconnected transistor into a state most convenient for separating it from the correct information.
This facilitates error correction by duplicating circuit blocks such as memory.

A detailed explanation will be given below with reference to the drawings.

FIG. 2 shows an example of the basic structure of the present invention, in which an R transistor consisting of a MOS field effect transistor formed on a P type semiconductor substrate is shown.
An example applied to an OM type storage device will be shown.

Similarly to FIG. 1, a common seven drive wiring 8 is connected to one drive circuit made up of transistors 1 and 2, and the gates of a plurality of transistors 10 to 10k are connected to this.

Transistors 10 to 10k contain information written during manufacturing.
This is a memory cell transistor having two types of threshold voltages corresponding to 1" and "O n.

In FIG. 2 and other figures as well, the transistors marked with * are depletion type transistors with negative threshold voltages, and the others are enhancement type transistors with positive threshold voltages.

The transistors 111 to 11k are transistors that charge the output terminals 12 to 12k to a high voltage in advance before reading information, and are driven by the input voltage from the common gate wiring terminal 13, and are driven by the voltage input from the DC power supply wiring 14 to the output terminals 12 to 12k. ,~? Charge 2k.

Reference numeral 15 denotes a disconnection compensation transistor, which is a feature of the present invention, and is connected to the other end of the common drive wiring 8, and in this example, a depression type transistor is used.

Figure 3 shows the voltage waveform of the part indicated by a"e in Figure 2,
a is the input voltage applied to the input terminal 6, b is the output voltage of the drive circuit, and C is the input voltage to the gate wiring terminal 13.

d is the output voltage of terminal 12 when the transistor of the memory cell is an enhancement type transistor, which is a typical output voltage of terminal 12, and e is the output voltage of terminal 12 when the transistor of the memory cell is a depletion type transistor, which is a typical output voltage of terminal 12. The output voltage of terminal 121 is shown in FIG.

If there is no disconnection 9 and the wiring 8 is connected, all transistors 10 to 10k operate normally.

That is, from the time the voltage C drops until the input voltage a falls, the output voltage d or e is outputted to the terminals 121 to 12k according to the threshold voltages of the transistors 10 to 10k.

At this time, transistor 15 is transistor 1 of the drive circuit.
, 2 shall have a size that does not affect the operations of .

For example, if the ratios of channel length and channel width of transistors 1 and 2 are 1 and 2, the ratio of transistor 15 may be approximately 0.01.

The operation of the example shown in FIG. 2 will be explained with reference to FIG.

When the voltage a at the input terminal 6 of the drive circuit becomes a high voltage, the gate voltage b of the transistors 101 to 10k of the memory cells becomes zero voltage.

At this time, the depletion type transistors marked with an * are in a conductive state, and the enhancement type transistors are in a cutoff state.

When the voltage C at the terminal 13 becomes a high voltage, the voltage e at the output terminal 12 connected to the depletion type transistor hardly increases, but the voltage d at the output terminal connected to the enhancement type transistor is charged and becomes a high voltage.

When the voltage C falls, the connected output terminal of the depletion mode transistor becomes zero voltage, but the connected output terminal of the enhancement mode transistor becomes the input voltage a.
The positive information is held for a time T until it falls.

If there is no break in the wire 8, voltage b is applied to the gates of all the transistors 10 to 10k, but as shown in FIG.

If the wire is divided into two, then the wiring 82 after the transistor 10i where the disconnection 9 has occurred? Voltage b is not supplied.

However, a transistor 15 is connected to the other end of the wiring 8, so that even if the disconnection 9 occurs, the wiring 8 does not float as in the conventional case, and is always maintained at a high voltage due to the conduction of the transistor 15.

Therefore, the transistors 10i to 10k after the disconnection 9 are always in a conductive state, and their output terminals 12i to 12k always output zero voltage.

On the other hand, the output terminals 12, ~12i, on the wiring 81 side
A zero or positive voltage is normally output depending on the form of the transistors 101 to 10i.

As mentioned above, this is convenient for isolating erroneous information due to disconnection, and can be better understood by referring to FIG.

FIG. 4 shows an embodiment of the present invention, in which the ROM type storage device shown in FIG. 2 is applied to a dual ROM type storage device.

Transistors 301 and 31, 302 and 31, . . . corresponding to two memory devices having the same configuration as in FIG. 2, respectively.
, 30k and 31k are written with the same "1" and "0" information depending on the change in threshold voltage.

There is no disconnection in one of the common drive wiring lines.

Outputs 32 and 331 of both storage devices, 32 and 332,...
..., the information of 32k and 33k are respectively Xj and Yj
(j=1, 2, . . . , k) and input them to a circuit for calculating the logical sum consisting of transistors 34, 35, and 36.

If the output of the logical sum circuit is Zj, then Zj = Xj + Y
becomes j.

In Fig. 4, outputs 321 to 32k and outputs 331 to
33i-, outputs positive information, but outputs 33i to 33k
always outputs zero voltage (“0” information) due to the disconnection 9.

That is, in the above logical sum expression, j-1, 2,...
・, for i-1, Xj=Yj and Zj =Xj+Yj=Xj
=Yj, and j=i, i+1, ..., k TehaYj = 0TeZj =X・+o=xT.

That is, output 33.~33kJ J
The error of outputting information "0" when information "1'" should be outputted is ignored, and only the correct information outputted from outputs 32i to 32k is outputted to outputs 37i to 37k.

There is no transistor 15 as in the conventional case, but transistor 3
When the gates of 1i to 31k are at zero voltage, 33i to 33
Information that should originally be “0′” becomes “l” in k, and 3
The normal information of 2i to 32k is destroyed, and the outputs 37i to 37k all become information "1".

FIG. 5 shows another example of the basic configuration of the present invention. This is an example in which the present invention is applied to a RAM type memory device consisting of a MOS field effect transistor formed on a conductor substrate.

The enhancement type transistors 401 to 40k store information in the storage capacitors 411 to 41k, that is, information about whether or not the capacitors are charged.
It plays the role of a switch that transmits this to the output terminals 421 to 42k.

The depression type transistor 43 is a transistor that fixes the floating wiring 8 caused by the disconnection 9 to zero voltage, and has the same size as the transistor 5 in FIG. 2.

The operation will be explained using a timing chart of voltage waveforms at each terminal shown in FIG.

f is the input voltage applied to the input terminal 6, g is the output voltage of the drive circuit consisting of transistors 2, that is, the voltage to be applied to the wiring 8 and the gates of the transistors 40 to 40k, and h is the voltage applied to the output terminals 42 to 42k. This voltage is applied to the transistors 11 to 11k in order to charge them to a high voltage in advance.

First, when the soldering pressure h becomes high voltage, the output terminals 42 to 4
2k is all high voltage.

When the voltage h becomes zero voltage and the input voltage f falls, the driving wiring 8, which is originally one, becomes a high voltage, and the information stored in the capacitor is output.

The capacitor is charged with a negative charge in response to "0" information, and is not charged in response to "1" information.

Therefore, if “0” information is stored in the capacitor,
The voltage of the output terminal, which was previously charged to a high voltage, decreases from its initial value.

This situation is shown as a voltage drop V in voltage I.

Typically, this voltage drop is then further amplified and reduced to zero voltage.

The "011" information that has become zero voltage is held for a time T until the voltage h rises again.

If the capacitor is not charged, the voltage at the output terminal that was previously charged to a high voltage remains at its initial value.

This state is shown by voltage m.

In FIG. 5, when the wiring 8 is divided into two by the disconnection 9,
The wiring 8 and the gates of the transistors 40i to 40k are fixed at zero voltage by the action of the transistor 43.

Therefore, the transistors 40i to 40k are always cut off, and a high voltage, ie, n 1 tt information, is always output to the output terminals 42 to 42kl.

As mentioned above, this is suitable for isolating erroneous information due to disconnection.

FIG. 7 shows another embodiment of the present invention. This is an example in which an AM type storage device is applied to a RAM type storage device with duplication.

Two storage devices having the same configuration as in FIG. 5 are used, and storage capacitors 60 and 61, 60 are used.

The same information is written in 612, . . . , 60k and 61k.

Let the information of outputs 621 to 62k and 63 to 63k of both storage devices be Xj and Yj, respectively (j-1, 2,...
..., k), and connect them to transistors 64, 65, 66
It is input to a circuit that takes a logical product consisting of .

If the information of the outputs 67 to 67k of the logic embedded circuit is Zj, then Z
j=Xj−Yj.

In Fig. 7, outputs 62 to 62k, 631 to 631
-1 outputs positive information, but the outputs 63i to 63k always output high voltage due to disconnection 9, that is, "1" information.

That is, in the logical formula, j-1, 2,...
For i-1, Xj = Yj and Zj = Xj - Yj
=Xj 1Y-tona'), j=i, i+1--, k-
(- is Yj=J 2, and Zj=Xj ・1=Xj.

In other words, the error of outputting information "1" when information "0" should be output in the outputs 63i to 63k is ignored,
Only the positive information output from outputs 62i to 62k is output 6.
7i.

There is no transistor 43 as in the conventional case, but a wiring 8.

When the capacitor 61i is electrically floating in a high voltage state, the capacitor 61i
Incorrect information is written to ~61k.

For example, if information "0" is written when information "1'" should be written, that information will remain in L63i to 63k.
According to the logical formula, the correct side output 62
Destroy information from i to 62k.

That is, 67i to 67k are all information n 1 ? It becomes 1.

Note that 68 is a circuit for amplifying the outputs of both devices and reducing the "011 information to zero voltage."

Although the above two embodiments are examples in which the present invention is applied to a memory device formed of a semiconductor integrated circuit, the present invention is not limited to this. This method can be applied to all cases where two transistors are commonly driven by a long wiring.

Furthermore, the voltage for electrically fixing the wiring that is floating due to the disconnection is determined by the method used to separate the false information output from the disconnection from the correct information.

Therefore, the voltage at the disconnection portion is not limited to high voltage or zero voltage as shown in the above embodiments.

In addition, the method of setting the voltage at the wiring break point is not limited to the circuit consisting of one transistor as shown in the above embodiment. It is possible to use a circuit that connects a power source and wiring via a capacitor or a capacitor.

Further, in the above embodiment, the wiring is one without branching, but it may be branched.

In that case, the voltage setting circuit may be provided at each end of the branch wiring.

Furthermore, if the wiring length is very long, a plurality of the voltage setting circuits may be installed in a distributed manner so that floating portions of the wiring do not occur even in the event of disconnection at two or more locations.

As explained above, the present invention is most effective for relieving erroneous information especially when devices are multiplexed.

In this case, if even one piece of information out of a plurality of equivalent output information from each multiplexed device is correct, it can be extracted as correct information for the entire device.

As described above, the present invention can automatically and minimize the spread of defects in the circuit due to a disconnection to other circuits, and therefore has the effect of facilitating separation of information from the disconnection or repair.

Applying repair techniques to tolerate disconnection improves the manufacturing yield of the device, which in turn contributes to lowering the cost of the device.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing a conventional example, Fig. 2 is a circuit diagram showing an example of the basic configuration of the present invention, Fig. 3 is a waveform diagram explaining Fig. 2,
FIG. 4 is a circuit diagram showing an embodiment of the present invention when FIG. 2 is used, FIG. 5 is a circuit diagram showing another basic configuration example of the present invention,
FIG. 6 is a waveform diagram explaining FIG. 5, and FIG. 7 is a circuit diagram showing another embodiment of the present invention in which FIG. 5 is used. 1 and 2...Transistors forming the drive circuit, 101 to 10k...1 Transistors commonly driven by the drive circuit, 8...Common 1
Driving wiring, 15...Transistor that makes the disconnected floating part high voltage.

Claims (1)

[Claims] 1 At least two sets of similar circuit blocks having a drive circuit, a plurality of transistors, and wiring for commonly driving the plurality of transistors by the drive circuit, and inputting the outputs of opposing transistors of each circuit block, respectively. In a device comprising a plurality of logic circuits that prohibit false information among them and output only normal information, the output voltage of the drive circuit in each circuit block is commonly supplied to the plurality of transistors. Of the wiring? A voltage setting circuit that is operationally independent from the drive circuit is connected to the end, and when the wire beyond the disconnection point floats from the drive circuit due to a break in the wire, the output of the transistor in the floating portion is connected to the drive circuit. A logic circuit which is fixed at a predetermined voltage value by a voltage setting circuit and whose input is the output of the transistor is:
A disconnection compensation method characterized in that the fixed output is regarded as false information and is prohibited.