JPS5840196B2 - Waveform signal generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an envelope waveform signal generator used for controlling musical tones of electronic musical instruments, for example.

2. Description of the Related Art Among electronic musical instruments, synthesizers that form musical tones through voltage signal control are known.

These electronic musical instruments attempt to express performance sounds that are more natural and musical by controlling pitch, timbre, volume, etc. using envelope waveform signals generated in response to key operations. It is something.

FIG. 1 shows an example of the basic configuration of such an electronic musical instrument, in which a keyboard circuit 11 generates a voltage pitch signal corresponding to the pitch of the operated key, as well as key press (key on) and release. Generates a keying signal corresponding to the key (key off).

The pitch signal from the keyboard circuit 11 is supplied to a VCO 12 (voltage controlled variable frequency oscillator), and this VCO 12 is controlled to oscillate a sound source signal with a frequency corresponding to the pitch of the operated key. The obtained sound source signal is V
A tone is formed using a CF 13 (voltage controlled variable filter) to produce a musical tone signal.

The musical tone signal obtained from the VCF 13 is then
After setting the amplitude envelope with A14 (voltage controlled variable gain amplifier) and appropriately amplifying it with the amplifier 15, the speaker 16
to generate a performance sound.

Mata, the above VCO12, VCFl 3. For each VCA14, an envelope generation circuit 17°18.1
The envelope waveform signal generated in step 9 is supplied as a control signal.

This envelope waveform signal is generated from the initial level (I
attack level (AL) from attack time (AT)
), and thereafter the 1st decay time (IDT
) to the sustain level (SL) and maintain this sustain level (SL).
The initial level (I
It is the one that attenuates up to L).

In order to obtain such a waveform signal, the keyboard circuit 11 is connected to each of the envelope generating circuits 17 to 19.
IL, AT, and AL for combining keying signals from the control circuit 20 and shaping the envelope waveform from the control circuit 20.
, IDT, SL, 2DT, and other condition signals.

That is, from the envelope generation circuits 17 to 19, the VC
By supplying envelope waveform signals such as those described above as control signals to each of Ol 2 , VCFI 3 , and VCAl 4, the performance sound pitch, timbre, and volume are modulated, and performance sound expression is made effective. It is.

FIG. 3 shows an example of an envelope waveform generating circuit used as described above, with input terminals 21a, 21
b, 21c are the level conditions that form the above waveform = AL,
Voltage signal VAL 2VSLtVI that rains SL and IL
A voltage signal vA is coupled to input terminals 22a, 22b, and 22c to apply time conditions AT, IDT, and 2DT.
T, VIDT.

Combine V2DT.

These voltage signals are each set by a voltage dividing circuit using a variable resistor or the like in the control circuit 20.

The voltage signals coupled to each of the input terminals 21a to 21c are sent to switch circuits 23a to 23c each formed of an FET.
and is coupled to a storage capacitor 25 via a voltage-controlled variable resistance circuit 24.

Further, voltage signals from the terminals 22a to 22c are also combined together via switch circuits 26a to 26c each made of FET, and are supplied to the variable resistance circuit 24 as a resistance value setting control signal.

Then, the terminal potential of the capacitor 25 is read via the high input impedance buffer 27 and used as a waveform output signal.

Then, the output voltage signal from the high input impedance buffer 27 and the signal voltage VAL from the input terminal 21a
A comparator 28 compares the output voltage of the high input impedance buffer 27 with VAL, and sets the flip-flop circuit 29 when the output voltage of the high input impedance buffer 27 exceeds VAL.

The keying signal from the keyboard circuit 11 is expressed as a logic "1" when the key is released and a logic "O" when the key is pressed.
This keying signal is coupled to inverter 30 and switch circuit 23c.

26c as a closing command signal.

Further, the output signal of the inverter 30 (together with the reset output signal of the flip-flop circuit 29) is coupled to the AND circuit 31, and the output signal of the AND circuit 31 is supplied to the switch circuits 23a and 26a as a closing command signal, and the keying signal and The output signal of the NOR circuit 32 to which the output signal of the AND circuit 31 is combined is connected to the switch circuits 23b and 2.
It is used as a closing command signal for 6b.

Then, a signal from the capacitor 33 with a keying signal and a logic "1" signal added to both poles is applied to the inverter 34, and an output "1" is sent to the inverter 34 when the keying signal changes from "1" to "0" when the key is on. This causes the flip-flop circuit 29 to be reset.

That is, in the steady state when no key is pressed, the keying signal is "1", so the switch circuits 23c and 26
c is applied, and the terminal potential of the capacitor 25 is maintained at the initial level potential VIL.

Then, in this state, the key is pressed and the keying signal is 10.
, the flip-flop circuit 29 is reset, and the switch circuit 23 is reset by the output of the AND circuit 31.
a, 26a is closed, and the voltage signal VA is applied to the variable resistance circuit 24.
L is combined.

The resistance value of this resistance circuit 24 is set by the voltage signal VAT, and the capacitor 25 is set at a time constant corresponding to VAT.
Charged to L.

When the terminal potential of the capacitor 25 reaches VAL, an output signal is generated from the comparator 28, and the flip-flop circuit 29 is set.

Therefore, since the output of the AND circuit 31 is null and the keying signal is "0", the output signal from the NOR circuit 32 turns on the switch circuits 23b and 26b.

That is, the input voltage of the variable resistance circuit 240 becomes VSL, the control voltage v1DT, and the capacitor V□D
It changes to VSL with a time constant determined by T, and maintains that state while the key is pressed thereafter.

Then, when the key is released and the keying signal becomes "1",
The switch circuits 23c and 26c are turned on, the input terminal voltage of the variable resistance circuit 24 becomes VIL, and the control voltage becomes V
2DT, and the terminal potential of the capacitor 25 becomes V2DT.
It is possible to change up to VIL with a time constant determined by .

Then, an envelope waveform signal as shown in FIG. 2 is read out and output as a change in the terminal potential of the capacitor 25.

Note that the power supply E connected to the negative terminal of the comparator 28 is a security power supply.

That is, since it takes an infinite amount of time for the charging voltage of the capacitor 25 to reach VAL, the comparator 28 theoretically does not operate forever.

Therefore, by connecting the security power supply E, capacitor 2
The comparator 28 is configured to operate when the charging voltage of No. 5 reaches vAL-E.

However, such an envelope waveform signal has a rising and falling edge of 1 when a key is pressed and a key is released.
Only the step change state is set, and it is not possible to determine the waveform change especially when the key is continuously pressed.

In other words, the envelope waveform is relatively unchanging, making it difficult, for example, to make the musical tone control more variable and to broaden the expressive power.

The present invention has been made in view of the above points, and provides a waveform signal generator that enables the envelope waveform to be variably set in more stages, thereby making it possible to issue a more varied control command. The purpose of this invention is to provide reliable setting control of waveform rising and falling modes.

That is, in the waveform signal generator according to the present invention, a plurality of level setting voltage signals are set, and the voltage signals are taken out through each of the plurality of switch circuits and sent to the voltage storage element through the time constant circuit. The above-mentioned switch circuit performs switching control using a counter in order of priority.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 4 shows the configuration of a waveform signal generator according to the present invention, and input terminals 41a, 41b, .
...VLn is combined.

This voltage signal sets the ascending step of the envelope waveform in order, and is VLo, vLo,...
. . . the potential becomes higher in sequence, and is taken out from a voltage setting circuit such as a voltage divider circuit (not shown).

Also, the input terminal 41a under this level condition? 4 l
In addition to b...input terminal 42a for time conditions.
, 42b... are provided, and this input terminal 4
2 a, 42 b..., the time condition voltage signal ■T1 when the waveform rises. vT2.・－・・・・vTn
combine.

The above input terminals 41a, 41b... and 42a
.

The voltage signals from 42b...... are sent to each FET.
A switch circuit 43 a t 43 b...
... and 44at44b..., and are coupled to the switch circuits 43a, 43b-...
The output signals from ... are collectively supplied to the variable resistance circuit 24.

The resistance value of the variable resistance circuit 24 is set and controlled by a voltage signal taken out via the switch circuits 44a, 44b, . . . .

The voltage signal taken out from this variable resistance circuit 24 is coupled to a storage capacitor 25, and the terminal potential of this capacitor 25 is read as an output waveform signal via a high input impedance buffer 27.

The input voltage signal to the variable resistance circuit 24 and the read voltage signal from the high input impedance buffer 27 are compared by a comparator 45.

Here, E is a power supply for compensation.

The comparator 45 generates an output signal when the read voltage reaches the input voltage to the variable resistance circuit 24, that is, when the terminal potential of the capacitor 25 reaches the input command voltage, and causes the counter 46 to count steps. advance.

This counter 46 includes, for example, switch circuits 43 a , 43 b , . . . to which level designating voltage signals are coupled.
It is configured so that each can be specified, and when the keying signal rises with the key press, the differential output is used to reset and initialize the count value, and the decoder 47 detects the count value. As the counting progresses, the switch circuits 43a, 43b, . . . are sequentially switched on and on.

At the same time, switch circuits 44a, 44b...
. . . are also controlled in parallel.

That is, in the above device, when the keying signal is combined, the counter 46 is set to the initial state, and the output signal from the decoder 47 causes the switch circuit 43a to be set to the initial state.
, 44a are input.

Therefore, the voltage signal VT1 is transmitted through the variable resistance circuit 24.
The terminal potential of the capacitor 25 is set to the voltage VLO with the time constant set by .

In this case, since this is the initial state when the key is turned on, VLo is set in as short a time as possible.

Then, when the terminal potential of the capacitor 25 becomes VLO,
An output signal is obtained from the comparator 45, the counter 46 is incremented by one, and the decoder 47 outputs the output signal to the switch circuit 43b,
44b is switched on.

That is, the input voltage of the variable resistance circuit 240 is VLI, the resistance value of which is set by vT2, and the terminal potential of the capacitor 25 is VLt with a time constant proportional to VT2.
When VLt is reached, the counter 46 is again incremented by the output of the comparator 45.

That is, voltage signals vLo, VLl, .
The terminal potential of the capacitor 25 changes according to a time constant determined by .

Therefore, the output envelope waveform signal becomes as shown in FIG. 5, for example, and the level is set to rise in multiple stages after the key is turned on, so that a varied envelope waveform can be set as appropriate.

Here, in the above description, only the rising mode of the waveform was shown, but in the case of the falling mode, the input terminal of the comparator 45 may be reversed.

In the above embodiment, only the waveform of either the rising mode or the falling mode is controlled depending on the input setting state of the comparator 450, but if the waveform is configured as shown in FIG. 6, both the rising and falling modes can be combined as appropriate. The waveform can also be set arbitrarily.

That is, in this embodiment, in addition to the switch circuits 43a, 43b, . . . of the previous embodiment, the input terminal 41
Further switch circuit 4 for bs41c...
3b', 43c', .

That is, the voltage signals from the switch circuits 43a, 43b, .
The output voltage signal from the buffer 48b is supplied to the variable resistance circuit 24 as the subsequent stage information 1□.

Further, the output signals of the buffers 48a and 48b are compared by a first comparator 49 to determine whether the mode is rising or falling. For example, in the rising mode where 11<12, the output of the comparator 49 is "0". , conversely, in the falling mode of 11>12, a comparison output of "1" is generated.

Furthermore, the output potential of the buffers 48a and 48b is set to a resistor R.
1, voltage is divided by R2, and a buffer 48 is created between 11 and 12.
A potential sufficiently close to 12 on the b side is detected and compared with the output read voltage of the high input impedance buffer 27 by the second comparator 50.

The comparator 50 outputs "1" and "2" when the read voltage exceeds the divided voltage, and "0" and "0" when the read voltage exceeds the divided voltage.
” output signal is generated.

The output signal from the second comparator 50 is coupled with the output of the first comparator 49 to an exclusive OR circuit 51 via an integrating circuit that absorbs pulses when the FET switch circuit is switched. The output of the sum circuit 51 is used to increment the counter 46.

That is, in this device, the terminal potential of the capacitor 25 is
It is always set to ■Lo, and when a keying signal is input in this state, the counter 46 is reset,
The switch circuit 43at43b' is turned on by the output of the decoder 4T, and the voltage signals VI, o are supplied to the buffers 48a and 48b.
, VL, is coming.

Then, the first comparator 49 compares the two.

Here, if VLo<vLl, the output of the first comparator 49 is "0", and the voltage signal VT from the switch circuit 44a that is simultaneously turned on at this time via the variable resistance circuit 24
The capacitor 25 changes from VCo to VLt with a time constant determined by □.
is charged towards.

When the terminal potential of the capacitor 25 becomes sufficiently close to VLI, the output of the second comparator 50 is inverted to "1", and a signal is generated from the exclusive OR circuit 51 to set the counter 46 to 1.
You will be able to make one step forward.

In addition, in the above case, when VL O > VL 1, the first
The output of the comparator 49 becomes "1", and the output of the second comparator 50 becomes "1".
When the output of the counter 46 is inverted to "0", the counter 46 is incremented.

That is, regardless of whether the waveform change step is in the rising mode or the falling mode, the counter 46 is incremented in a state in which the output signal voltage reaches the target potential of that step, and the process proceeds to the next step. For example, it is possible to generate and control a free envelope waveform signal as shown in FIG.

In the above explanation, only the setting of the envelope waveform from the time of key-on has been explained, but when this waveform signal generator is used in an electronic musical instrument as shown in FIG. 1, it is also necessary to set the waveform from the time of key-off.

In such a case, as shown in FIG. 8, two sets of waveform signal generators 52a and 52b as shown in FIGS. 4 and 6 are prepared, and a keying signal that changes between "1" and "0" One of them is selected by controlling gates 53a and 53b.

Then, if the rising and falling edges of the keying signal are detected by the differentiating circuits 54a and 54b, respectively, and coupled to the waveform signal generators 52a and 52b as a reset command, an envelope waveform signal corresponding to the key operation state can be set arbitrarily. It is something that will be done.

As described above, according to the present invention, it is highly arbitrary,
In addition, it provides a waveform signal generator that can set multi-stage variable steps, and when used, for example, to control the musical tone of an electronic musical instrument, the expression of the performance sound can be expressed with sufficient variation, and it can greatly improve the performance effect. It can be very effective.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining an electronic musical instrument related to the present invention, FIG. 2 is a diagram showing an example of a waveform signal used in the electronic musical instrument, FIG. 3 is a diagram showing a means for generating the waveform signal, and FIG. 5 is a diagram illustrating an example of a waveform generated by the above device, FIG. 6 is a diagram illustrating another embodiment of this invention, and FIG. FIG. 8 is a diagram showing examples of waveforms generated in the embodiment, and FIG. 8 is a diagram showing an example of means for using the above device for controlling an electronic sound collector. 24... Variable resistance circuit, 25... Storage capacitor, 27... High input impedance buffer, 43a, 43b...-, 44a, 4
4b...Switch circuit, 45, 49, 50...
...Comparator, 46...--Counter, 47--
...Decoder, 48 a p 48 b...
-Buffer, 51...Exclusive OR circuit.

Claims (1)

[Claims] 1. A plurality of switch circuits to which a plurality of set voltage signals are respectively coupled, and voltage signals taken out from the switch circuits are commonly coupled and charge/discharge is controlled with a set time constant to generate a terminal potential. a voltage storage element that reads the voltage as an output signal; a comparator that compares the voltage stored in the voltage storage element with the input side voltage from the switch circuit; and a counter that is incremented by the comparator output signal. Equipped with
A waveform signal generating device characterized in that the plurality of switch circuits are sequentially switched on and controlled in accordance with the counted value of the counter. 2 A plurality of switch circuits to which a plurality of set voltage signals are respectively coupled, and voltage signals taken out from the switch circuits are commonly coupled, charge and discharge are controlled with a set time constant, and the terminal potential is read as an output signal. A voltage storage element, a counter that sequentially switches on and off the plurality of switch circuits, and a voltage signal from the switch circuit that is switched on and off in accordance with the count value of this counter is compared with a voltage signal from the previous switch circuit. The device includes means for determining whether the mode is rising or falling, and comparing means for comparing the memory element terminal potential and its input side potential in accordance with the discrimination mode of this means, and the output signal from the comparing means determines the A waveform signal generator characterized by incrementing a counter.