JPS5840348B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device having a plated heat sink.

Generally, plated heat sinks are used as effective heat dissipation electrodes in semiconductor microwave oscillation devices, such as in-bat diodes and Gunn diodes.

The conventional Gunn diode with plated sheet sink is shown in a perspective view in FIG.

In this figure, 1 is an n+ GaAs substrate with a carrier concentration of 1×10 CrrL, and 2 is a carrier concentration of 2×10 cm.
nGaAs working layer, 3 has a carrier concentration of 8×10
n++GaAs ohmic layer of crIL,
4 is a plated heat sink, 5 is an upper electrode,
The dimensions of this Gunn diode are from the upper electrode 5 to n++Ga
Thickness t to As ohmic layer 3 = 10 to 30 μm1
The proportion of the content layer is as follows.

That is, the n+GaAs substrate 1 has a thickness of 10 to 20 μm r
The n-GaAs' operating layer 2 is 2-20 μm, n++Ga
The AS ohmic layer 3 has a thickness of 1 to 3 μm.

Also, the size of the plated heat sink 4 is width W.
= 300 to 500 μm, thickness T = 150 to 250 μm, and made of gold, silver, copper, etc.

1 to 4 show the manufacturing process of a conventional Gunn diode with a plated heat sink, in which a silver (Ag ) to 150-200μm by electrolytic plating method.
After forming the plated heat sink 4 by adhering the above, the plated heat sink 4 is used as a protection plate.
GaAs substrate 1 is ground to a desired thickness.

For example, when creating a diode for 10GHz, H
−++GaAs ohmic layer 3 has a thickness of 1 to 2 μm, n
The GaAs active layer 2 is finished to a thickness of 10 μm, and the n+GaAs substrate 1 is finished to a thickness of 15 to 20 μm.

Next, as shown in FIG. 3, on the top surface of the scraped n'' GaAs substrate 1, an AuGe layer to be used as the upper electrode 5 is deposited by vapor deposition, and then a resist film 6 is formed on the top surface of the AuGe layer using photolithography. It is formed on the electrode 5.

After that, as shown in FIG. 4, unnecessary parts of the n+GaAs substrate 1 are removed by chemical etching, sandblasting, etc.
The silver plated heat sink 4 is cut into dice using a wire saw, an electrical discharge machine, a laser, a cutter, etc. to produce each element shown in FIG.

The biggest drawback of this traditional manufacturing method is that
At the stage of attaching silver plating to a GaAs wafer, GaAs
The wafer warps, which not only makes it impossible to use large wafers, but also causes distortion in the GaAs crystal, resulting in ri+GaAs
During substrate polishing, countless cracks occur along the shear plane, and Ga
Damage to the As crystal often occurs.

In addition, if you want to take a lead wire from the upper electrode 5 on the plated heat sink 4, or if you want to take out a lead wire from the upper electrode 5 of each chip after forming multiple chips on the same plated heat sink 4, This was difficult considering the structure of the plated heat sink 4.

This invention was made to eliminate the above-mentioned drawbacks.
at a position surrounding a region in which at least one semiconductor element is to be formed in a semiconductor wafer comprising a substrate and an active layer;
After forming a plurality of four parts at a desired depth from the main surface on the active layer side of this semiconductor wafer and forming a material with good thermal conductivity on the main surface including the recesses, the substrate of the semiconductor wafer is thinned and After forming the upper electrode of the semiconductor element on this thinned main surface, unnecessary parts of the semiconductor wafer are removed to create a mesa-shaped semiconductor element having the upper electrode, and the semiconductor element is formed. The material with good thermal conductivity formed in the area can be used as a plastic heat sink, and the material with good thermal conductivity formed in the recess can be used as a bump.

The present invention will be explained below. Figures 6 to 17 show one embodiment of the present invention, and show the manufacturing process of a Gunn diode with a plated heat sink.

First, an nl'' GaAs substrate 1, an nl GaAs active layer 2,
The G shown in FIG.
The aAs wafer is made into n+ by photolithography and chemical etching.
+The surface of the GaAs ohmic layer 3 is finished into a concave shape as shown in FIG.

At this time, it is important that the digging depth is slightly deeper than the thickness of the n7 GaAs active layer 2.

Next, gold nick plating (Au and N) was applied to the entire surface of the recess.
After performing wet electroless plating (a type of wet electroless plating mixed with i),
Alloy in H2 gas at 500°C for 2 minutes.

After that, 150-200μ of silver is applied to that surface by electroplating.
m to form a plated heat sink 4.

This state is shown in FIG. Next, the n+ GaAs substrate 1 is thinned by mechanical polishing and chemical etching using the grown plated heat sink 4 as a reference.

This gradual thinning is shown in FIGS. 9, 10, and 11.

After that, Au-Ge is vapor-deposited on the part that will become the upper electrode 5.
Alloying was carried out at 00° C. for 2 minutes to form the upper electrode 5.

This is shown in FIGS. 12 and 13. After that, a resist film 6 with the same area as the electrode is applied on the upper electrode 5 using photolithography again, as shown in FIG. , about 2~
A thick layer of 3 μm is more effective in protecting the upper electrode 5.

After the process is completed, the chip is formed into a mesa shape as shown in FIG. 15 by sandblasting and chemical etching.

Thereafter, the resist film 6 on the upper electrode 5 is removed and the silver plated heat sink 4 is cut into dice using a wire saw to produce a Gunn diode with a bumped plated heat sink as shown in FIG.

Although the above embodiment describes a GaAs Gunn diode, the present invention can be applied to any semiconductor device equipped with a plated heat sink 4.

Furthermore, this invention provides one plated heat sink 4
This method is not limited to forming a single element on the same plated heat sink 4, but is particularly useful when forming a plurality of elements on the same plated heat sink 4 as shown in FIG.

In addition, 7 in FIG. 17 is a gold lead wire, 8 is a metal rice of a ceramic plate, and 9 is a ceramic plate.

As described in detail above, according to the present invention, since a concave portion is formed on the main surface of a semiconductor wafer on which a material with good thermal conductivity is formed, even if the material with good thermal conductivity is grown thickly, there is little Furthermore, there is less warpage in the process of polishing the semiconductor substrate to make it thinner, unlike in the conventional method, and the semiconductor wafer is not damaged, so the yield of semiconductor devices can be improved.

Furthermore, since the material with good thermal conductivity formed in the recess can be used as a bump, handling of the semiconductor device becomes easier.

Furthermore, it is an extremely useful method when a large number of chips are formed and lead wires are taken out from each chip individually, and is extremely useful in industry.

[Brief explanation of drawings]

Figures 1 to 5 are diagrams for explaining the conventional method.
Figures 4 to 4 are cross-sectional views, Figure 5 is a perspective view, and Figures 6 to 4 are cross-sectional views.
Fig. 17 is a diagram for explaining the present invention; Figs. 6 to 10, Fig. 12, Fig. 14, and Fig. 15 are cross-sectional views;
1 and 13 are top views, and FIGS. 16 and 17 are perspective views. In the figure, 1 is an n+GaAs substrate, 2 is an nGaAs active layer, 3 is an n++GaAs ohmic layer, 4 is a silver plated heat sink, 5 is an upper electrode, 6 is a resist film, and 7
8 is a gold lead wire, 8 is a metalized helical plate, and 9 is a ceramic plate. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1. In a semiconductor wafer equipped with a substrate and an active layer formed on one main surface of this substrate, a desired area is placed from the main surface of the semiconductor wafer on the active layer side at a position surrounding a region where at least one semiconductor element is to be formed. a step of forming a plurality of recesses of different depths, a step of forming a material with good thermal conductivity on the main surface including the recesses on the active layer side of the semiconductor urchin, a step of thinning the substrate of the semiconductor wafer; forming an upper electrode of the semiconductor element on the other principal surface of the thinned substrate; removing a portion of the semiconductor wafer other than the semiconductor element portion having the upper electrode; and shaping the semiconductor element having the upper electrode; A method for manufacturing a semiconductor device including a step of creating a mesa shape.