JPS5840766B2 - Auto clear circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an auto-clear circuit that automatically clears each circuit when power is turned on in an electronic desktop calculator or the like.

Generally, electronic circuits with arithmetic functions, such as electronic desktop calculators, are equipped with an auto-clear circuit that automatically clears circuits such as counters and flip-flops when the power is turned on.

However, the conventional auto clear circuit used in electronic desktop calculators, for example, is based on the LSII circuit as shown in Figure 1.
A resistor 13 and a large-capacity capacitor 14 are externally connected to the auto-clear terminal 12 of the LSI 11, and an inverter 15 is connected to the terminal 12 inside the LSI 11.

Then, when the power is turned on, the inverter 14 outputs an auto clear signal ACL, and this auto clear signal ACL
is maintained for a certain period of time determined by the time constants of the resistor 13 and capacitor 14.

That is, when the power is turned on, the auto clear signal ACL is held by the time constant of the resistor 13 and capacitor 14 until the power supply voltage stabilizes, for example, from 30 m5ec to 50 m5ec, and after the power supply voltage stabilizes, the auto clear signal ACL is held. This allows the computer to start operating by setting the ACL to '0'.

However, in the conventional auto-clear circuit described above, a time constant circuit such as a resistor and a capacitor must be externally attached to the LSI, which increases the number of work steps during manufacturing.
There is a problem in that the cost is high.

Furthermore, externally attaching a resistor and a large-capacity capacitor to an LSI poses a problem in terms of miniaturization.

Furthermore, providing an auto-clear terminal in the LSI increases the number of external connection terminals, which is not preferable.

The present invention has been made in view of the above points, and does not require any external parts, and can hold an auto-clear signal inside the LSI from the time the power is turned on until the power supply voltage stabilizes, and when parts are attached. An object of the present invention is to provide an auto-clear circuit that can reduce the number of work steps and reduce costs.

An embodiment of the present invention will be described below with reference to the drawings.

As shown in Fig. 2, the present invention consists of an oscillation detection circuit 21 that detects the clock pulse φ inside the computer, and a flip-flop 22 for waveform shaping and state maintenance. When the signal ACL is output and internal circuits such as counters and flip-flops are cleared and the clock pulse φ of the internal LSI starts to be output normally, this clock pulse φ is detected by the oscillation detection circuit 21 and the flip-flop 22 is reset. Then, the auto clear signal ACL is set to 0'' so that the operation of the computer can be started.

Next, details of the present invention will be explained with reference to FIG.

In FIG. 3, 31 is an input terminal of the oscillation detection circuit 21, and this input terminal 21 is connected to the clock pulse generation circuit (
(not shown) provides a clock pulse φ.

Generally, in an LSI, a circuit operation is performed in synchronization with clock pulses φl and φ2, that is, a clock pulse φ for signal reading and a clock pulse φ2 for signal reading. ．． φ
Either of 2 is fine.

Thus, the clock pulse φ input to this input terminal 31 is inputted to the gate of the MOS transistor 33 via the capacitor C□.

A capacitor C is connected between the gate of this transistor 33 and the ground.
2 and a MOS transistor 32 are interposed.

The output of the transistor 33 is the MOS transistor 3
The signal is taken out as the output of the oscillation detection circuit 21 via the signals 4 to 36.

The transistors 33 to 36 are supplied with VDD power through load MOS transistors 37 to 40, respectively.

Further, capacitors C3 and C4 are interposed between the output terminals of the transistors 33 and 36 and ground, respectively.

- The flip-flop 22 is mainly composed of MOS transistors 41 to 46, and an MOS transistor 47 whose output operates in synchronization with the clock pulse φ2.
and an auto clear signal ACL via the inverter 48.
is output as

In this case, the flip-flop sets the size of the load MOS transistor 45.46 to (W/L)tr45>(W
/L) is set to the relationship of tr46, so that the transistor 44 is turned on, that is, set, when the power is turned on.

Note that W is the channel width of the MOS transistor, and L is the channel length.

Further, transistors 41 and 42 are for performing reset control, and the output of the oscillation detection circuit 21 is applied to the gate of the transistor 41, and a predetermined timing signal such as D1□, T8 . φ
1 is given.

For example, when the display digit of the computer is 12 digits, this signal is D
02 is a digit signal specifying the 12th digit, T s t
ti is a timing signal specifying the most significant bit of a 4-bit digit, and φ□ is the clock pulse for reading.

Next, the present invention configured as described above will be explained in detail.

First, when the power is turned on, the VDD power begins to change from O■ toward a predetermined level as shown in FIG. 4a.

As the VDD power supply voltage rises, the transistor 44 of the flip 70 tube 22 turns on and becomes set.

That is, this flip-flop 22 is set so that a larger current flows through the transistor 45 than the transistor 46, so when the power is turned on, the transistor 44 side is turned on by the current flowing through the transistor 45, and the set state is established. Become.

Furthermore, when the power is turned on, the clock pulse φ2 applied to the transistor 47 is not generated yet as shown in FIG. As shown in FIG. 4f, the clear signal ACL changes from the O" level to the "1" level as the VDD power supply voltage changes.

Thereafter, even when the clock pulse φ2 shown in FIG.
The output of is held at the "0" level, and the auto clear signal ACL output from the enabler 48 is kept at the 1" level, so that circuits such as 1) counters and flip-flops inside the LSI are held in the clear state.

When the power is first turned on, the oscillation circuit is not operating, and no clock pulse φ is applied to the input terminal 31 of the oscillation detection circuit 21.

When the clock pulse φ is input to the input terminal 31,
When the pulse voltage is VCP, a voltage Va Jz Vcp is applied to point a, that is, the gate of the transistor 33, but C
+C The input of input terminal 31 is DC 0■ or ■DD, etc.
Alternatively, when it is at an intermediate level, Va is approximately O■, and the output of the oscillation detection circuit 21 is held at O■.

Therefore, the transistor 41 of the flip-flop 22 remains off, and the timing pulses D1□, T8.
Even if φ1 is applied to transistor 42, flip-flop 22 is not reset.

When the oscillation circuit starts oscillating due to the rise in the power supply voltage and a clock pulse φ is inputted to the input terminal 31, a voltage Va is excited at point a according to both equations as shown in FIG.

This voltage Va is sequentially inverted via transistors 33 to 36, and is output from the oscillation detection circuit 21 as an oscillation detection signal as shown in FIG. 4e, and is input to the transistor 41 of the flip-flop 22.

In this state, the timing signals D1□ and T8 shown in FIG.
．． When φ1 is applied to the transistor 42, transistors 41 and 42 are both turned on, and the flip-flop 22 is reset with the transistor 44 turned off and the transistor 43 turned on.

Thereafter, when the clock pulse φ2 shown in FIG.
The auto clear signal ACL output from the inverter 48 returns to the "0" level as shown in FIG. 4f, and the clearing of each circuit is released.

In the explanation of FIG. 4 above, when the oscillation detection circuit 21 detects the clock pulse φ, the oscillation detection circuit 21 outputs a pulse-like detection signal, but in this case, the clock pulse φ and It is necessary to synchronize the timing signals given to the 7-lip-flop 22.

Furthermore, when the oscillation detection circuit 21 outputs a direct current oscillation detection signal, there is no need to synchronize the clock pulse φ and the timing signal D02°Ts, φ.

The waveform of the oscillation detection signal of the oscillation detection circuit 21 can be set arbitrarily depending on the sizes of the capacitors C1 to C3 and the transistors 32 and 33, but the signal output form may be determined by taking into consideration the frequency of the clock pulse φ, etc. Select.

FIG. 5 shows the clock pulse φ in the oscillation detection circuit 21 and the input/output signal waveforms of each transistor 33 to 36, where the solid line indicates the case where a DC detection signal is output, and the broken line indicates the case where a pulsed detection signal is output. This is an example of a signal waveform.

When a clock pulse φ shown in FIG. 5A is applied to the input terminal 31, a voltage Va is excited at point a as shown in FIG. Added.

At this time, the capacitor (C1+C2) and the transistor 32, and the capacitor C3 and the transistor 33 play the role of extending the voltage Va excited at the point a in a DC manner.

Therefore, the sizes of capacitors C1 to C3 and transistors 32 and 33 are determined by the frequency and pulse width of clock pulse φ.

Incidentally, since the capacitor C2 needs to be made as small as possible in order to increase the voltage Va, circuit conditions are actually set by the sizes of the capacitors C1 and C3 and the transistors 32 and 33.

When the frequency of clock pulse φ is high, capacitor C
1, C3, and transistors 32 and 33 are relatively small and can lengthen the time width of the signal, but when the frequency of the clock pulse φ becomes lower, for example, 10 KHz or I KHz, it is necessary to increase the size of the capacitors C1 and C8. .

When the frequency of the clock pulse φ is low in this way, when trying to reduce the chip size, the oscillation detection signal is made into a pulse as shown by the broken line in FIG. 5, and the clock pulse φ and the read timing of the flip-flop 22 are If the pulses are synchronized, the purpose can be achieved with small capacitors C, C3.

As described above, according to the present invention, -g[
It detects that the LsI clock pulse has started to be output normally, and uses that detection signal to reset the 7 lip-flop for outputting the auto-clear signal and stop outputting the auto-clear signal, so it is not necessary to use a large capacitor. The time constant circuit used is no longer necessary, and the external parts for the auto clear circuit of the LSI can be eliminated, and the work process for mounting parts can be reduced, reducing costs.

Further, since the auto-clear circuit can be externally attached without any parts, it is advantageous for miniaturization and an external connection terminal for the auto-clear circuit is not required.

Therefore, it is also possible to add other functions to the LSI using these unnecessary terminals.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional auto clear circuit, FIG. 2 is a block diagram showing the basic structure of the present invention, FIG. 3 is a block diagram showing a specific embodiment of the present invention, and FIGS. FIG. 5 is a time chart for explaining the operation of the same embodiment. 21...Oscillation detection circuit, 22...Flip-flop for waveform shaping and state holding, 48...
...Inverter.

Claims (1)

[Claims] 1. A clear signal generation circuit that generates an auto-clear signal when power is turned on, and a clear signal generation circuit that detects that the generation of internal clock pulses has become normal and resets the clear signal generation circuit to generate a clear signal. An auto clear circuit characterized by comprising an oscillation detection circuit that stops output. 2. The auto clear circuit according to claim 1, wherein the clear signal generating circuit is constituted by a flip-flop that is forcibly set when the power is turned on. 3. The auto clear circuit according to claim 2, which comprises a flip-flop and an input m and an output circuit that operate in synchronization with a timing signal.