JPS5841544B2 - Debugging processing system for pattern recognition equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a debug processing system for a pattern recognition device, in particular, a debug processing system for a pattern recognition device having a high calculation processing speed, in order to receive and store randomly generated information in a memory device. This invention relates to a debug processing system for a pattern recognition device, which includes a memory control device that receives information from the pattern recognition device and independently performs write processing to the memory device, and is capable of extracting information essential for debugging the pattern recognition device. It is something.

In a pattern recognition device such as a pattern recognition device, the amount of information to be processed is enormous, and the hardware configuration for performing recognition processing is configured to perform processing at the highest possible speed.

When such a pattern recognition device is manufactured, it is necessary to debug the operation function of the pattern recognition device, but for this purpose, a large amount of known input information is supplied, and the input pattern itself and the input pattern during that time are debugged. It is necessary to extract and analyze analysis results, extracted feature quantities, recognition processing results, etc.

Since the various types of information described above are randomly generated at each processing stage in the pattern recognition device, it is necessary to have a buffer storage means.

However, as mentioned above, while the pattern recognition processing unit is processing a large number of input patterns one after another, if you try to extract the information necessary for debugging one after another, it will be necessary to retrieve the information necessary for debugging through the central processing unit, which operates at normal speed or lower. Storing it in a large-capacity memory device would not be enough time.

Further, the bit widths of the various types of information are random, and it is necessary to write them into the memory device in units of, for example, one word, which further delays the processing.

The present invention aims to solve the above-mentioned problems, and a debugging processing system for a pattern recognition device according to the present invention receives an input cover turn, analyzes the input cover turn, and extracts a feature amount corresponding to the input cover turn. The tag is configured to be connected to a pattern recognition device that performs recognition processing based on the feature amount.The above-mentioned cover pattern or the above-mentioned analysis result held by the pattern recognition device, or one of the above-mentioned feature amount or the above-mentioned recognition processing result, or In a debug processing system for a pattern recognition device that extracts a combination thereof, the input cover pattern, the analysis result, the feature value, or the A memory control circuit unit having a buffer storage means for receiving and storing one or a combination of recognition processing results, a memory device storing the contents of the buffer storage means, and at least writing/reading processing for the memory device. and a central processing unit that controls the pattern recognition device, and the memory control circuit section is configured to be able to directly write to the memory device using a direct memory access method. .

This will be explained below with reference to the drawings.

FIG. 1 shows the configuration of an embodiment of the present invention, and FIG. 2 is an explanatory diagram illustrating an aspect of debugging based on information obtained by the system of the present invention.

In FIG. 1, 1 is a pattern recognition device, such as an optical pattern recognition device, 2 is a debug processing system which is the subject of the present invention, 3 is a memory control circuit section provided in the present invention, and 4 is a large capacity memory device, 5
represents the central processing unit.

The central processing unit 5 is a stored program type processing unit, and performs normal writing and reading processing on the memory device 4, as well as arithmetic processing, information transfer processing to external input/output devices, and control over various devices. It has the function to do.

The memory control circuit section 3 also has an interface to the pattern recognition device 1 and has the following functions.

That is, (1) data (#1) whose bit width is not fixedly determined from the pattern recognition device 1 at random timing;
to #n data), and (ii) #n data).
When all of the 1 data to #n data have been buffered, the data is divided according to the write bus width for the memory device 4, and (ili) the write address information for the memory device 4 is updated according to the division. and is configured to issue a write access request to the memory device 4 at the same time.

In other words, it has a buffer storage means for temporarily storing data, a data editing function section, and a write access function section for the memory device 4.

When the program for operating the debug processing system 2 is loaded into the memory device 4 and started, a control signal is supplied to the pattern recognition device 1 via the memory control circuit section 3, and the pattern recognition device 1 is placed in the debug mode. For example, data specified by a program can be output from the pattern recognition device 1 to the memory control circuit section 3.

At this time, the pattern recognition device 1 outputs control signals (#1 to #nC0NTL) such as timing signals together with data to be transferred (#1 to #n data).

In the memory control circuit section 3, for example, a control signal (#I
C0NTL) sent in parallel with the data (#1
data) in a buffer storage means.

When all the data has been sent as described above, the contents of the buffer storage means are divided one after another according to the bus width to the memory device 4, and at the time of division, a write access request to the memory device 4 is issued to store address information in the memory. The address information is sent to device 4 and updated.

That is, data from the pattern recognition device 1 is written into the memory device 4 at high speed via the memory control circuit section 3.

The central processing unit 5 outputs the contents of the memory device 4 to the external input/output device I10 as necessary.

As described above, the data from the pattern recognition device 1 includes the input cover pattern itself, the analysis result of the input cover pattern, the feature quantity extracted from the input cover pattern, the recognition processing result, etc., and is stored in, for example, a magnetic tape device.

FIG. 2 explains the manner in which debugging is carried out, in which reference numeral 2 is the same debug processing system as shown in FIG. 1, 6 is a magnetic tape device which is one of the input/output devices, and 7 is a matching dictionary or simulator. , 8 represents a mismatch checking device section.

As mentioned above, the debug data output from the debug processing system 2 is temporarily stored in the magnetic tape device 6.

By comparing the contents of the magnetic tape device 6 with the results of a simulation performed by a simulator, a fault in the pattern recognition device 1 is discovered.

In addition, by comparing the feature values stored in the magnetic tape device 6 with an existing matching dictionary and using it to modify the matching dictionary itself, or by checking the number of times the standard pattern is referenced by the pattern recognition device, Provide information for simplifying the harmonized dictionary.

As described above, according to the present invention, various information generated in the pattern recognition device 1 can be transferred and stored in the memory device 4 at high speed, and can be used for debugging processing.

In particular, when the recognition target category is dog and there are many deformations such as handwritten characters, there are many different types of feature values required for identification, so the cause of misrecognition or jikuto may lie in the matching dictionary or in the feature extraction process. Although it is necessary to check whether the information is present in very detailed parts, etc., it becomes possible to extract this large amount of information to the outside.

[Brief explanation of drawings]

FIG. 1 shows the configuration of an embodiment of the present invention, and FIG. 2 is an explanatory diagram illustrating an aspect of debugging based on information obtained by the system of the present invention. In the figure, 1 is a pattern recognition device, 2 is a debug processing system, 3 is a memory control circuit, 4 is a memory device, and 5 is a central processing unit.

Claims (1)

[Claims] 1 is configured to be connected to a pattern recognition device that receives a person's cover turn, analyzes the input cover turn, extracts a feature quantity corresponding to the input cover turn, and performs recognition processing based on the feature quantity; In a depack processing system for a pattern recognition device that extracts one or a combination of the input cover pattern, the analysis result, the feature quantity, or the recognition processing result held by the recognition device, an interface to the pattern recognition device is provided. A memory having buffer storage means for receiving and storing one or a combination of the above-mentioned cover pattern, the above-mentioned analysis result, the above-mentioned feature quantity, or the above-mentioned recognition processing result, which are supplied randomly from the pattern recognition device. A control circuit section, a memory device that stores the contents of the buffer storage means, and a central processing unit that performs at least write/read processing on the memory device and controls the pattern recognition device, and the memory control circuit section has a direct memory device. memory·
1. A debug processing system for a pattern recognition device, characterized in that the system is configured to directly write to the memory device using an access method.