JPS5841688B2 - 2 Tanshi impedance warmer - Google Patents
2 Tanshi impedance warmerInfo
- Publication number
- JPS5841688B2 JPS5841688B2 JP49130125A JP13012574A JPS5841688B2 JP S5841688 B2 JPS5841688 B2 JP S5841688B2 JP 49130125 A JP49130125 A JP 49130125A JP 13012574 A JP13012574 A JP 13012574A JP S5841688 B2 JPS5841688 B2 JP S5841688B2
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- impedance
- resistor
- transistor
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Networks Using Active Elements (AREA)
Description
【発明の詳細な説明】
本発明は、印加電圧に応じてインピーダンスが変化し、
しかも、印加電圧が犬となるにつれてインピーダンスが
小となって一定値に漸近し確つ印加電圧が小となるにつ
れてインピーダンスが無限大に漸近するような特性を有
する２端子インピーダンス回路を提案せんとするもので
ある。[Detailed Description of the Invention] The present invention is characterized in that impedance changes depending on applied voltage,
Furthermore, we will propose a two-terminal impedance circuit having such characteristics that as the applied voltage decreases, the impedance decreases and asymptotically approaches a constant value, and as the applied voltage decreases, the impedance asymptotically approaches to infinity. It is something.
以下に図面について本発明をその実施例につき詳細に説
明するに、本発明２端子インピーダンス回路は、第１図
に示す如く、トランジスタ（この例ではＮＰＮ形のバイ
ポーラトランジスタ）Ｑのコレクタが第１の端子Ｔ１に
接続され、トランジスタＱのベースが第１の抵抗器（抵
抗値をＲ１とする）１を通じて第１の端子Ｔ１に接続さ
れると共に第２の抵抗器（抵抗値をＲ２とする）２を通
じて第２の端子Ｔ２に接続され、トランジスタＱの工□
ツタが第３の抵抗器（抵抗値をＲ３とする）３を通じて
第２の端子Ｔ２に接続されて成るものである。The present invention will be described in detail below with reference to the drawings.The two-terminal impedance circuit of the present invention has a two-terminal impedance circuit as shown in FIG. The base of the transistor Q is connected to the first terminal T1 through a first resistor (resistance value R1) 1, and a second resistor (resistance value R2) 2. is connected to the second terminal T2 through the terminal T2 of the transistor Q
The ivy is connected to the second terminal T2 through a third resistor 3 (having a resistance value of R3).
次に、この本発明による２端子インピーダンス回路の解
析を、第２図の等価回路を参照して行なう。Next, the two-terminal impedance circuit according to the present invention will be analyzed with reference to the equivalent circuit shown in FIG.
第２図では、トランジスタＱを、電圧ＶＢＥの電圧源５
、電流ｈｆｅ・Ｉｂの電流源及び抵抗ｒｏの抵抗器６よ
り成る等価回路にて示しである。In FIG. 2, transistor Q is connected to voltage source 5 of voltage VBE.
, an equivalent circuit consisting of a current source with a current hfe·Ib and a resistor 6 with a resistance ro.
尚、ｖＢＥはトランジスタＱのベース・工□ツタ間電圧
（例えば０．６Ｖ）、ｈｆｅ はその工□ツタ接地電
流増巾率、Ｉｂはそのベース電流、ｒｏはそのコレクタ
抵抗を夫々示す。Note that vBE is the voltage between the base and the terminal (for example, 0.6 V) of the transistor Q, hfe is the amplification rate of the terminal ground current, Ib is the base current, and ro is the collector resistance.
又、第２図において、第１及び第２の端子Ｔ１，７２間
に印加される電圧をＶ（この場合一応直流電圧にて考え
る）、それによって第１及び第２の端子Ｔ１，７２間に
流れる電流を■、第１の抵抗器１を流れる電流を■１、
ベース電流をＩｂとし、従って第２の抵抗器２を流れる
電流はＩ、−Ｉｂ、第３の抵抗器３を流れる電流は（１
＋ｈｆｏ）Ｉｂとなる。In addition, in FIG. 2, the voltage applied between the first and second terminals T1 and 72 is V (in this case, consider it as a DC voltage), so that the voltage applied between the first and second terminals T1 and 72 is The flowing current is ■, the current flowing through the first resistor 1 is ■1,
The base current is Ib, so the current flowing through the second resistor 2 is I, -Ib, and the current flowing through the third resistor 3 is (1
+hfo)Ib.
第２図の等何回路においては、トランジスタＱがオン状
態にあるとき、その各電圧、電流間において次のような
関係式が成立する。In the equal circuit shown in FIG. 2, when the transistor Q is in the on state, the following relational expression holds between the respective voltages and currents.
※は夫々次の如くなる。* is as follows.
尚、式αυにおいて、■≧０である。In addition, in the formula αυ, ■≧0.
式αυをグラフに表わすと、第３図の如くなる。When formula αυ is expressed in a graph, it looks like FIG. 3.
かくして、第１及び第２の端子Ｔ１，７２間のインピー
ダンス（抵抗）２は、式ａυから、となる。Thus, the impedance (resistance) 2 between the first and second terminals T1 and 72 is given by the formula aυ.
尚武α望において、ｚ〉０である。式（１つをグラフに
表わすと第４図の如くなる。In the case of Shangwu α, z〉0. Equation (If one is represented in a graph, it will look like FIG. 4.
このグラフは、Ｖ＝−及びＺ＝−を夫々漸近線とする双
曲線Ａ
である。This graph is a hyperbola A with asymptotes at V=- and Z=-, respectively.
このインピーダンス２の電圧■に対する特性は、第１、
第２及び第３の抵抗器１，２及び３の各抵抗値Ｒ，，Ｒ
２及びＲ３を適当に可変することにより、変化させるこ
とができる。The characteristics of this impedance 2 with respect to voltage ■ are as follows:
Resistance values R, , R of the second and third resistors 1, 2 and 3
It can be changed by appropriately varying 2 and R3.
一例としてＲ１＝２（ｋ、Ｑ）、Ｒ２＝ ２００ （、
！Ｑ）、Ｒ３＝２０Ｑ、ＶＢＥ＝０．６（Ｖ）の場合、
−及び１Ｂ １
−は夫々−＝６（Ｖ）、−＝２００（Ω）となる。As an example, R1=2(k,Q), R2=200 (,
! Q), R3=20Q, VBE=0.6(V),
- and 1B 1 - are -=6 (V) and -=200 (Ω), respectively.
ＡＡ Ａ
上述せる本発明２端子インピーダンス回路は、トランジ
スタのコレクタが第１の端子に接続され、トランジスタ
のベースが第１の抵抗器を通じて第１の端子に接続され
ると共に第２の抵抗器を通じて第２の端子に接続され、
トランジスタのエミッタが第３の抵抗器を通じて第２の
端子に接続されて成り、第１及び第２の端子間のインピ
ーダンスを２、第１及び第２の端子間に印加されるべき
電圧をＶ、第１、第２及び第３の抵抗器の各抵抗値ヲ夫
々Ｒ１、Ｒ２、Ｒ３、トランジスタのベース・エミッタ
間電圧をＶＢＥ とするとき、電圧■に対するインピ
ーダンスＺの特性が、
を満足する双曲線特性となるようにして成るものである
から、印加電圧に応じてインピーダンスが変化し、しか
も印加電圧が犬になるにつれてインピーダンスが小とな
って一定値に漸近し且つ印加電圧が小となるにつれてイ
ンピーダンスが無限大に漸近する特性を有する２端子イ
ンピーダンス回路を得ることができると共に、第３の抵
抗器の抵抗値Ｒ３ヶ選定すう。AA A In the two-terminal impedance circuit of the present invention described above, the collector of the transistor is connected to the first terminal, the base of the transistor is connected to the first terminal through the first resistor, and the collector is connected to the first terminal through the second resistor. Connected to terminal 2,
The emitter of the transistor is connected to the second terminal through a third resistor, the impedance between the first and second terminals is 2, the voltage to be applied between the first and second terminals is V, When the resistance values of the first, second, and third resistors are R1, R2, and R3, respectively, and the voltage between the base and emitter of the transistor is VBE, the characteristic of the impedance Z with respect to the voltage ■ is a hyperbolic characteristic that satisfies the following. Therefore, the impedance changes according to the applied voltage, and as the applied voltage decreases, the impedance decreases and approaches a constant value, and as the applied voltage decreases, the impedance decreases. A two-terminal impedance circuit having a characteristic asymptotically approaching infinity can be obtained, and three resistance values R of the third resistor can be selected.
よよっ１、上式。１８Ａ を同時に容易に選定することができる。Yoyo 1, above formula. 18A can be easily selected at the same time.
第１図は本発明の一実施例を示す回路図、第２図はその
等価回路図、第３図及び第４図はその特性曲線図である
。
Ｑはトランジスタ、Ｔ１は第１の端子、Ｔ２は第２の端
子、１は第１の抵抗器、２は第２の抵抗器、３は第３の
抵抗器である。FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram thereof, and FIGS. 3 and 4 are characteristic curve diagrams thereof. Q is a transistor, T1 is a first terminal, T2 is a second terminal, 1 is a first resistor, 2 is a second resistor, and 3 is a third resistor.
Claims (1)
上記トランジスタのベースが第１の抵抗器を通じて上記
第１の端子に接続されると共に第２の抵抗器を通じて第
２の端子に接続され、上記トランジスタのエミッタが第
３の抵抗器を通じて上記第２の端子に接続されて成り、
上記第１及び第２の端子間のインピーダンスを２、上記
第１及び第２の端子間に印加されるべき電圧をＶ、上記
第１、第２及び第３の抵抗器の各抵抗値を夫々Ｒ１、Ｒ
２、Ｒ３、上記トランジスタのベース・エミッタ間電圧
をＶＢＥ とするとき、上記電圧■に対する上記インピ
ーダンスＺの特性が、 を満足する双曲線特性となるようにして成ることを特徴
とする２端子インピーダンス回路。[Claims] 1. The collector of the transistor is connected to the first terminal,
A base of the transistor is connected to the first terminal through a first resistor and a second terminal through a second resistor, and an emitter of the transistor is connected to the second terminal through a third resistor. It is connected to a terminal,
The impedance between the first and second terminals is 2, the voltage to be applied between the first and second terminals is V, and the resistance values of the first, second, and third resistors are respectively R1, R
2. R3. A two-terminal impedance circuit characterized in that, when the base-emitter voltage of the transistor is VBE, the characteristic of the impedance Z with respect to the voltage (2) is a hyperbolic characteristic satisfying the following.
Priority Applications (9)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP49130125A JPS5841688B2 (en) | 1974-11-12 | 1974-11-12 | 2 Tanshi impedance warmer |
| GB46090/75A GB1508228A (en) | 1974-11-12 | 1975-11-06 | Transistor circuits |
| AU86384/75A AU499114B2 (en) | 1974-11-12 | 1975-11-07 | Fet bias circuit |
| CA75239332A CA1049106A (en) | 1974-11-12 | 1975-11-10 | Bias circuit for fet |
| US05/630,331 US4031482A (en) | 1974-11-12 | 1975-11-10 | Bias circuit for FET |
| BR7507422*A BR7507422A (en) | 1974-11-12 | 1975-11-11 | PERFECTING IN POLARIZATION CIRCUIT FOR USE WITH FIELD EFFECT TRANSISTORS AND PERFECTING IN TENSION CONTROLLED IMPEDANCE |
| DE19752550636 DE2550636A1 (en) | 1974-11-12 | 1975-11-11 | PRE-VOLTAGE CIRCUIT FOR A FIELD EFFECT TRANSISTOR |
| NL7513266A NL7513266A (en) | 1974-11-12 | 1975-11-12 | CIRCUIT FOR SUPPLY OF A SETTING VOLTAGE OF A FIELD EFFECT TRANSISTOR. |
| FR7534489A FR2291640A1 (en) | 1974-11-12 | 1975-11-12 | POLARIZATION CIRCUIT OF A FIELD-EFFECT TRANSISTOR |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP49130125A JPS5841688B2 (en) | 1974-11-12 | 1974-11-12 | 2 Tanshi impedance warmer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5155648A JPS5155648A (en) | 1976-05-15 |
| JPS5841688B2 true JPS5841688B2 (en) | 1983-09-13 |
Family
ID=15026533
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP49130125A Expired JPS5841688B2 (en) | 1974-11-12 | 1974-11-12 | 2 Tanshi impedance warmer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5841688B2 (en) |
-
1974
- 1974-11-12 JP JP49130125A patent/JPS5841688B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5155648A (en) | 1976-05-15 |
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