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JPS5841771B2 - semiconductor equipment - Google Patents
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JPS5841771B2 - semiconductor equipment - Google Patents

semiconductor equipment

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Publication number
JPS5841771B2
JPS5841771B2 JP14432077A JP14432077A JPS5841771B2 JP S5841771 B2 JPS5841771 B2 JP S5841771B2 JP 14432077 A JP14432077 A JP 14432077A JP 14432077 A JP14432077 A JP 14432077A JP S5841771 B2 JPS5841771 B2 JP S5841771B2
Authority
JP
Japan
Prior art keywords
insulator
main electrode
main
plate
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP14432077A
Other languages
Japanese (ja)
Other versions
JPS5476063A (en
Inventor
光雄 大館
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP14432077A priority Critical patent/JPS5841771B2/en
Priority to US05/957,330 priority patent/US4274106A/en
Priority to DE2848252A priority patent/DE2848252C2/en
Publication of JPS5476063A publication Critical patent/JPS5476063A/en
Publication of JPS5841771B2 publication Critical patent/JPS5841771B2/en
Expired legal-status Critical Current

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Description

【発明の詳細な説明】 この発明は半導体装置に係り、特にその短絡電流による
爆発に対する耐量の向上を図るための構造の改良に関す
るものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to an improvement in the structure of the semiconductor device in order to improve its resistance to explosion due to short-circuit current.

最近、半導体装置、特に電力用半導体装置では、大電力
・小形化が進められている。
Recently, semiconductor devices, especially power semiconductor devices, are becoming more powerful and smaller.

しかしながら、定格電流容量が増大すると、保護用ヒユ
ーズとの協調をとることが困難となり、保護用ヒユーズ
が適当でない場合には、このヒユーズがしゃ断する筐で
の数サイクルの間に、半導体装置にその定格電流の数十
倍の短絡電流が流れ、この短絡電流により上記半導体装
置が爆発破壊するおそれがあった。
However, as the rated current capacity increases, it becomes difficult to coordinate with the protective fuse, and if the protective fuse is not suitable, the semiconductor device may be A short-circuit current several tens of times higher than the rated current flows, and there is a risk that the semiconductor device may explode and be destroyed by this short-circuit current.

以下、図面を用いて説明する。This will be explained below using the drawings.

第1図は従来の電力用半導体整流装置を示す要部破砕正
面図である。
FIG. 1 is a fragmented front view of the main parts of a conventional power semiconductor rectifier.

図において、1は半導体整流素子、2は半導体整流素子
1のPNN+接合(図示せず)が形成されたシリコン基
板、3はシリコン基板2とほぼ等しい熱膨張係数を有す
るモリブデン板からなりシリコン基板2を支持する支持
板、4はシリコン基板2と支持板3とをろう付けするア
ルミニウムアルミニウムシリコン(Al−AlSi)共
晶層、5はシリコン基板1の主面上にアル□ニウムA7
の蒸着により形成されたAl電極層、6は銅からなシ半
導体整流素子1のA7電極層5に加圧されて接触する第
1の主電極、Tは銅からなり、半導体整流素子1の支持
板3に加圧されて接触する第2の主電極、8はセラ□ツ
クなどの絶縁材料からなり半導体整流素子1と第1.第
2の主電極6,7とを取り囲んで設けられた筒状の絶縁
体、9は銅薄板からなり内周部が第1の主電極6にろう
付けされ外周部が絶縁体8の第1の端面にろう付けされ
た可撓性のある可撓金属板、10は鉄板もしくは鉄−ニ
ッケル合金板からなり絶縁体8の第2の端面にろう付け
されたつば状平板、11は鉄板もしくは鉄−ニッケル合
金板からなり内周部が第2の主電極Tにろう付けされ外
周部がつば状平板10に溶接された環状平板、12は第
1Q主電極6および第2の主電極7にそれぞれろう付け
された放熱フィンを示す。
In the figure, 1 is a semiconductor rectifying element, 2 is a silicon substrate on which a PNN+ junction (not shown) of the semiconductor rectifying element 1 is formed, and 3 is a molybdenum plate having almost the same coefficient of thermal expansion as the silicon substrate 2. 4 is an aluminum aluminum silicon (Al-AlSi) eutectic layer for brazing the silicon substrate 2 and the support plate 3; 5 is an aluminum A7 layer on the main surface of the silicon substrate 1;
6 is made of copper; T is the first main electrode that is pressed into contact with the A7 electrode layer 5 of the semiconductor rectifying element 1; T is made of copper and serves as a support for the semiconductor rectifying element 1; The second main electrode 8, which is pressed into contact with the plate 3, is made of an insulating material such as ceramic, and is connected to the semiconductor rectifying element 1 and the first main electrode 8. A cylindrical insulator 9 provided surrounding the second main electrodes 6 and 7 is made of a copper thin plate, and the inner circumference is brazed to the first main electrode 6 and the outer circumference is the first insulator 8. 10 is an iron plate or an iron-nickel alloy plate and is a collar-shaped flat plate brazed to the second end face of the insulator 8; 11 is an iron plate or iron plate; - An annular flat plate made of a nickel alloy plate, the inner circumference of which is brazed to the second main electrode T and the outer circumference welded to the collar-shaped flat plate 10; 12 is connected to the first Q main electrode 6 and the second main electrode 7, respectively; Shows brazed heat dissipation fins.

次に、このように構成された電力用半導体整流装置の短
絡電流による破壊状態の一例を第2図に示す短絡電流の
波形図および第3図に示す要部破砕正面図で説明する。
Next, an example of a state of destruction due to a short circuit current in the power semiconductor rectifier configured as described above will be explained with reference to a waveform diagram of the short circuit current shown in FIG. 2 and a fragmented front view of the main part shown in FIG. 3.

この電力用半導体整流装置の両生電極6,7間に、定格
サージ順電流よりも大きい順電流が流れ得るような交流
電圧を印加すると、第2図に示すように、第1のサイク
ルでは、第1図に示したシリコン基板2に流れる順電流
によりシリコン基板2の温度が250〜500’Ctで
上昇するが、そのPNN+接合が破壊に至らず、逆電流
が阻止される。
When an AC voltage that allows a forward current larger than the rated surge forward current to flow is applied between the bidirectional electrodes 6 and 7 of this power semiconductor rectifier, as shown in FIG. Although the temperature of the silicon substrate 2 rises to 250 to 500'Ct due to the forward current flowing through the silicon substrate 2 shown in FIG. 1, the PNN+ junction is not destroyed and the reverse current is blocked.

ところが、第2のサイクルでは、シリコン基板2の温度
が更に1200〜2000’C4で上昇し、この温度上
昇により、シリコン基板20PNN+接合が整流機能を
失い、逆電流が流れるようになる。
However, in the second cycle, the temperature of the silicon substrate 2 further increases to 1200 to 2000'C4, and due to this temperature increase, the silicon substrate 20PNN+ junction loses its rectifying function, and a reverse current begins to flow.

この逆電流が流れるようになると、シリコン基板2の温
度が益々上昇し、第2のサイクル以後は短絡電流が流れ
るようになる。
When this reverse current starts to flow, the temperature of the silicon substrate 2 increases more and more, and a short circuit current starts to flow after the second cycle.

このように、短絡電流が流れるようになると、シリコン
基板2の温度がその主面に形成されたAl−AlSi共
晶層4およびAA電極層5の融点以上となり、これらの
層4,5がシリコン基板2の周辺部から蒸発する。
In this way, when a short circuit current starts to flow, the temperature of the silicon substrate 2 becomes higher than the melting point of the Al-AlSi eutectic layer 4 and the AA electrode layer 5 formed on its main surface, and these layers 4 and 5 become silicon It evaporates from the periphery of the substrate 2.

この蒸発に伴ないシリコン基板2の周辺部にトいて、シ
リコン基板2と第1の主電極6との間、およびシリコン
基板2と支持板3との間に高温アークが発生する。
Along with this evaporation, high-temperature arcs are generated around the silicon substrate 2, between the silicon substrate 2 and the first main electrode 6, and between the silicon substrate 2 and the support plate 3.

この高温アークにより、シリコン基板2の周辺部ならび
にこの周辺部近傍の第1の主電極6および支持板3がそ
れぞれ溶融され溶融片となって第1の主電極6と第2の
主電極7と絶縁体8とで作る空間内に飛散するとともに
、この空間内の封入ガスがプラズマ状態となり、急膨張
する。
This high-temperature arc melts the periphery of the silicon substrate 2 and the first main electrode 6 and support plate 3 near this periphery to form molten pieces, which form the first main electrode 6 and the second main electrode 7. It scatters into the space created by the insulator 8, and the gas sealed in this space becomes a plasma and rapidly expands.

ところで、従来の電力用半導体装置の構造では第1の主
電極6と第2の主電極7と絶縁体8とで作る空間内に可
撓金属板9および環状平板11などの厚さの薄い金属板
が露出しているので、これらの金属板に上記封入ガスの
プラズマがふれてその温度が上昇する上に、更にこれら
の金属板に上記溶融片がぶつかるので、その溶融片のも
つエネルギにより上記金属板の温度が融点に達し、上記
溶融片のぶつかった部分に穴があく。
By the way, in the structure of a conventional power semiconductor device, a thin metal plate such as a flexible metal plate 9 and an annular flat plate 11 is placed in the space created by the first main electrode 6, the second main electrode 7, and the insulator 8. Since the plates are exposed, the plasma of the sealed gas comes in contact with these metal plates, raising their temperature. Furthermore, since the molten pieces collide with these metal plates, the energy of the molten pieces causes the above-mentioned The temperature of the metal plate reaches its melting point, and a hole is created where the molten piece collides with the metal plate.

この穴から上記急膨張した封入ガスが上記溶融片を伴な
って外部へ爆発的に噴出する。
From this hole, the rapidly expanded filled gas is explosively ejected to the outside, accompanied by the molten pieces.

この破壊状態を第3図に示す。This state of destruction is shown in FIG.

よって、従来の構造では、この外部へ爆発的に噴出する
溶融片により、半導体装置の設置場所によっては重大な
災害を招く危険性があるという欠点があった。
Therefore, the conventional structure has the disadvantage that the molten pieces explosively ejected to the outside may cause a serious disaster depending on the location where the semiconductor device is installed.

な釦上述の実験に用いた半導体装置は、サージ順電流(
IFsM)33.oooA、電流二乗時間積(I2t
)5X10 A Sを保障するものであり、印加電
圧1,0OOV、短絡電流170KA、電流二乗時間積
20XI06A2Sの条件で実験を行った結果、全ての
試料が破壊した。
The semiconductor device used in the above experiment has a surge forward current (
IFsM)33. oooA, current squared time product (I2t
) 5X10A S, and as a result of conducting experiments under the conditions of applied voltage 1.0OOV, short circuit current 170KA, and current squared time product 20XI06A2S, all samples were destroyed.

この発明は上述の欠点に鑑みてなされたもので、第1お
よび第2の主電極がその対向方向においてそれぞれ絶縁
体と対向し、上記第1および第2の主電極と絶縁体との
対向部間に弾性を有する遮蔽体を設けることによって、
爆発耐量のある半導体装置を提供することを目的とする
The present invention has been made in view of the above-mentioned drawbacks, and includes first and second main electrodes each facing an insulator in their opposing directions, and a portion where the first and second main electrodes and the insulator face each other. By providing an elastic shield between the
The purpose is to provide a semiconductor device with explosion resistance.

第4図はこの発明による電力用半導体整流装置の一実施
例を示す要部破砕正面図である。
FIG. 4 is a fragmented front view of essential parts showing an embodiment of a power semiconductor rectifying device according to the present invention.

図において、13aおよび13bはそれぞれ第1および
第2の主電極6,7の全周にわたって設けられた突出部
、14は絶縁体8の内面に全周にわたって設けられた突
出部、15は第1および第2の主電極6,7の突出部1
3a、13bと絶縁体8の突出部14との対向面間に介
在し、半導体整流素子1から可撓金属板9および環状平
板11への通路を閉鎖するように設けられた金属からな
る断面U字形の環状遮蔽体である。
In the figure, 13a and 13b are protrusions provided over the entire circumference of the first and second main electrodes 6 and 7, respectively; 14 is a protrusion provided on the inner surface of the insulator 8 over the entire circumference; and the protrusion 1 of the second main electrodes 6, 7
3a, 13b and the protruding portion 14 of the insulator 8, and the cross section U is made of metal and is provided so as to close the passage from the semiconductor rectifying element 1 to the flexible metal plate 9 and the annular flat plate 11. It is a letter-shaped annular shield.

このように構成された電力用半導体整流装置では、短絡
電流により半導体整流素子1の周辺部に発生した高温ア
ークによって溶融した部材の溶融片が、図中に実線矢印
で示すように、各突出部13a、13b、14に当り、
可撓金属板9および環状平板11に肖ることを防止する
ことができると共に、上記高温アークによりプラズマ化
された封入ガスのプラズマが直接可撓′金属板9および
環状平板11にふれることも防止することができる。
In the power semiconductor rectifying device configured in this way, melted pieces of the member melted by the high temperature arc generated around the semiconductor rectifying element 1 due to the short circuit current are scattered at each protrusion, as shown by the solid line arrows in the figure. 13a, 13b, 14,
It is possible to prevent the flexible metal plate 9 and the annular flat plate 11 from touching the flexible metal plate 9 and the annular flat plate 11, and also to prevent the plasma of the sealed gas turned into plasma by the high temperature arc from directly touching the flexible metal plate 9 and the annular flat plate 11. can do.

絶縁体8は大きな熱容量を持っており、また第1および
第2の主電極6,7の各突出部13a。
The insulator 8 has a large heat capacity, and each protrusion 13a of the first and second main electrodes 6, 7.

13bの厚さが1m以上であれば、図中に点線矢印で示
すように、各主電極6,7および絶縁体8内部に上記溶
融片のもつエネルギが吸収され、溶融片はこれに固着す
る。
If the thickness of 13b is 1 m or more, the energy of the melted pieces is absorbed inside each main electrode 6, 7 and insulator 8, and the melted pieces are fixed thereto, as shown by the dotted arrows in the figure. .

突出部13a、13b。14に集中的に溶融片が当る場
合は、大きなエネルギにてこれを溶かすことになるが、
これに要するエネルギが大きく消費され、また加速され
た溶融片が一時的に停止するために、可撓金属板9およ
び環状平板11を溶かし破るだけのエネルギを持たなく
なる。
Projections 13a, 13b. If the molten pieces hit 14 intensively, it will be melted with a large amount of energy,
This consumes a large amount of energy, and since the accelerated melting pieces temporarily stop, they do not have enough energy to melt and break the flexible metal plate 9 and the annular flat plate 11.

更に各突出部13a、13b。14間を通過しようとす
る溶融片は全体の数多であり、しかもここには遮蔽体1
5があるため、この遮蔽体を通り抜けることなくこれの
表面に固着する。
Furthermore, each protrusion 13a, 13b. There are a large number of melted pieces trying to pass through the space between the shield 1 and the shield 1.
5, it adheres to the surface of this shield without passing through it.

よって第1図に示した従来装置のように、可撓金属板9
および環状平板11の温度が急速に融点に達し、融解し
て穴かあくのを抑制できるので、上記溶融片が爆発状態
となって装置の設置場所周辺に飛び散るのを防止するこ
とができる。
Therefore, as in the conventional device shown in FIG.
Also, the temperature of the annular flat plate 11 rapidly reaches its melting point, and it is possible to suppress the formation of holes due to melting, so that it is possible to prevent the molten pieces from becoming explosive and scattering around the installation location of the device.

な卦絶縁体8の内壁と各主電極6,7の端面との間隙は
、それらの熱膨張差と加工精度によって決1す、銅から
なる主電極が直径70mmのものでは、片側Q、 6
MAILあればよい。
The gap between the inner wall of the insulator 8 and the end face of each main electrode 6, 7 is determined by their thermal expansion difference and processing accuracy.If the main electrode is made of copper and has a diameter of 70 mm, one side Q, 6
All you need is MAIL.

また各主電極6,7の突出部13a、13bと絶縁体8
の突出部14の対向面間の間隙は、挿入する遮蔽体15
により決めればよいが、挿入する遮蔽体15の弾性力は
、各主電極6,7にそれぞれ取り付けられている可撓金
属板9および環状平板11の弾性力より小さくすること
が望曾しい。
In addition, the protrusions 13a and 13b of each main electrode 6 and 7 and the insulator 8
The gap between the opposing surfaces of the protrusion 14 is the width of the shield 15 to be inserted.
However, it is desirable that the elastic force of the inserted shield 15 be smaller than the elastic force of the flexible metal plate 9 and the annular flat plate 11 attached to the main electrodes 6 and 7, respectively.

なお上述の実施例においては、各主電極6,7と絶縁体
8にそれぞれ突出部13a、13b。
In the above embodiment, the main electrodes 6 and 7 and the insulator 8 have protrusions 13a and 13b, respectively.

14を設け、各主電極6,7の突出部13a。14, and a protrusion 13a of each main electrode 6,7.

13bと絶縁体8の突出部14との対向部間に弾性を有
する遮蔽体15を挿入するようにしたが、第5図に示す
ように、絶縁体8には突出部を設けず、各主電極6,7
の突出部13a、13bが絶縁体8の両端面に対向する
ようにして、この対向部間に例えば断面円形の環状遮蔽
体15を挿入しても同等の効果を奏する。
Although the elastic shield 15 is inserted between the facing portion of the insulator 13b and the protrusion 14 of the insulator 8, as shown in FIG. Electrodes 6, 7
The same effect can be obtained by inserting, for example, an annular shield 15 having a circular cross section between the opposing portions so that the protruding portions 13a and 13b face both end surfaces of the insulator 8.

第6図a−eはそれぞれこの発明の特徴とする環状遮蔽
体15の直径方向断面を示す断面図である。
FIGS. 6a to 6e are sectional views showing a diametrical cross section of the annular shield 15, which is a feature of the present invention.

第6図a、b、eはそれぞれ金属ばね材例えば洋白、ス
テンレス、キュプロニッケルなどからなる厚さ0.1〜
Q、 3 ytmのリング板を弾性をもつように加工し
て形成したもので、aは断面が傾斜した長方形に、bは
断面U字形に、eは断面中空円形に形成したものである
Figure 6 a, b, and e are each made of a metal spring material such as nickel silver, stainless steel, cupronickel, etc., and have a thickness of 0.1~
Q. It is formed by processing a 3 ytm ring plate to have elasticity, and a has an inclined rectangular cross section, b has a U-shaped cross section, and e has a hollow circular cross section.

また第6図c、dはそれぞれ弾性絶縁物例えばケイ素、
フッ素系ゴムを加工して形成したもので、Cは断面円形
に、dは断面方形に形成したものである。
In addition, FIGS. 6c and d show elastic insulators such as silicon, respectively.
It is formed by processing fluororubber, and C has a circular cross section, and d has a square cross section.

実験によれば、厚さ0.2 mm(IJfr面U字形遮
蔽体15を用いたものでは、電流二乗時間積が8×10
7A2S以下の値では、破壊しないことが判明した。
According to experiments, when the thickness is 0.2 mm (IJfr surface U-shaped shield 15 is used, the current squared time product is 8 × 10
It was found that a value of 7A2S or less does not cause destruction.

以上述べたようにこの発明によれば、第1および第2の
主電極がその対向方向においてそれぞれ絶縁体と対向し
、上記第1および第2の主電極と絶縁体との対向部間に
弾性を有する遮蔽体を挿入したので、従来のものより電
流二乗時間積値を大きくすることができ、爆発耐量のあ
る半導体装置を実現することができる。
As described above, according to the present invention, the first and second main electrodes each face the insulator in their opposing directions, and there is an elastic force between the facing portions of the first and second main electrodes and the insulator. Since a shield having a shielding structure is inserted, the current squared time product value can be made larger than that of the conventional one, and a semiconductor device with explosion resistance can be realized.

な釦以上は電力用半導体整流装置を例にとって述べてき
たが、この発明はこれに限らず、この他の半導体装置に
適用することができる。
Although the above description has been made using a power semiconductor rectifier as an example, the present invention is not limited to this and can be applied to other semiconductor devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の電力用半導体整流装置を示す要部破砕正
面図、第2図は従来の電力用半導体整流装置の短絡電流
の一例を示す電流波形図、第3図は第1図に示す従来装
置の短絡電流による破壊状態の一例を示す要部破砕正面
図、第4図はこの発明の一実施例を示す要部破砕正面図
、第5図はこの発明の他の実施例を示す要部破砕正面図
、第6図a−eはそれぞれこの発明の特徴とする遮蔽体
を示す断面図である。 図において、1は半導体整流素子、6は第1の主電極、
7は第2の主電極、8は絶縁体、9は可撓金属板、10
はつば状平板、11は環状平板、13a、13b、14
は突出部、15は環状遮蔽体である。 なお、図中同一符号は夫々同一または相当部分を示す。
Fig. 1 is a fragmented front view of main parts showing a conventional power semiconductor rectifier, Fig. 2 is a current waveform diagram showing an example of short circuit current of a conventional power semiconductor rectifier, and Fig. 3 is shown in Fig. 1. FIG. 4 is a fragmented front view of the main part showing an example of a state of destruction due to short-circuit current of a conventional device. FIG. 4 is a front view of the main part broken, showing one embodiment of the present invention. FIG. A partially exploded front view and FIGS. 6a to 6e are sectional views showing a shielding body that is a feature of the present invention, respectively. In the figure, 1 is a semiconductor rectifier, 6 is a first main electrode,
7 is a second main electrode, 8 is an insulator, 9 is a flexible metal plate, 10
11 is an annular flat plate, 13a, 13b, 14
is a protrusion, and 15 is an annular shield. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] 1 半導体素子、この半導体素子をはさんで設けられた
第1.第2の主電極、上記半導体素子ど上記第1.第2
の主電極の上記半導体素子への当接部の外周を囲むよう
に配設された絶縁体、この絶縁体の両端面にそれぞれ外
周部が取9付けられ、上記第1.第2の主電極に内周部
が取り付けられた第1.第2の可撓金属板を備えてなる
半導体装置に釦いて、上記第1.第2の主電極がその対
向方向においてそれぞれ上記絶縁体と対向する部分を有
し、この対向部分と上記絶縁体との間に弾性を有する遮
蔽体を挿入したことを特徴とする半導体装置。
1 semiconductor element, a first semiconductor element provided with this semiconductor element in between. The second main electrode, the semiconductor element and the first. Second
An insulator is disposed so as to surround the outer periphery of the contact portion of the main electrode to the semiconductor element, and outer peripheral portions are attached to both end faces of the insulator, respectively. The first main electrode has an inner circumference attached to the second main electrode. The first button is pressed on the semiconductor device including the second flexible metal plate. A semiconductor device characterized in that the second main electrode has a portion facing the insulator in the opposing direction, and an elastic shield is inserted between the facing portion and the insulator.
JP14432077A 1977-11-07 1977-11-30 semiconductor equipment Expired JPS5841771B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP14432077A JPS5841771B2 (en) 1977-11-30 1977-11-30 semiconductor equipment
US05/957,330 US4274106A (en) 1977-11-07 1978-11-03 Explosion proof vibration resistant flat package semiconductor device
DE2848252A DE2848252C2 (en) 1977-11-07 1978-11-07 Semiconductor component and method for its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14432077A JPS5841771B2 (en) 1977-11-30 1977-11-30 semiconductor equipment

Publications (2)

Publication Number Publication Date
JPS5476063A JPS5476063A (en) 1979-06-18
JPS5841771B2 true JPS5841771B2 (en) 1983-09-14

Family

ID=15359341

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14432077A Expired JPS5841771B2 (en) 1977-11-07 1977-11-30 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS5841771B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105934821B (en) * 2014-01-21 2018-11-23 Abb瑞士股份有限公司 Power semiconductor arrangement

Also Published As

Publication number Publication date
JPS5476063A (en) 1979-06-18

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