JPS5842659B2 - transistor warmer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to transistor circuits, particularly C-MO8) transistor circuits.

C-MO8, or complementary metal oxide silicon transistor circuits, are generally said to have sufficient power supply margin, but
For example, when C-MOS circuits are formed on different semiconductor chips and have different power supply voltages, their C-MOS circuits
Connecting circuits together can be problematic.

Figure 1 shows a C-MO8 circuit that constitutes an inverter.
T1 is a P-channel FET (field effect transistor), T
2 is an N-channel FET, which is connected in series between power supply lines 11 and 12.

These gate electrodes are commonly connected to the input terminal IN,
The source electrodes are commonly connected to the output terminal OUT.

The voltage now applied to the power line 1m, 12 is VDD FV
SS (VDD > VSS), the low level of the input voltage vI applied to the terminal IN is vIL, the high level is VIH, and the transistors T1. If the turn-off critical values of T2 are ■TP and ■TN, then the input voltage ■□ is generally the second
As shown by the dotted line in the figure, vI ss+vTI-VIH
〉VDD swings in the range of v'rp, and when vIL, T0 is off, T2 is off, and therefore the output voltage V.

is V. When 2vDD1vIH, T1 is off and T2 is on, VoξVSS, and the former is used as 1"' and the latter as "0".

In this case, one transistor is always off, so C
- The characteristics of low power consumption and high output voltage of the MO8 circuit are retained.

However, as shown by the solid line in Fig. 2, the input voltage V is VI L>VS S+'VT N, VI H<VDD
-VTP, the transistor T1. Both T2 are turned on, and the power supply voltage VDD is applied to the output terminal OUT.
vss to transistor T1. A voltage divided by the gm ratio of T2 is generated, and the inverter no longer operates.

In such a case, the front stage C-MO8 circuit and the rear stage C-MO
Eight circuits are formed on separate semiconductor chips and form part of an integrated circuit, and the power supply voltage of the subsequent chip is greater than the power supply voltage VDD of the previous stage by more than a critical value VTP, and VSS
This occurs when the C-MO8 circuits in the front and rear stages are directly connected when the value is smaller than the critical value VTN.

The present invention is intended to provide an interface means that allows the subsequent stage C-MOS circuit to operate logically as planned even in such a case.

The present invention provides a complementary transistor circuit in which a P-channel field effect transistor and an N-channel field effect transistor are connected in series between power supplies, and an input voltage is commonly applied to the gate electrode of each transistor. A second P-channel field effect transistor and a second N-channel field effect transistor are inserted in series in the series connection portion of each of the N-channel and N-channel transistors, and the series connection point of these second transistors is used as an output terminal. The input voltage is applied to the gate electrode of the 10th transistor, and the 10th transistor
A third ON channel and P channel field effect transistor is provided between each connection point of the channel and N channel field effect transistor and the 20th P channel and N channel field effect transistor and each other power source, and a gate electrode of the third transistor is provided. The input voltage is applied to the input voltage, and depending on the input voltage, one of the third transistors is turned on and the second P-channel or N-channel transistor is turned off. This will now be explained in detail with reference to examples.

FIG. 3 shows an embodiment of the present invention, and as is clear from comparison with FIG. 1, transistors T1. A field effect transistor 'r3jT4 is further connected in series with T2, and the output terminal OUT is taken out from the interconnection point of these transistors T3 and T4.

□In addition, an N-channel field effect transistor T5 is connected between the connection point A of the P-channel field effect transistors T1 and T3 and the power supply v1, and the connection point B of the N-channel field effect transistors T2 and T4 is connected to the power supply v2. A P-channel field effect transistor T6 is connected between these transistors T5. The gate power supply of T6 is connected to the input terminal IN.

In the circuit of FIG. 3, the input voltage V□ is now input to the P-channel transistor T1 as shown in FIG. Critical value V of T3
V3, an N-channel TPI type transistor T2. Critical value of T4 VTN2, VTN
4, these transistors T□~
T4 are all conductive, and as in the case of FIG. 1, a voltage V determined by the gm ratio of transistors T1 to T4 is applied to the output terminal OUT.

appears. However, adding transistor T5,
The voltage of the source power supply V1 (indicated by the same symbol V1).

The same applies hereinafter) is determined appropriately, when the input voltage v1 is at a high level VIH, the transistor T5 is turned on and the connection point A is turned on.
voltage V, to turn off transistor T3.

When transistor T3 is turned off, transistor T1. T
3 circuit is cut off and transistor T2? Since the circuit of T4 is on, the output voltage of the terminal OUT is ■.

Haha it becomes gVSS.

Similarly, when the input voltage is ■□L, transistor T6 is turned on by appropriately selecting voltage ■2, the voltage at connection point B is increased toward voltage V2, transistor T4 is turned off, and transistor T1 is turned on. ．． Since T3 is on, the voltage at the terminal OUT can be set to VDD.

The values of the voltages V11V2 necessary to perform such an operation are as follows: T5 on, T3 . T6 off, T6 on at VIL, 'r4j 'r, off condition VIH+VTP3>
Vl>TIL VTN5VHH+ VT p 6>V
l:> becomes TIL -VTN4.

In this process, VTN, 5 t VTN6 is a transistor 'r
, j' is the turn-off critical value of r6.

When turning on the transistor T or T6 to turn off the transistor T3 or T4, the voltage at the connection point A or B is the same as that between the conducting transistors T1 and T, or T6.
The voltage at the connection point A is higher than the voltage 1, and the voltage at the connection point B is lower than the voltage V2.

This is indicated by a symbol in the above two equations.

If the sides are properly determined so that transistors 'r, j' r6 are completely conductive, transistor T6. The voltage at connection points A and B when T6 is turned on is ■l, and g for v2.
become equal, which causes the voltage v0. ■The 2Q value can also be changed.

In addition to the case where the input voltage V□ falls between the turn-off threshold values of P and N channel transistors as shown in FIG. 4, the present invention can also be applied when the input voltage VDD exceeds the power supply voltage VDD, vsS as shown in FIG. However, in this case, it is necessary to take appropriate measures for the protection diode.

That is, as shown in FIG. 6, in the C-MO8 circuit, a P-type source region 2, a drain region 3, and a P-type channel 4 connecting these are formed on an N-type semicircular substrate 1, and a gate electrode 5 is attached. Then, a P-type head region 6 is formed on the substrate 1, an N-type source region T, a drain region 8, and a channel 9 are formed thereon, and a gate electrode 10 is deposited to form a transistor T2. Furthermore, a P-type head region 11 is formed on the substrate 1 to form a protection diode, and this is connected to the gate electrodes 5 and 1.
0, but when the input voltage vI has a large amplitude as shown in FIG.
There is a risk of causing trouble such as destroying this.

In such a case, a simple measure is to use a diode 1-1.
All you have to do is cut off circuit 1.

Input voltage vI is VIL-VSS or VIH=VDD
It may also be the power supply v1. As V2, the first stage C
- It is possible to use the power supply voltage of the MOS circuit appropriately.

When the input voltage V has a sufficiently large amplitude and is VIH, transistors T1 and T8 are turned off, and when it is VIL, transistors T2 and T8 are turned off. T.

If you can turn off the transistor T'
5. ``'The above on/off operation is performed whether T6 is on or off, so that transistor T6.
Addition of T6 does not result in an equivalent failure.

As is clear from the above description, according to the present invention, by adding transistors T3-1-T6, it is possible to directly connect C-MO6 circuits that operate with different power supply voltages to each other, and ';F:h It is suitable as an interface circuit when a large number of integrated circuits are used, each of which operates at an appropriate power supply voltage.

Brief explanation of the drawings: Fig. 1 is a circuit diagram showing an example of a C-MO8 circuit, Fig. 2 is an explanatory diagram of its operation, Fig. 3 is a circuit diagram of a transistor circuit according to the present invention, and Fig. 4 is its operation. 5 is an explanatory diagram of a large amplitude input voltage, and FIG. 6 is a sectional view showing a specific example of the circuit of FIG. 1.

In the drawing, T, , T2 are P-channel and N-channel field effect transistors, T3 . T4 is the second transistor, T
5. T6 is the third transistor.

Claims (1)

[Claims] 1. In a complementary transistor circuit in which a P-channel field-effect transistor and an N-channel field-effect transistor are connected in series between power supplies, and an input voltage is commonly applied to the gate electrode of each transistor, the first P-channel and N-channel A second P is connected to the series connection of each transistor in the channel.
channel and N-channel field effect transistors are inserted in series, the series connection point of these second transistors is an output terminal, and the input terminal is applied to the gate electrode of these second transistors, and the first P-channel and N-channel field effect transistors and the 20th P
A third ON-channel and P-channel field-effect transistor is provided between each connection point of the channel and N-channel field-effect transistor and each other power source, respectively, and the input voltage is applied to the gate electrode of the third transistor, and the input voltage 1. A transistor circuit, wherein either one of the third transistors is turned on and the second P-channel or N-channel transistor is turned off in response to the above.