JPH0213490B2 - - Google Patents
Info
- Publication number
- JPH0213490B2 JPH0213490B2 JP55059750A JP5975080A JPH0213490B2 JP H0213490 B2 JPH0213490 B2 JP H0213490B2 JP 55059750 A JP55059750 A JP 55059750A JP 5975080 A JP5975080 A JP 5975080A JP H0213490 B2 JPH0213490 B2 JP H0213490B2
- Authority
- JP
- Japan
- Prior art keywords
- input
- circuit
- transistor
- output
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000000295 complement effect Effects 0.000 claims description 9
- 230000005669 field effect Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 5
- 230000010354 integration Effects 0.000 description 1
- 239000008188 pellet Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
Landscapes
- Logic Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electronic Switches (AREA)
Description
【発明の詳細な説明】
本発明は相補型電界効果トランジスタ（以下Ｃ
−MOSという）入力回路に関し、特に一つの入
力端子を大規模集積回路（以下LSIという）の入
力回路として使用すると共にテスト用の入力端子
としても用いることのできるＣ−MOS入力回路
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a complementary field effect transistor (hereinafter referred to as C
The present invention relates to a C-MOS input circuit, and particularly to a C-MOS input circuit in which one input terminal can be used as an input circuit for a large-scale integrated circuit (hereinafter referred to as LSI) and also as an input terminal for testing.
従来、Ｃ−MOS型LSIにおいて、LSIの集積度
の増大に伴つて入出力端子数が増大して来ている
がLSIのチツプサイズの点からは数多くの入出力
端子はチツプサイズの増大をまねく為望ましくな
い、しかしながら、LSIが高集積化して来ると、
LSIの内部回路の良否を判定する為のテスト用の
入力端子が必要になつて来て、入力出端子数をま
すます増加させる欠点があつた。 Conventionally, in C-MOS type LSIs, the number of input/output terminals has increased as the degree of integration of the LSI has increased, but from the point of view of the chip size of the LSI, it is desirable to have a large number of input/output terminals because it increases the chip size. No, however, as LSIs become more highly integrated,
Input terminals for testing to determine the quality of the internal circuits of LSIs have become necessary, which has the disadvantage of increasing the number of input and output terminals.
本発明は上記欠点を除去し、一つの入力端子を
LSIの入力回路として使用すると共にテスト用の
入力端子としても用いることのできる相補型電界
効果トランジスタ入力回路を提供するものであ
る。 The present invention eliminates the above drawbacks and uses one input terminal.
The present invention provides a complementary field effect transistor input circuit that can be used as an input circuit for LSI and also as an input terminal for testing.
本発明の相補型電界効果トランジスタ入力回路
は、一方の主電源が電源の高電位に接続された第
１、第２、第３のＰチヤンネルトランジスタの前
記第１のＰチヤンネルトランジスタの他方の主電
極を第１のＮチヤンネルトランジスタの一方の主
電極に接続してこれを第１の出力とし、前記第１
のＮチヤンネルトランジスタの他方の主電極は電
源の低電位側に接続し、前記第１のＰチヤンネル
トランジスタの制御電極と前記第１のＮチヤンネ
ルトランジスタの制御電極とを共通接続してこれ
を入力端子とし、前記第２のＰチヤンネルトラン
ジスタの他方の主電極を第２のＮチヤンネルトラ
ンジスタの一方の主電極に接続してこれを第２の
出力とし、前記第２のＮチヤンネルトランジスタ
の他方の主電極は電源の低電位側に接続し、前記
第２のＰチヤンネルトランジスタの制御電極と前
記第２のＮチヤンネルトランジスタの制御電極と
前記第３のＰチヤンネルトランジスタの他方電極
とを、他方の電極と制御電極が次段のトランジス
タの一方の電極に接続されている複数段のＰチヤ
ンネルトランジスタの縦積み回路の初段の一方の
電極に接続し、最終段の他方の電極と制御電極と
前記入力端子とを共通接続して構成される。 In the complementary field effect transistor input circuit of the present invention, the other main electrode of the first P-channel transistor of the first, second, and third P-channel transistors has one main power supply connected to a high potential of the power supply. is connected to one main electrode of the first N-channel transistor to make it the first output, and the first
The other main electrode of the N-channel transistor is connected to the low potential side of the power supply, and the control electrode of the first P-channel transistor and the control electrode of the first N-channel transistor are commonly connected and used as an input terminal. the other main electrode of the second P-channel transistor is connected to one main electrode of the second N-channel transistor to provide a second output; is connected to the low potential side of the power supply, and connects the control electrode of the second P-channel transistor, the control electrode of the second N-channel transistor, and the other electrode of the third P-channel transistor to the other electrode and the control electrode of the third P-channel transistor. The electrode is connected to one electrode of the first stage of a vertically stacked circuit of multiple stages of P-channel transistors, the electrode of which is connected to one electrode of the next stage transistor, and the other electrode of the final stage, the control electrode, and the input terminal are connected. Configured with common connections.
本発明を実施例により説明する。 The present invention will be explained by examples.
第１図は本発明の第一の実施例の回路図、第２
図ａ〜ｃは第１図に示す回路を動作させたときに
各部に現われる信号のタイムチヤートであつて、
ａ図、ｂ図、ｃ図はそれぞれ端子１２，１３，１
４に現われる信号の波形を示す。 FIG. 1 is a circuit diagram of the first embodiment of the present invention, and FIG.
Figures a to c are time charts of signals appearing in various parts when the circuit shown in Figure 1 is operated.
Figures a, b, and c are terminals 12, 13, and 1, respectively.
4 shows the waveform of the signal appearing in FIG.
第１図においてＰチヤンネルトランジスタ（以
下Ｐ−Trという）１とＮチヤンネルトランジス
タ（以下Ｎ−Trという）２は通常のＣ−MOSイ
ンバータを構成している。Ｐ−Tr５はＰ−Tr
６，７，８，９の縦積み回路の負荷MOSトラン
ジスタであり、ソース電極を電源の高電位側の＋
VDD（以下“Ｈ”レベルという）に接続し、ゲー
トは電源の低電位側の−VSS（以下“Ｌ”レベルと
いう）に接続する。Ｐ−Tr３，４は節点１１の
電圧レベルを検出するためのＣ−MOSインバー
タである。１２は入力端子、１３，１４はそれぞ
れ通常信号の入力回路の出力端子とテスト信号の
入力回路の出力端子である。 In FIG. 1, a P channel transistor (hereinafter referred to as P-Tr) 1 and an N channel transistor (hereinafter referred to as N-Tr) 2 constitute a normal C-MOS inverter. P-Tr5 is P-Tr
It is a load MOS transistor in a vertically stacked circuit of 6, 7, 8, and 9, and the source electrode is connected to the high potential side of the power supply (+).
It is connected to V DD (hereinafter referred to as "H" level), and its gate is connected to -V SS (hereinafter referred to as "L" level) on the low potential side of the power supply. P-Trs 3 and 4 are C-MOS inverters for detecting the voltage level of node 11. 12 is an input terminal, and 13 and 14 are output terminals of a normal signal input circuit and a test signal input circuit, respectively.
今、入力端子１２に“Ｌ”レベルが入力される
と、Ｐ−Tr１はオンして通常信号の入力回路の
出力端子１３には“Ｈ”レベルが現われる。Ｐ−
Tr５はゲートに“Ｌ”レベルが加わつているの
でオンしており、Ｐ−Tr６，７，８，９の縦積
み回路の入力端子１２には“Ｌ”レベルが加わつ
ていて縦積み回路の各トランジスタのゲートはト
ランジスタ自身のドレイン（又はソース）と次段
のトランジスタのソース（又はドレイン）と接続
されているので、各トランジスタのゲート電圧は
直列接続されることになり、この縦積み回路をオ
ンさせるには各トランジスタのVTの和より高い
電圧を節点１１と入力端子１２に加えなければな
らない。このVTの和を電源電圧差以上になる様
に縦積みトランジスタの段数を設定しておけば入
力端子１２に“Ｌ”レベルが入力された時、縦積
みＰ−Tr６，７，８，９はオフし、節点１１の
レベルは“Ｈ”レベルになり、Ｎ−Tr４がオン
するので出力端子１４に“Ｌ”レベルが現われ
る。 Now, when the "L" level is input to the input terminal 12, the P-Tr1 is turned on and the "H" level appears at the output terminal 13 of the normal signal input circuit. P-
Tr5 is turned on because "L" level is applied to its gate, and "L" level is applied to the input terminal 12 of the vertically stacked circuit of P-Trs 6, 7, 8, and 9, so that the vertically stacked circuit is turned on. Since the gate of each transistor is connected to the drain (or source) of the transistor itself and the source (or drain) of the next transistor, the gate voltage of each transistor is connected in series, and this vertically stacked circuit is To turn it on, a voltage higher than the sum of V T of each transistor must be applied to node 11 and input terminal 12. If the number of stages of vertically stacked transistors is set so that the sum of V is turned off, the level of node 11 becomes "H" level, and N-Tr4 is turned on, so that "L" level appears at output terminal 14.
次に、入力端子１２に“Ｈ”レベルが加わると
Ｎ−Tr２がオンし、出力端子１３には“Ｌ”レ
ベルがあらわれる。縦積みトランジスタ回路には
各トランジスタのVTの和より大きな電圧は加わ
つていないため、Ｐ−Tr６，７，８，９はオフ
しており、前と同様に出力端子１４は“Ｌ”レベ
ルであり変化しない。 Next, when the "H" level is applied to the input terminal 12, the N-Tr2 is turned on, and the "L" level appears at the output terminal 13. Since no voltage greater than the sum of V T of each transistor is applied to the vertically stacked transistor circuit, P-Trs 6, 7, 8, and 9 are off, and the output terminal 14 is at the "L" level as before. and does not change.
この様に、通常の信号レベルが入力されている
時は出力端子１４には“Ｈ”レベルは現われず、
テスト用出力信号は発生されない。そこで、入力
端子１２“Ｌ”レベルより低い電圧レベル−
Vtestをテスト信号として入力すると、Ｐ−Tr１
がオンし、出力端子１３の出力は“Ｈ”レベルと
なり、Ｐ−Trの縦積み回路には電源電圧＋Vtest
の電圧が加わつており、この電圧が縦積みトラン
ジスタ回路のVTの和より大きくなるようにテス
ト信号レベルをテスト信号として入力すると、Ｐ
−Tr６，７，８，９の各ゲートにはVT以上の電
圧が加わり、トランジスタはオンするのでＰ−
Tr５を通して縦積みトランジスタ回路には電流
が流れる。節点１１の電位はＰ−Tr５のオン抵
抗とＰ−Tr６，７，８，９のオン抵抗の比で決
定される。この抵抗比を適当に選ぶことによつて
Ｐ−Tr３をオンさせることができ、出力端子１
４には“Ｈ”レベルが現われテスト信号出力を発
生する。 In this way, when a normal signal level is input, "H" level does not appear at the output terminal 14,
No test output signal is generated. Therefore, the voltage level lower than the "L" level of input terminal 12 -
When V test is input as a test signal, P-Tr1
is turned on, the output of the output terminal 13 becomes "H" level, and the power supply voltage +V test is applied to the vertically stacked P-Tr circuit.
voltage is applied, and if the test signal level is input as a test signal so that this voltage is greater than the sum of V T of the vertically stacked transistor circuit, P
- A voltage higher than V T is applied to each gate of Tr6, 7, 8, and 9, and the transistor is turned on, so P-
Current flows through the vertically stacked transistor circuit through Tr5. The potential of the node 11 is determined by the ratio of the on-resistance of the P-Tr 5 to the on-resistance of the P-Trs 6, 7, 8, and 9. By appropriately selecting this resistance ratio, P-Tr3 can be turned on, and output terminal 1
4, the "H" level appears and a test signal output is generated.
この様に、縦積み回路のＰ−TrのVTの和を電
源電圧より大きくし、テスト信号と電源電圧の和
よりも小さくなる様に縦積み段数及びテスト信号
レベルを設定し、節点１１のレベルがＰ−Tr４
をオンできるようなレベルになるように、Ｐ−
Tr５のオン抵抗とＰ−Tr６，７，８，９のオン
抵抗の和の比を設定することにより、通常の信号
が入力された時には通常の出力信号が発生し、テ
スト信号が入力された時にはテスト用出力信号が
発生する入力回路を構成できる。 In this way, the number of vertically stacked stages and the test signal level are set so that the sum of V T of the P-Trs of the vertically stacked circuit is larger than the power supply voltage and smaller than the sum of the test signal and the power supply voltage, and the Level is P-Tr4
P-
By setting the ratio of the on-resistance of Tr5 and the sum of the on-resistances of P-Tr6, 7, 8, and 9, a normal output signal is generated when a normal signal is input, and a normal output signal is generated when a test signal is input. An input circuit that generates test output signals can be configured.
本発明の入力回路は縦積み段数を変えることに
より複数のテスト信号入力を同一入力端子から入
力できる。 The input circuit of the present invention can input a plurality of test signals from the same input terminal by changing the number of vertically stacked stages.
第３図は本発明の第二の実施例の回路図、第４
図ａ〜ｅは第３図に示す回路を動作させたとき各
部に現われる信号のタイムチヤートであつて、
ａ，ｂ，ｃ，ｄ，ｅはそれぞれ端子３４，３７，
３８，３９，４０に現われる信号の波形を示す。 FIG. 3 is a circuit diagram of the second embodiment of the present invention, and FIG.
Figures a to e are time charts of signals appearing in various parts when the circuit shown in Figure 3 is operated.
a, b, c, d, e are terminals 34, 37, respectively.
The waveforms of the signals appearing at 38, 39, and 40 are shown.
第３図において、３０は通常信号の入力回路、
３７はその出力端子３１，３２，３３はそれぞれ
V1（Ｖ）、V2（Ｖ）、V3（Ｖ）の入力しきい値を持
つテスト用入力回路であり、V1＞V2＞V3となつ
ている。３５はテスト用入力回路３１，３２の出
力を入力とする排他的論理和（以下EX−ORと
いう）、３６はテスト用入力回路３２，３３の出
力を入力とするEX−ORである。 In FIG. 3, 30 is a normal signal input circuit;
37 has its output terminals 31, 32, and 33, respectively.
This is a test input circuit having input threshold values of V 1 (V), V 2 (V), and V 3 (V), with V 1 >V 2 >V 3 . 35 is an exclusive OR (hereinafter referred to as EX-OR) whose inputs are the outputs of the test input circuits 31 and 32, and 36 is an EX-OR whose inputs are the outputs of the test input circuits 32 and 33.
今、入力端子３４に通常の信号レベルが加わる
と、すでに説明したように、出力端子３７に出力
信号が発生するが、テスト信号レベルがV1（Ｖ）
という信号が入力端子３４に入力されると３１の
入力回路の出力だけ“Ｈ”レベルになり他はすべ
て“Ｌ”レベルであるのでEX−OR３５の出力
は“Ｈ”レベルでEX−OR３６の出力は“Ｌ”
レベルとなり、出力端子３８だけに出力信号が発
生される。 Now, when a normal signal level is applied to the input terminal 34, an output signal is generated at the output terminal 37 as described above, but the test signal level is V 1 (V).
When this signal is input to the input terminal 34, only the output of the input circuit 31 becomes "H" level and all others are "L" level, so the output of EX-OR35 is "H" level and the output of EX-OR36 is “L”
level, and an output signal is generated only at the output terminal 38.
同様に、V2（Ｖ）のテスト信号が加わると、出
力端子３９にのみ出力信号が発生し、V3（Ｖ）の
テスト信号が加わると、出力端４０にだけ出力信
号が発生する。 Similarly, when a test signal of V 2 (V) is applied, an output signal is generated only at the output terminal 39, and when a test signal of V 3 (V) is applied, an output signal is generated only at the output terminal 40.
以上詳細に説明したように、本発明によれば、
通常入力信号とテスト信号とを同一の端子から入
力することができるので、LSIのテスト端子を大
幅に削減できペレツトサイズの縮小化を図ること
ができるのでその効果は大きい。 As explained in detail above, according to the present invention,
Since the normal input signal and the test signal can be input from the same terminal, the number of LSI test terminals can be greatly reduced and the pellet size can be reduced, which is very effective.
第１図は本発明の第一の実施例の回路図、第２
図ａ〜ｃは第１図に示す回路を動作させたとき各
部に現われる信号のタイムチヤート、第３図は本
発明の第二の実施例の回路図、第４図ａ〜ｅは第
３図に示す回路を動作させたとき各部に現われる
信号のタイムチヤートである。
１……Ｐチヤンネルトランジスタ、２……Ｎチ
ヤンネルトランジスタ、３……Ｐチヤンネルトラ
ンジスタ、４……Ｎチヤンネルトランジスタ、
５，６，７，８，９……Ｐチヤンネルトランジス
タ、１２……入力端子、１３，１４……出力端
子、３０……通常信号の入力回路、３１，３２，
３３……テスト信号の入力回路、３５，３６……
排他的論理和（EX−OR）、３７……通常信号の
出力端子、３８，３９，４０……テスト信号の出
力端子。
FIG. 1 is a circuit diagram of the first embodiment of the present invention, and FIG.
Figures a to c are time charts of signals appearing in various parts when the circuit shown in Figure 1 is operated, Figure 3 is a circuit diagram of the second embodiment of the present invention, and Figures 4 a to e are diagrams of Figure 3. This is a time chart of the signals that appear in each part when the circuit shown in is operated. 1...P channel transistor, 2...N channel transistor, 3...P channel transistor, 4...N channel transistor,
5, 6, 7, 8, 9... P channel transistor, 12... Input terminal, 13, 14... Output terminal, 30... Normal signal input circuit, 31, 32,
33... Test signal input circuit, 35, 36...
Exclusive OR (EX-OR), 37... Normal signal output terminal, 38, 39, 40... Test signal output terminal.
Claims (1)
タ回路と、電源間に接続された第２の相補型トラ
ンジスタ回路と、前記第１の相補型トランジスタ
回路の入力端に接続された入力信号端子と、一端
が電源の一方に接続されゲートが電源の他端に接
続された一導電源の第１のトランジスタと、前記
第１のトランジスタと同一導電源でかつダイオー
ド接続されたトランジスタを複数個縦続接続した
縦続接続回路と、該縦続接続回路の一端を前記第
１のトランジスタの他端および前記第２の相補型
トランジスタ回路の入力端に接続し、前記縦続接
続回路の他端を前記入力信号端子に接続する手段
とを有し、入力信号として電源電圧レベルに等し
い信号が入力された時は前記第１の相補型トラン
ジスタ回路から出力がとり出され、入力信号とし
て前記電源電圧レベルを超える電圧のテスト信号
が入力された時は前記第２の相補型トランジスタ
回路から出力がとり出されるようにしたことを特
徴とする電界効果トランジスタ集積回路。1 a first complementary transistor circuit connected between the power supplies, a second complementary transistor circuit connected between the power supplies, and an input signal terminal connected to the input end of the first complementary transistor circuit; , a first transistor with a single conductive power source, one end of which is connected to one end of the power source and a gate connected to the other end of the power source, and a plurality of transistors connected in cascade and each having the same conductive power source as the first transistor and which are diode-connected. one end of the cascaded circuit is connected to the other end of the first transistor and the input terminal of the second complementary transistor circuit, and the other end of the cascaded circuit is connected to the input signal terminal. and a means for connecting, when a signal equal to the power supply voltage level is input as an input signal, an output is taken from the first complementary transistor circuit, and a voltage exceeding the power supply voltage level is tested as an input signal. A field effect transistor integrated circuit, characterized in that when a signal is input, an output is taken out from the second complementary transistor circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5975080A JPS56156023A (en) | 1980-05-06 | 1980-05-06 | Complementary field effect transistor input circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5975080A JPS56156023A (en) | 1980-05-06 | 1980-05-06 | Complementary field effect transistor input circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56156023A JPS56156023A (en) | 1981-12-02 |
| JPH0213490B2 true JPH0213490B2 (en) | 1990-04-04 |
Family
ID=13122224
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5975080A Granted JPS56156023A (en) | 1980-05-06 | 1980-05-06 | Complementary field effect transistor input circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56156023A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61201517A (en) * | 1985-03-04 | 1986-09-06 | Mitsubishi Electric Corp | Semiconductor device |
| JPH01202025A (en) * | 1988-02-08 | 1989-08-15 | Mitsubishi Electric Corp | Mode switching circuit |
-
1980
- 1980-05-06 JP JP5975080A patent/JPS56156023A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56156023A (en) | 1981-12-02 |
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