JPS5843901B2 - Plating thickness measurement method - Google Patents
Plating thickness measurement methodInfo
- Publication number
- JPS5843901B2 JPS5843901B2 JP3628977A JP3628977A JPS5843901B2 JP S5843901 B2 JPS5843901 B2 JP S5843901B2 JP 3628977 A JP3628977 A JP 3628977A JP 3628977 A JP3628977 A JP 3628977A JP S5843901 B2 JPS5843901 B2 JP S5843901B2
- Authority
- JP
- Japan
- Prior art keywords
- plating
- thickness
- pattern
- plating thickness
- patterns
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Length Measuring Devices With Unspecified Measuring Means (AREA)
- Electroplating Methods And Accessories (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
【発明の詳細な説明】
本発明は、半導体装置に形成したメッキ層の厚さを測定
するのに好適な方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method suitable for measuring the thickness of a plating layer formed on a semiconductor device.
一般に、半導体装置では所要部分に金属をメッキして電
極・配線とすることは数多く行なわれている。In general, in semiconductor devices, required portions are often plated with metal to form electrodes and wiring.
ところが、そのメッキ厚を比較的正確に、また、簡易に
測定する適切な手段がないため、それ等電極・配線に要
求される電気的特性、機械的特性を大幅に越える許容範
囲を以って形成されている。However, since there is no appropriate means to relatively accurately and easily measure the plating thickness, it is difficult to measure the plating thickness with tolerances that greatly exceed the electrical and mechanical properties required for electrodes and wiring. It is formed.
しかしながら、この電極・配線が安価な材料で形成され
るのであれば問題は少ないが、例えばビーム・リード方
式の半導体装置に於ける如く、金Auをメッキする場合
には、コストに大きな影響を与える。However, if these electrodes and wiring are made of inexpensive materials, there will be no problem, but if gold-Au is plated, as in the case of beam-lead type semiconductor devices, for example, it will have a significant impact on the cost. .
通常、ビーム・リードは10〜20μm1内部配線は1
〜5岬の厚さに金メッキを行なっている。Normally, the beam lead is 10 to 20 μm, and the internal wiring is 1
Gold plating is applied to a thickness of ~5 capes.
従来、半導体装置に於ける金属メッキの厚さ測定が全く
行なわれていないわけではないが、何分にも半導体装置
の表面は一様ではないし、また、パターンも微細である
から、例えばノギスを用いる等の機械的手法を利用する
ことは困難である。It is not that the thickness of metal plating on semiconductor devices has not been measured in the past, but since the surface of semiconductor devices is often uneven and the patterns are minute, it is difficult to measure the thickness of metal plating on semiconductor devices. It is difficult to use mechanical methods such as
本発明は、顕微鏡観察に依り、比較的正確に、しかも、
簡易にメッキ厚を測定できるようにするものであり、以
下これを詳細に説明する。The present invention relies on microscopic observation, relatively accurately, and
This allows the plating thickness to be easily measured, and will be explained in detail below.
一般に、メッキすべき部分上に厚さtpμmのフォトレ
ジスト膜でパターンを形成し、その後、厚さtμmの金
メッキを行なうと蔦それぞれのパターンに於けるメッキ
は、そのパターン・エツジから、厚さと垂直な方向にt
−t pμmだけ拡がることが知られている。Generally, if a pattern is formed using a photoresist film with a thickness of tμm on the part to be plated, and then gold plating is performed with a thickness of tμm, the plating in each pattern will be perpendicular to the thickness from the edge of the pattern. t in the direction
-t pμm is known to spread.
本発明ではこの現象を利用する。The present invention utilizes this phenomenon.
即ち、半導体装置の適所に、フォト・レジスト膜を用い
て少なくとも二つのモニタ・パターンを所定フォト・マ
スクに依り一度に並設し、その後、電極・配線等のメッ
キと同時にそのパターンにもメッキし、メッキ皮膜に依
る各パターン間の間隙の挟まり王台に依ってメッキ厚さ
を判定するものである。That is, at least two monitor patterns are placed side by side at the same time using a photoresist film at appropriate locations on a semiconductor device using a predetermined photomask, and then those patterns are plated at the same time as the electrodes, wiring, etc. are plated. The plating thickness is determined based on the size of the gap between each pattern due to the plating film.
各パターン間の間隙は、同一フォトマスクで形成される
ものであるから、高精度で一定に形成でき、また、その
寸法を予じめ知ることは容易である。Since the gaps between each pattern are formed using the same photomask, they can be formed uniformly with high precision, and it is easy to know the dimensions in advance.
尚、パターン間隙がメッキに依って狭まる程度はメッキ
工程の途中で随時顕微鏡で観察するものである。The extent to which the pattern gap narrows due to plating is to be observed with a microscope at any time during the plating process.
第1図はメッキ厚を測定する為のパターン近傍の平面図
、第2図は線A−A’に於ける断面図、第3図は線B−
B’に於ける断面図をそれぞれ表わし、また、a−dは
メッキ工程の進行過程を表わしている。Figure 1 is a plan view of the vicinity of the pattern used to measure plating thickness, Figure 2 is a sectional view taken along line A-A', and Figure 3 is taken along line B-
Each of the cross-sectional views at B' is shown, and ad represents the progress of the plating process.
a参照
今、シリコン半導体基板1上に二酸化シリコン膜2、チ
タン膜3、白金膜4が形成されているものとする。Refer to a. It is now assumed that a silicon dioxide film 2, a titanium film 3, and a platinum film 4 are formed on a silicon semiconductor substrate 1.
尚、チタン膜3は電極・配線の一部であるから、適当箇
所で二酸化シリコン膜2に形成された電極コンタクト窓
を介して基板1に接触していることは云うまでもない。Incidentally, since the titanium film 3 is a part of the electrode/wiring, it goes without saying that it is in contact with the substrate 1 through the electrode contact window formed in the silicon dioxide film 2 at an appropriate location.
さて、白金膜4上にフォト・レジスト膜5を形成し、そ
のフォト・レジスト膜5のパターニングを行なって所望
のメッキパターンと同時にモニタ・パターン6.7を形
成する。Now, a photoresist film 5 is formed on the platinum film 4, and the photoresist film 5 is patterned to form a monitor pattern 6.7 at the same time as a desired plating pattern.
尚、パターン6はパターン7との対向縁に切欠部6Aを
有している。Note that the pattern 6 has a notch 6A on the edge opposite to the pattern 7.
この切欠部6Aはメッキ厚の限界値を測定する為のもの
であるが、その測定に然程精度を要しない場合は形成し
なくとも良い。This notch 6A is for measuring the limit value of the plating thickness, but it may not be formed if the measurement does not require much precision.
尚、本実施例に於けるパターン6.7は方形を基礎とし
ているが、その形状はこれに限定されるものではなく、
要は二つのパターンの間隙が一定に維持され、また、観
察容易なものであれば良い。Note that although the pattern 6.7 in this example is based on a rectangle, its shape is not limited to this.
The point is that the gap between the two patterns can be maintained constant and can be easily observed.
本実施例では、第2図aの距離lは26μm1第3図a
の距離l′は32μmとなるようにパターン6.7を形
成した。In this example, the distance l in Figure 2 a is 26 μm1 in Figure 3 a
Pattern 6.7 was formed so that the distance l' was 32 μm.
また、フォト・レジスト膜5の厚さは0.5μmであり
、最終的には厚さ15±1.5μmの全皮膜8の形成を
四指している。Further, the thickness of the photoresist film 5 is 0.5 μm, and it is intended that the entire film 8 will ultimately have a thickness of 15±1.5 μm.
b参照 図示例のメッキ厚は13.5μm以下である。See b. The plating thickness in the illustrated example is 13.5 μm or less.
C参照 図示例のメッキ厚は15±0.5μmである。See C. The plating thickness in the illustrated example is 15±0.5 μm.
この場合、切欠部6Aの影響に依る目視の容易さは顕著
である。In this case, the ease of visual inspection due to the effect of the notch 6A is remarkable.
d参照 図示例のメッキ厚は16.5μm以上である。d reference The plating thickness in the illustrated example is 16.5 μm or more.
従ってメッキ作業はCの状態で完了させると良い。Therefore, it is best to complete the plating work in state C.
前記実施例ではモニタ・パターンが6と7の二つであっ
たが、その数は適当に選択できる。In the above embodiment, there were two monitor patterns, 6 and 7, but the number can be selected appropriately.
そして、例えばパターン6を二つに分割した場合には、
メッキの限界値を判定する切欠部6Aの形成を止め、二
つのパターン6の間に形成される間隙を適当に選択し、
その間隙が金メッキに依って埋められる程度と、パター
ン6とパターン7との間隙が埋められる程度とを比較し
て限界値を判定することもできる。For example, if pattern 6 is divided into two,
Stop the formation of the notch 6A for determining the plating limit value, appropriately select the gap formed between the two patterns 6,
The limit value can also be determined by comparing the degree to which the gap is filled by gold plating and the degree to which the gap between pattern 6 and pattern 7 is filled.
また、本発明は実施例に限られず、メッキ厚の測定全般
に関して適用することができる。Further, the present invention is not limited to the embodiments, and can be applied to general measurement of plating thickness.
以上の説明で判るように、本発明に依れば、半導体装置
の適所に少なくとも二つのモニタ・パターンを所望のメ
ッキパターンと同時に形成し、そのモニタ・パターンに
対するメッキの状態を目視することに依り、かなり正確
に、また、容易にメッキ厚を知得することができるので
、要求される緒特性を大幅に越えるような無駄なメッキ
を行なうことがなくなり、製造時間の短縮は勿論のこと
、メッキ材料が高価である場合にはコストの低減に大き
な威力を発揮する。As can be seen from the above explanation, according to the present invention, at least two monitor patterns are formed at appropriate locations on a semiconductor device at the same time as a desired plating pattern, and the state of plating with respect to the monitor patterns is visually observed. Since the plating thickness can be determined fairly accurately and easily, there is no need to perform unnecessary plating that greatly exceeds the required properties, which not only shortens manufacturing time, but also improves the plating material. This is a great way to reduce costs when the cost is high.
第1図a = dは本発明の一例を実施する過程を説明
する為の半導体装置の要部平面図、第2図a〜dは第1
図の線A−A′に於ける断面図、第3図a=dは第1図
の線B−B’に於ける断面図をそれぞれ表わす。
図に於いて、1は基板、2は二酸化シリコン膜、3はチ
タン膜、4は白金膜、5はフォトレジスト膜、6,7は
パターン、8は全皮膜、6Aは切欠部をそれぞれ示す。FIG. 1 a = d is a plan view of the main part of a semiconductor device for explaining the process of implementing an example of the present invention, and FIGS.
A cross-sectional view taken along the line A-A' in the figure, and FIG. 3 a=d represent a cross-sectional view taken along the line B-B' in FIG. 1, respectively. In the figure, 1 is a substrate, 2 is a silicon dioxide film, 3 is a titanium film, 4 is a platinum film, 5 is a photoresist film, 6 and 7 are patterns, 8 is the entire film, and 6A is a cutout.
Claims (1)
レジスト膜をパターニングして少なくとも二つのモニタ
・パターンを所定間隔を保って対向形成し、しかる後メ
ッキを必要とする部分へのメッキと同時に前記モニタ・
パターンにもメッキを行なってそれ等モニタ・パターン
間の間隙がメッキされた金属で狭められる状態を観察し
てメッキ厚の測定を行なうことを特徴とするメッキ厚測
定方法。1 Form a photoresist film on the substrate, and
The resist film is patterned to form at least two monitor patterns facing each other at a predetermined interval, and then the monitor patterns are simultaneously plated on the areas that require plating.
A plating thickness measuring method characterized in that the plating thickness is measured by plating the patterns and observing the state in which the gap between the monitor patterns is narrowed by the plated metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3628977A JPS5843901B2 (en) | 1977-03-30 | 1977-03-30 | Plating thickness measurement method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3628977A JPS5843901B2 (en) | 1977-03-30 | 1977-03-30 | Plating thickness measurement method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS53120381A JPS53120381A (en) | 1978-10-20 |
| JPS5843901B2 true JPS5843901B2 (en) | 1983-09-29 |
Family
ID=12465625
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3628977A Expired JPS5843901B2 (en) | 1977-03-30 | 1977-03-30 | Plating thickness measurement method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5843901B2 (en) |
-
1977
- 1977-03-30 JP JP3628977A patent/JPS5843901B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS53120381A (en) | 1978-10-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5347226A (en) | Array spreading resistance probe (ASRP) method for profile extraction from semiconductor chips of cellular construction | |
| JPH0594933A (en) | Alignment check pattern | |
| JPH0321901B2 (en) | ||
| DE1303674C2 (en) | MAGNETIC THICKNESS GAUGE | |
| JPS5843901B2 (en) | Plating thickness measurement method | |
| DE4228795A1 (en) | Rotation rate sensor formed from silicon@ wafer - has axis of vibration perpendicular to surface of wafer, and accelerometer perpendicular to vibration axis | |
| JPS6219707A (en) | Method for measuring film thickness | |
| JPH08285502A (en) | Reference sample for distance and step | |
| JPS63228010A (en) | Method for measuring depth of groove in semiconductor | |
| DE69207213T2 (en) | Method of measuring the displacement of a pattern | |
| DE69110427T2 (en) | Method of measuring the displacement of a pattern. | |
| DE69803660T2 (en) | ELKETROSTATIC ADHESIVITY TESTER FOR THIN-LAYER LADDER | |
| JP2570130B2 (en) | Pattern for measuring film thickness and method for measuring film thickness | |
| JPS6030099B2 (en) | Etching gradient determination method | |
| DE102011012981B3 (en) | Standard hybrid spherical cap for calibration of coordinate measuring machine, has recess whose edge extends from slope of acute angle to planar measuring surface such that calotte is provided in contact points at another edge | |
| JPH0729952A (en) | MOS semiconductor device and alignment inspection method using the same | |
| JPH0348190A (en) | Electron beam diameter and current density measuring device | |
| JPS60217642A (en) | Method for detection of fine pattern | |
| DE19935907C2 (en) | Calibration body for ultrasound microscopes | |
| JPH03127848A (en) | Semiconductor device | |
| JPH025404A (en) | Measurement of photoresist layer pattern | |
| JPS6127632A (en) | Etching process | |
| JPH01265532A (en) | Interlayer insulation film evaluation pattern | |
| JPH07249667A (en) | Film thickness measurement method of interlayer film in multilayer wiring | |
| JP3890919B2 (en) | Manufacturing method of semiconductor device |