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JPS6030099B2 - Etching gradient determination method - Google Patents
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JPS6030099B2 - Etching gradient determination method - Google Patents

Etching gradient determination method

Info

Publication number
JPS6030099B2
JPS6030099B2 JP51019390A JP1939076A JPS6030099B2 JP S6030099 B2 JPS6030099 B2 JP S6030099B2 JP 51019390 A JP51019390 A JP 51019390A JP 1939076 A JP1939076 A JP 1939076A JP S6030099 B2 JPS6030099 B2 JP S6030099B2
Authority
JP
Japan
Prior art keywords
etching
thin film
insulating thin
groove
slope
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP51019390A
Other languages
Japanese (ja)
Other versions
JPS52103963A (en
Inventor
大夫 長沼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP51019390A priority Critical patent/JPS6030099B2/en
Publication of JPS52103963A publication Critical patent/JPS52103963A/en
Publication of JPS6030099B2 publication Critical patent/JPS6030099B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)

Description

【発明の詳細な説明】 半導体装置の製造に際して、絶縁薄膜を彼膜した後、金
属配線の写真蝕刻を行なう際に、絶縁薄膜の側面を、半
導体チップ表面に対して、90度以下の所定の煩度を有
してエッチングをほどこすことが行われている。
DETAILED DESCRIPTION OF THE INVENTION During the manufacture of semiconductor devices, after depositing an insulating thin film, when photo-etching metal wiring, the side surface of the insulating thin film is placed at a predetermined angle of 90 degrees or less with respect to the semiconductor chip surface. Etching is carried out with a certain degree of tediousness.

これは、絶縁薄膜の側面が半導体基板表面に対して殆ど
垂直にエッチング処理された後、金属蒸着により金属配
線を形成すること、金属配線に断線が生ずることがあり
、この断線を防止するための処置である。しかし、頻度
があまり小さすぎると、傾斜部の基板と平行な方向の長
さ、すなわち傾斜中が大きくなることにより、所定部以
外の部分における膜厚が薄くなることにより、該部の破
壊電圧が低下したり、素子が密に集積している装置にお
いては、他素子部をも同時に蝕刻してしまうことがある
ため、額度は、ある所定の範囲内におさまるように設け
なければならない。
This is because metal wiring is formed by metal evaporation after the side surface of the insulating thin film is etched almost perpendicular to the semiconductor substrate surface, which may cause disconnection in the metal wiring, and measures are taken to prevent this disconnection. It is a treatment. However, if the frequency is too small, the length of the inclined part in the direction parallel to the substrate, that is, the part of the inclined part, will increase, and the film thickness will become thinner in parts other than the designated parts, which will reduce the breakdown voltage in those parts. In devices where the thickness of the device is lowered or where elements are densely integrated, other elements may be etched at the same time, so the forehead must be set so as to fall within a certain predetermined range.

現在この懐度エッチング処理をほどこす方法として、絶
縁薄膜の表面にエッチング速度の高い物質を所望の煩度
に応じて彼着したり、又、薄膜表面をエッチング速度の
高い物質に適当な方法で変化させた後にエッチング処理
をほどこすということが行われているが、これは、非常
に精度を要求されるものであり、現在の技術水準では、
膜厚を一定と仮定しても薄膜表面の状況などにより常に
一定の額度をもった懐斜エッチング処理をほどこすこと
は不可能とされ、ある程度の誤差が出てくるのは必然と
されている。又傾斜エッチング処理をほどこす際には薄
膜の厚さを正確にコントロールする事も重要であるが、
これは、基板表面の状態などに多少影響され、1ロット
中のウエフアーについては10%、ロットごとには20
〜30%程度のばらつきがある。上記のような状況のも
とに製造された半導体装置のエッチンゲ頃度の不適当な
ことによる不良品は、5%程度である。又、頻度の測定
は、不良品か否かの判断に有用であると同時に、不良品
の原因追求に対しても重要である。
Currently, there are methods for applying this deep etching process, such as applying a substance with a high etching rate to the surface of the insulating thin film depending on the desired degree of etching, or applying a substance with a high etching rate to the surface of the thin film using an appropriate method. Etching is performed after the change, but this requires great precision, and with the current state of technology,
Even assuming that the film thickness is constant, it is said that it is impossible to perform an oblique etching process with a constant thickness due to factors such as the condition of the thin film surface, and it is inevitable that some error will occur. . It is also important to accurately control the thickness of the thin film when performing inclined etching.
This is somewhat influenced by the condition of the substrate surface, etc., and is 10% for wafers in one lot and 20% for each lot.
There is a variation of about 30%. The percentage of defective products due to inappropriate etching of semiconductor devices manufactured under the above-mentioned conditions is about 5%. Furthermore, measuring the frequency is not only useful for determining whether a product is defective, but also important for investigating the cause of a defective product.

従来、上記のような値度の測定方法として、代表的なも
のに、まず絶縁薄膜の厚さtを、光の千渉などを利用し
て求めた後、頚。
Conventionally, as a typical method for measuring the above-mentioned value, first, the thickness t of the insulating thin film is determined using a beam of light, etc., and then the neck is measured.

徴計を用いて、鏡肌dを実欄こよ啄め、額度8を8=肌
−さより求めていた。前記測定法によれば、頚。
Using a scale, I checked the mirror skin d on the real column and found the forehead degree 8 from 8=skin. According to the measurement method, the neck.

徴計により、傾斜部の中を実測するという作業は、非常
に手間のかかることであり、かつ熟練と精度とを要求さ
れる作業であるという欠点があった。本発明は上記のよ
うな欠点を解消し、簡単に、所定の煩度内にあるかどう
かを判定しうるエッチング傾度判定方法を提供すること
を目的とする。
The work of actually measuring the inside of a slope using a survey has the disadvantage that it is very time-consuming and requires skill and precision. SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for determining an etching gradient, which eliminates the above-mentioned drawbacks and can easily determine whether or not the etching degree is within a predetermined degree of complexity.

本発明を好ましい実施例にもとづいて説明する。第1図
は、本発明半導体装置に際して絶縁薄膜上に被着したレ
ジスト膜1の一部に孔部が設けられていることを示す平
面図である。孔部2と3は最小許容傾斜中bを隔てて設
けられており、孔部3と4は最小許容傾斜中bを隔てて
設けられている。前記最大許容傾斜中a及び、最小許容
傾斜中bは、薄膜の厚さ及びそのばらつきも考慮して所
定の煩度例えば15〜20oという値から決定される。
上記の構造となるように、レジスト膜1に孔部2,3,
4を設け、エッチング処理をほどこすと、半導体装置の
基板5の表面に設けられた絶縁薄膜6の表面を2層構造
として上層の方が下層に比べてエッチング速度の速い材
料例えばポリシリコンと2酸化珪素との2層としている
ため横方向の蝕刻が垂直方向の蝕刻よりも速く行われる
The present invention will be explained based on preferred embodiments. FIG. 1 is a plan view showing that a hole is provided in a part of a resist film 1 deposited on an insulating thin film in the semiconductor device of the present invention. The holes 2 and 3 are separated by the minimum allowable slope b, and the holes 3 and 4 are separated by the minimum allowable slope b. The maximum permissible inclination a and the minimum permissible inclination b are determined from a predetermined value, for example, 15 to 20 degrees, taking into consideration the thickness of the thin film and its variation.
In order to obtain the above structure, holes 2, 3,
4 and etching process is performed, the surface of the insulating thin film 6 provided on the surface of the substrate 5 of the semiconductor device is formed into a two-layer structure, and the upper layer is made of a material such as polysilicon, which has a faster etching rate than the lower layer. Since it has two layers with silicon oxide, etching in the lateral direction is faster than etching in the vertical direction.

このことにより、絶縁薄膜6の側面を、基板表面に対し
て90o以下の煩度とすることができるのである。上記
のように絶縁薄膜6に傾斜エッチングをほどこした後、
レジスト膜を剥離する。
This allows the side surface of the insulating thin film 6 to have an angle of 90 degrees or less relative to the substrate surface. After performing inclined etching on the insulating thin film 6 as described above,
Peel off the resist film.

この状態において、1一1′にそった種々の断面形状を
第2図に示す。第2図Aは半導体基板5上の絶縁薄膜6
に正常な傾斜エッチング処理がほどこされた状態を示し
ている。
In this state, various cross-sectional shapes along the line 1-1' are shown in FIG. FIG. 2A shows an insulating thin film 6 on a semiconductor substrate 5.
This shows a state where the normal inclined etching process has been applied.

第2図Bは、絶縁薄膜6の傾斜中が最大許容傾斜中以上
にエッチング処理されたために、最大許容傾斜中の2倍
の長さを有する部分の絶縁薄膜の溝部の断面形状7が三
角形になってしまっており、過度の頻度になっているこ
とを示している。
FIG. 2B shows that because the slope of the insulating thin film 6 was etched to a length greater than the maximum allowable slope, the cross-sectional shape 7 of the groove of the insulating thin film in a portion having twice the length of the maximum permissible slope becomes triangular. This shows that the frequency has become excessive.

第2図Cは、逆に、絶縁薄膜1の傾斜中が、最小許容中
以下になっているため、最小許容中の2倍の長さを有す
る部分の絶縁薄膜の溝部の断面形状8が台形になってい
る。これらの状態は、顕微鏡観察のもとに簡単に判断で
きる。すなわち、該部に光をあげると額斜部には干渉じ
まができるため、顕微鏡観察のもとでこの干渉じまの状
態を調べることにより、第2図、A,B,Cそれぞれの
状態を簡単に区別できるのである。即ち、絶縁薄膜の溝
部の断面形状7が台形であり、絶縁薄膜の溝部の断面形
状8が三角形となる様エッチング処理されていれば所定
の懐度である事が一目瞭然である。次に本発明による他
の実施例について説明する。
In FIG. 2C, on the contrary, since the inclination of the insulating thin film 1 is less than the minimum permissible value, the cross-sectional shape 8 of the groove of the insulating thin film in the portion having twice the minimum permissible length is trapezoidal. It has become. These conditions can be easily determined by microscopic observation. In other words, when light is shined on this area, interference fringes appear on the oblique part of the forehead, so by examining the state of these interference fringes under a microscope, the states of A, B, and C in Figure 2 can be determined. can be easily distinguished. That is, if the cross-sectional shape 7 of the insulating thin film groove is trapezoidal and the etching process is performed so that the cross-sectional shape 8 of the insulating thin film groove is triangular, it is obvious that the groove has a predetermined degree. Next, another embodiment according to the present invention will be described.

第3図は本発明の半導体装置の表面の一部のレジスト層
11を所定部12のみ剥離し、かつエッチング処理をほ
どこす前の状態を示す平面図を示している。前記彼処理
体に、エッチング処理をほどこした後の半導体素子の該
当部の形状を第4図に示す。Aは平面図であり、Bは、
ロー0′にそった断面図である。
FIG. 3 is a plan view showing a state in which only a predetermined portion 12 of the resist layer 11 on the surface of the semiconductor device of the present invention is removed and before etching treatment is performed. FIG. 4 shows the shape of the corresponding portion of the semiconductor element after the etching process has been applied to the etched body. A is a plan view, B is
It is a sectional view along row 0'.

第5図は、第4図の傾斜エッチングの傾斜中が許容範囲
内にあるかどうかを測定するための測定用のマスク15
を示す。
FIG. 5 shows a measurement mask 15 for measuring whether the slope of the slope etching shown in FIG. 4 is within the allowable range.
shows.

13は最大許容傾斜中を示す線、14は最小許容傾斜中
を示す線を表わしている。
Reference numeral 13 represents a line indicating the maximum allowable inclination, and 14 represents a line indicating the minimum allowable inclination.

該測定用マスクを第4図に示す傾斜エッチング処理後の
半導体素子の基板5の表面に形成された絶縁薄膜6のエ
ッチング部に置き、斜面を形成している最上部16が、
上記最大許容傾斜中を示す線13と最小許容傾斜中を示
す線との間に入ってあるかどうかを目で判定して、懐度
が許容範囲内にあるかどうかを簡単に知ることができる
。上記測定においても、あらかじめ薄膜の厚さ及びその
ばらつきを考慮して小孔12及び最大許容傾斜中13、
最小許容傾斜中14を決定する。
The measurement mask is placed on the etched part of the insulating thin film 6 formed on the surface of the substrate 5 of the semiconductor element after the inclined etching process shown in FIG.
It is possible to easily determine whether or not the degree of inclination is within the permissible range by visually determining whether it is between the line 13 indicating the maximum allowable inclination and the line indicating the minimum allowable inclination. . In the above measurement, the thickness of the thin film and its variation are taken into account in advance, and the small hole 12 and the maximum allowable slope 13 are
Determine the minimum allowable slope of 14.

上記に示すように、本発明によれば、薄膜の懐度が、許
容範囲内にあるかどうかを簡単に測定でき、測定作業の
迅速化、不良品の区別、不良品の原因究明に非常に有益
である。
As shown above, according to the present invention, it is possible to easily measure whether the elasticity of a thin film is within an allowable range, and it is very useful for speeding up measurement work, distinguishing between defective products, and investigating the cause of defective products. Beneficial.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、絶縁薄膜にエッチング処理をほどこす前の状
態を示す平面図、第2図A〜Cはそれぞれエッチング処
理後における薄膜の種々の形状を第1図1−1′にそっ
て切断して示す断面図、第3図は、エッチング処理をほ
どこす前の状態を示す平面図、第4図A,Bは、エッチ
ング処理後における薄膜の形状を示す平面図とロー0′
にそつて切断した断面図、第5図は、測定用マスクを示
す平面図である。 5・・・・・・半導体基板、6,7,8・・・・・・絶
縁薄膜の溝部断面形状。 オ/図 オ2図 才3図 オ4図 汁J図
Figure 1 is a plan view showing the state before the insulating thin film is subjected to etching treatment, and Figures 2 A to C are various shapes of the thin film after etching treatment, cut along the lines 1-1' in Figure 1. FIG. 3 is a plan view showing the state before etching treatment, and FIGS. 4A and B are plan views showing the shape of the thin film after etching treatment and row 0'.
FIG. 5 is a plan view showing the measurement mask. 5... Semiconductor substrate, 6, 7, 8... Groove cross-sectional shape of insulating thin film. O / Figure O 2 Figure Age 3 Figure O 4 Figure Juice J Figure

Claims (1)

【特許請求の範囲】[Claims] 1 半導体基板表面に被着された絶縁薄膜の上にレジス
ト膜を被着し、そのレジスト膜に複数の孔部を設け、そ
れらの孔部からエツチングを施し、前記絶縁薄膜に側壁
が傾斜した複数の溝部を形成するにあたつて、あらかじ
め前記レジスト膜の孔部を、それらの間隔が前記溝部の
側壁の最大許容傾斜巾の2倍の部位と最小許容傾斜巾の
2倍の部位とを有するように形成して、前記絶縁被膜に
前記エツチングを施し、前記複数の溝部側壁の光干渉じ
まが連続した状態にあるか否かによつて前記溝部の傾度
を判定することを特徴とするエツチング傾度判定方法。
1. A resist film is deposited on an insulating thin film deposited on the surface of a semiconductor substrate, a plurality of holes are provided in the resist film, and etching is performed from the holes to form a plurality of insulating thin films with inclined side walls. In forming the groove, the holes in the resist film are formed in advance so that the distance between them is twice as large as the maximum allowable slope width of the side wall of the groove and twice as long as the minimum allowable slope width of the side wall of the groove. The etching is performed on the insulating film, and the slope of the groove is determined based on whether or not the optical interference fringes on the side walls of the plurality of grooves are continuous. Method of determining slope.
JP51019390A 1976-02-26 1976-02-26 Etching gradient determination method Expired JPS6030099B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP51019390A JPS6030099B2 (en) 1976-02-26 1976-02-26 Etching gradient determination method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP51019390A JPS6030099B2 (en) 1976-02-26 1976-02-26 Etching gradient determination method

Publications (2)

Publication Number Publication Date
JPS52103963A JPS52103963A (en) 1977-08-31
JPS6030099B2 true JPS6030099B2 (en) 1985-07-15

Family

ID=11997945

Family Applications (1)

Application Number Title Priority Date Filing Date
JP51019390A Expired JPS6030099B2 (en) 1976-02-26 1976-02-26 Etching gradient determination method

Country Status (1)

Country Link
JP (1) JPS6030099B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS577933A (en) * 1980-06-19 1982-01-16 Nec Corp Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPS52103963A (en) 1977-08-31

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