JPS5844261B2 - Subroutine operation failure detection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device for detecting a failure during subroutine operation in an information processing device controlled by a microprogram.

an information processing device controlled by a microprogram;
For example, in an input/output control device, if the multiplicity of the subroutine exceeds the permissible multiplicity due to an error in programming or a malfunction in the microprocessor hardware while executing a subroutine instruction, or if the subroutine returns even though the subroutine is not being executed. When a command occurs, it is possible to detect it and display an error message by configuring a detection system using software, and this has traditionally been done in large computer systems. .

However, in a device controlled by a microprogram, there is a problem in that implementing such detection software increases the burden on the software.

Therefore, it is an object of the present invention to provide a device with a simple configuration for detecting failures during subroutine operation as described above using hardware.

A feature of the present invention that is distantly related to this object is a device for detecting a failure during subroutine operation of an information processing device controlled by a microprogram, the device comprising a signal generating means indicating that the subroutine is being executed; and a return command signal, and means for generating an error signal in response to the AND output.

The present invention will be described in detail below using the drawings.

FIG. 1 is a diagram illustrating subroutine jump and return operations.

As shown in this figure, when a subroutine jump instruction (SSJ) occurs while the main routine is being executed, it jumps to the first subroutine SRO and executes it, and when an SSJ instruction occurs while this subroutine SRO is executing, it jumps to the next subroutine SR1. Furthermore, when an SSJ instruction occurs in this subroutine SR1, the next subroutine S
The multiplicity increases by jumping to R2.

In the case of FIG. 1, the multiplicity is allowed up to 8 times, and when it reaches 9 times, it enters the prohibited multiplicity region and a problem occurs.

Also, in each subroutine, a return instruction (RTRN
) occurs, the process returns to the previous subroutine or main routine and the multiplicity decreases.

FIG. 2 shows a block diagram of a subroutine counter portion in one embodiment of the present invention.

In this figure, 1 is a subroutine counter, which is an up/down counter that counts the multiplicity of subroutines.

This counter 1 has 4-bit outputs 5UBO and 5UBI.
, 5UB2.5UB3, and the return address of the subroutine is generally written on these output ports. In this embodiment, the signal is applied to an AND circuit 2 having a 4-bit negative input terminal.

The output of the AND circuit 2 is when the 4-bit output of the subroutine counter 1 is all “0”, that is, the first subroutine S
It becomes “1” while RO is running, and this output is 5UBALL.
AND circuit 11 (described later) of the fault detection circuit as the O signal
(Fig. 3).

The signal 5UBALLO obtained by inverting this signal 5UBALLO by the NOT circuit 3 is applied to one input terminal of the NAND circuit 4.

The other input terminal of the NAND circuit 4 receives the decoded signal when a return command of each subroutine is generated, that is,
A DCDRTRN signal is applied.

Therefore, the output of the NAND circuit 4 is the first subroutine S,
It becomes "0" for each return instruction in each subroutine except RO, and becomes "1" in all other cases.

The output of this NAND circuit 4 is inverted by passing through an OR circuit 5 having a negative input terminal, and is applied to one input terminal of an AND circuit 6.

Furthermore, when an SSJ command is generated, the OR circuit 5 is applied with a DCD SSJ signal which is decoded and inverted.

This signal is inverted at the input section of the OR circuit 50 and then applied to the input terminal of the AND circuit 6.

The other three input terminals of the antenna circuit 6 are a clock pulse CLK that is applied twice during one operation cycle, a timing signal Tx that represents the second half of each operation cycle, and a signal that indicates that the program flow is within a subroutine area. The configuration is such that a signal representing FTSSJ is applied to each of them.

The output terminal of the AND circuit 6 is connected to the clock terminal of the subroutine counter 1.

In addition, the DCDRTRN signal is applied to the count up/down switching control terminal (U/D) of subroutine counter 1, and when the signal is "1", the countdown is performed, and when it is 'O', the countdown is performed. It is set to perform the up operation respectively.

Next, the counting operation of this subroutine counter 1 will be explained.

When the SSJ instruction occurs in the main routine, the program jumps to the subroutine SRO, but in this case, since the FTSSJ signal is "0" as described later, the logical AND output from the AND circuit 6 becomes "0".

Therefore, since the clock CLK is not applied to the counter 1, its output remains at the initial setting value (o, o, o, o).

When an SSJ instruction occurs in subroutine SRO, the program jumps to subroutine SR1.

In this case, as described later, the FTSSJ signal is "1", so the AND output of the clock CLK, timing signal Tx, FTSSJ signal, and DCDS8J signal becomes "1" as shown in FIG. is applied to counter 1.

As a result, counter 1 is counted up and its output becomes (0, 0, 0, 1).

Thereafter, the counter 1 is sequentially counted up in response to the SSJ command.

When a return instruction occurs during subroutine execution, if the subroutine being executed is not SRO, 5UB
Since the ALLO signal is "1", the NAND circuit 4 is turned on, the DCDRTRN signal is applied to the AND circuit 6, and the clock CLK is applied to the counter 1 (see FIG. 4).

In this case, since the DCRTRN signal is also applied to the switching control terminal U/D, the counter 1 counts down in accordance with this clock CLK.

If a return instruction occurs in subroutine SRO, the program returns to the main routine, but in this case, US 5U
Since the BALLO signal is "O", the counter 1 does not perform a counting operation.

In FIG. 4, A is the clock CLK, B is the content of subroutine counter 1, and C is the SSJ instruction and RTR.
The decode signal of the N instruction and D represent the timing signal Tx, respectively.

FIG. 3 is a block diagram showing the failure detection circuit portion of this embodiment.

In this figure, T and 8 are clocked RS flip-flops, flip-flop 7 is used to form the FTSSJ signal and US FTSSJ signal, and flip-flop 8 is used to form the error signal indicating the occurrence of a fault. It will be done.

AND circuits 9 and 10 are connected to the clock terminals of flip-flops 7 and 8, respectively, and are configured so that clock CLK and timing signal Tx are both applied to these AND circuits 9 and 10.

A set input terminal and a reset input terminal of the flip-flop 7 are connected to AND circuits 11 and 120 output terminals, respectively.

The AND circuit 110 input terminal includes the DCDSSJ signal and the 5
It is configured so that the UBALLO signal is applied,
The input terminal of the AND circuit 120 is configured to receive the DCDRTRNCD and 5UBALLO signals.

The Q output terminal of the flip-flop 7 is connected to one input terminal of the AND circuit 13, and is configured to be applied to the other input terminal of the AND circuit 13 on DCDRTRNCD.

The output terminal of the AND circuit 13 is connected to the set input terminal of the flip-flop 80 via an OR circuit 14.

The other input terminal of the OR circuit 14 is connected to the most significant bit signal 5U of the subroutine counter 1 described in connection with FIG.
B3 is applied.

The Q output of flip-flop 8 is used as an error signal.

Next, the operation of the circuit shown in FIG. 3 will be explained.

Flip-flop 7 has DCDSSJ signal and 5UBALL
It is set when the AND output with the O signal is "1".

That is, it is set when jumping from the main routine to the first subroutine SRO.

Also, flip-flop 7 is 5UB on DCDRTRNCD.
It is reset when the AND output with the ALLO signal is "1".

That is, it is reset when returning to the main routine from the first subroutine SRO.

Therefore, the Q output portion of the flip-flop 7, ie, the FTSSJ signal, becomes "1" when the program is being executed in the subroutine area.

Conversely, the Q output section FTSSJ signal becomes "0" in the subroutine area.

Flip-flop 8 is the US FTSSJ signal and DCDRTR
It is set when the AND output on the NCD becomes "1".

That is, when a return instruction occurs even though no program is being executed in the subroutine area, the flip-flop 8 is set and its Q output becomes an error signal.

Furthermore, when the 5UB3 signal becomes "1", the flip-flop 8 outputs the output of the subroutine counter 1 (1).
, 0, 0, O) or more, it is set and an error signal is generated.

As explained above, the fault detection device of the present invention includes a signal generating means indicating that a subroutine is being executed, a means for outputting a logical product of the signal and a return command signal, and an error detecting device according to the logical product output. Since it is equipped with a means for generating a signal and a means for generating an error signal according to the most significant bit output of the subroutine counter, an error signal is generated when a return instruction is generated even though no program is being executed in the subroutine area. can be realized with simple hardware.

Further, in this embodiment, since the most significant bit signal of the subroutine counter is entered as a logical sum in the error signal generation condition, it is also possible to check whether the multiplicity of the subroutine exceeds the allowable value 8.

Therefore, it has the advantage of being able to reduce the burden on software.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of subroutine jump and return operations, FIGS. 2 and 3 are block diagrams of an embodiment of the present invention, and FIG. 4 is a waveform diagram illustrating the operation of the above embodiment. 1... Subroutine counter, 2, 5, 6, 9
゜10.11,12,13...AND circuit, 3
...Negation circuit, 4...Nand circuit, 7
．． 8...Flip-flop, 14...
OR circuit.

Claims (1)

[Claims] 1 A device for detecting a failure during subroutine operation of an information processing device controlled by a microprogram, comprising a signal generating means indicating that the subroutine is being executed, and an AND of an inverted signal of the signal and a return command signal. What is claimed is: 1. A subroutine operation failure detection device comprising: means for outputting a logical product; and means for generating an error signal in response to the AND output.