JPS6059608B2 - multiprocessor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to multiprocessors, and particularly to a multiprocessor equipped with a memory read control circuit that prevents malfunctions.

Despite the fact that multiprocessors are equipped with many arithmetic units (ALUs) to check their operation,
Since the program address selection circuit that specifies memory addresses only has a parity check function, even if the address specification instruction from the arithmetic unit is accurate, the memory address selection by the next program step will ultimately be performed accurately. The problem is that this is not guaranteed.

An object of the present invention is to eliminate the problems of the prior art as described above, and to provide a multiprocessor that can prevent malfunctions in advance by checking memory output data.

DESCRIPTION OF THE PREFERRED EMBODIMENTS A memory read circuit for a multiprocessor, which is an embodiment of the present invention, will be described in detail below with reference to the drawings. In the multiprocessor shown in the figure, an address signal e is applied to an address check circuit 3 by applying a clock pulse (CLK) to an address selection circuit, for example, a program counter 2.
and enter it in the memo I month.

By inputting this address signal e, the memory 1 outputs a data signal a corresponding to the designated address, and the internal operation command of this data signal a is input to the operation command decoder circuit 4, and is calculated by the output signal c. Unit 5 executes the designated command operation. By simultaneously inputting this output signal c to the counter 2 and the check circuit 3, the next address j signal e is generated, and the arithmetic unit 5 sequentially executes the specified operation. When a jump instruction is specified, a jump address signal d included in data signal a is input to the program counter 2 and address check circuit 3, and the jump instruction is executed. Now, when the address check circuit 3 receives the address signal e or the jump address signal d,
It is checked whether these signals are set in the program address counter 2, and if an abnormality occurs, a signal f is output.

The timing generation control circuit 6 which receives this signal f outputs a strobe signal g to the program counter 2 in order to reset the input data of the program counter 2 again. This strobe signal g causes the counter 2 to access the memory again using the same address. These series of operations are
The address of the memory 1 is selected in response to the output signal e from the counter 2, and the process is executed within the time when the data signal a is output, that is, within the access time. Therefore, program counter 2
In case of a data acquisition failure, it is possible to perform the process again, and even after a retry, subsequent step control is possible in the event of an abnormality, so abnormal operations of the multiprocessor can be prevented. As described above, according to the present invention, the reliability of the multiprocessor can be improved because the output data of the memory input to the program counter is checked to prevent malfunctions.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a multiprocessor including a memory read control circuit according to an embodiment of the present invention. Explanation of symbols, 1... Memory, 2... Program counter, 3... Address check circuit, 4... Malfunction instruction decoder circuit, 5... Arithmetic unit , 6... timing pulse generation control circuit.

Claims (1)

[Claims] 1. In a multiprocessor that performs calculations using data signals read from a memory that stores data signals corresponding to addresses, an address selection circuit that generates an address selection signal by inputting a clock pulse and inputs a data signal from the memory. , inputting the data signal output from the memory in synchronization with the input of the address selection circuit, detecting whether or not the data signal is input to the address selection circuit, and detecting whether the data signal is input to the address selection circuit. and a data check circuit that re-accesses the data signal within a memory access time when the multi-processor detects this.