JPS5844266B2 - Multiprocessor parallel operation execution processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a parallel operation execution processing method for a multiprocessor;
Particularly in multiprocessor systems, a mask processor that serves as a mask during processing issues parallel operation instructions to slave processors in a standby state via parallel operation communication means, such as matrix operations (also known as vector operations). The present invention relates to a multiprocessor parallel operation execution processing method in which a plurality of processors share and execute individual processes such as in the following.

Here, the standby state is a state of waiting for communication from the mask processor, and may also be a state of executing a specific program in a loop.

Although the present invention is not limited thereto, for example, in matrix calculations, b1+c1 is calculated for each element.
, b2+c2, . . . , bn+cn are sequentially executed.

In such processing, the number of elements may become enormous, and when executed by only a single processor, the calculation time becomes significantly longer.

In such a case, a so-called Solomon type data processing system is being considered, in which only a plurality of arithmetic circuit units are prepared and a common control unit gives arithmetic instructions to the plurality of arithmetic circuit units.

However, such a data processing system is a special type of data processing system, and is not necessarily practical at present.

On the other hand, conventionally, a single job with an enormous amount of processing has been divided and executed by a plurality of stored program data processing devices.

However, if we try to divide processing into relatively small units such as individual arithmetic processing, many processing steps are required for synchronization processing by the operating system, such as task switching processing, which is extremely inefficient. Become something.

The present invention adopts the latter method, but without requiring complicated processing such as the task switching processing, it is possible to parallelize multiple stored program data processing devices at the user program level, for example, in individual calculation units. The purpose is to enable switching to the operating state.

Note that the function of distributing processing to a plurality of data processing devices is referred to herein as EORKOR.

Further, in this specification, a processing function in which each data processing device executes a process instructed for itself, notifies the mask processor of the process, and the mask processor confirms the completion of each process is referred to as a JOIN function. I'm calling.

The parallel operation execution processing method for a multiprocessor according to the present invention is a multiprocessor system in which a plurality of central processing units each carry out processing according to a given program. Parallel operation instruction communication means in which only a mask processor that becomes a mask issues a parallel operation instruction, and a slave processor that receives the instruction only cancels the instruction; The slave processor monitors the occurrence in the standby state, and based on the parallel operation instruction, initializes the slave processor or each processor including the mask processor to execute the parallel operation. initial setting means, parallel operation execution starting means for each processor including the slave processor or the mask processor to start executing the parallel operation; processing end instruction communication means for notifying a mask processor; processing means for the mask processor to detect and confirm a processing end instruction communication from each of the slave processors;
A main processing execution means in which the mask processor checks all process termination instruction communications from each of the slave processors and executes its own processing, and each of the slave processors receives the process termination instruction from the mask processor. The slave processor is provided with a slave processor processing execution means that shifts to a standby state or a state in which it executes its own processing upon confirmation of communication, and when a parallel operation instruction from the mask processor is detected, the slave processor in the standby state - A processor or each processor including the mask processor executes the parallel operation, and the slave processor or each processor including the mask processor prevents the completion of the parallel operation by the mask processor.
It is characterized by communicating with the processor.

This will be explained below with reference to the drawings.

FIG. 1 is an explanatory diagram illustrating an example of processing to which the processing method of the present invention is applied, FIG. 2 is a configuration of one embodiment for carrying out the present invention, and FIG. 3 is a diagram showing the configuration of another embodiment. show.

For example, in matrix calculations, in order to efficiently execute the processing, the central processing unit requests the processing to a dedicated calculation unit that executes the matrix calculation processing, for example, by pipeline processing.

However, even if this method is adopted, if the number of elements in the matrix becomes enormous as described above, the computation time will undesirably increase.

Although the present invention does not necessarily require a dedicated arithmetic unit, in the case of the present invention, a data processing device (referred to as a mask processor) that serves as a so-called mask is used to execute the processing. , other data processing devices (slave
Processing is requested to a processor (referred to as a processor) by assigning the element number used in the matrix calculation.

Figure 1 shows the situation during this time, 1-0°1-1
．． 1-2... are processing steps by the master processor, 2, 3, 4. . . . represent processing steps by individual slave processors.

While the mask processor is performing its own processing,
For example, when performing a matrix operation as shown in FIG. 1B, for example, when four processors are available, the operation is performed on elements such as element numbers rOJ, r4Je "8", . . . .

+CO, b4 + C4, ...... self, element numbers rlJ, r5J, r9J, ...
・Operations for elements such as b1+c1. b5+c
5. One slave processor performs...
Distribute the processing as follows to perform parallel operations.

At this time, the FORK function is provided in the program prepared for the mask processor.

In addition, a JOIN function is provided in the program in order to receive notification of completion of the results executed by each processor.

A slave that receives processing by the above FORK function.
A processor may be put into a standby state in advance by some means that is executing a program given to it in the meantime, or it may be put into a standby state beforehand in order to perform the above parallel operation. However, in any case, when receiving the processing assignment, it is set to be in a standby state.

When a parallel operation instruction communication is received from the mask processor as described later, initial settings are made to perform the parallel operation, and the parallel operation is executed.

Note that the initial settings may be instructed by the mask processor, may be predetermined, or may be set by the slave processor.

When each slave processor executes the processing assigned to it, it sends a processing end instruction communication to the mask processor to that effect.

The mask processor uses the JOIN function to check and confirm the processing termination instruction communication from each slave processor, and thereafter executes the program given to itself.

On the other hand, each slave processor checks that the mask processor has performed the above confirmation, and thereafter enters a standby state or its own processing.

In the above, when the mask processor performs parallel operations, the processing that each slave processor is independently executing is forcibly interrupted by the intervention of the operation system such as task switching, and each slave processor As stated at the beginning of this specification, it is impractical to switch so that the above-mentioned parallel operations can be shared.

FIG. 2 shows an embodiment of the configuration for carrying out the present invention.

In the figure, numeral 5 is a main storage device, 6 is a storage control device, 7-b to 7-3 are respective stored program processors, 8 is an input/output processor, 9-01, 9-02 . ...
..., 9-23 is a communication line between husband and husband processors, 1o-o
10-3 respectively represent communication information transmitting/receiving circuit sections.

For example, if the processor 7-0 becomes the master processor, the processor 7-0 will connect to the communication line 9-01.9.
Parallel operation instruction communication is performed via -02 and 9-03.

That is, it sets start switch information SSO for itself, sets start switch information SS1 for slave processor 7-1, and sets start switch information SS1 for slave processor 7-2.
Start switch information SS2 is set for the slave processor 7-3, and start switch information SS3 is set for the slave processor 7-3.

In this case, each slave processor 7-1 to 7-3
Assume that it is in a standby state.

In each processor, start switch information SS
Check that the has been set up and start
Initial settings for erasing switch information SS and executing parallel operations are received using, for example, an index register.

That is, for example, it receives information such as which elements should be executed and up to how many times for the matrix.

The initial setting data may be written in the main storage device 5 in advance by the mask processor 7-0, or may be set in advance.

After receiving the above-mentioned initial settings, each processor jumps to a program that performs vector summation using a branch instruction, for example, and executes vector summation on the specified elements.

FORKOR processes from instructing and executing the above assignments
I'll call you up.

When each processor executes the processing assigned to it,
The above-mentioned inter-processor communication lines 9-01, 9-02, 9-0
3 to the mask processor 7-0.
Switch information ES1゜ES2. ES3, the mask processor 7-0 self-configures the end switch information -m s .

Set.

The mask processor 7-0 processes the end switch information ESO, ESI, ES2. It is checked whether ES3 is set or not, and when all the information ES is set, the end switch information is erased and the process associated with itself is executed thereafter.

On the other hand, each slave processor 7-1 to 7-3 confirms that the end switch information ES has been erased as described above, and enters a standby state, for example.

The processing in which each of the processors notifies the end of processing and enters the respective processing is called a JOIN function.

In the case of the present invention, the above FORKOR JOIN function is
The user's program can be executed directly without using the operating system's functions such as task switching.

That is, an instruction to perform the above FORKOR function and an instruction to perform the above JOIN function are provided in the user's program, and these instructions are executed.

Of course, this does not preclude adding the above-mentioned FORKOR JOIN function to the operating system, but in the case of the embodiment shown in FIG. It is sufficient to prepare the

That is, by the command group for executing FORK or JOIN, the communication information transmitting/receiving circuit section 10 of the other processor is set to that effect via the inter-processor communication line 9, and the other processor's own communication information transmitting/receiving circuit section 10 is set to that effect. Just check the contents.

In addition, in the case shown in FIG. 2, each processor 7-b to 7
-3 can serve as a mask processor, the inter-processor communication line 9 and the like are shown to be configured symmetrically.

Of course, it goes without saying that only a predetermined processor can be determined to be a mask processor.

FIG. 3 shows the configuration of another embodiment of the present invention.

Reference numerals 5, 6, 7-0 to 7-3.8 in the figure correspond to those in FIG. An example of a program prepared for processing, 13 is a program for vector sum operation -f
Reference numeral 14 represents a communication information storage section prepared on the main storage device 5.

In the case of this embodiment, the parallel operation instruction communication and processing termination instruction communication referred to in the present invention are performed via a storage device such as the main storage device 5, for example.

That is, each processor communicates with each other by reading/writing the contents of the communication information storage section 14 on the main memory 5 under the user's program.

Note that the illustrated program step 15 corresponds to the parallel operation instruction communication process according to the present invention.

16 corresponds to initial installation processing.

17 corresponds to parallel operation execution start processing.

18 corresponds to processing end instruction confirmation processing.

19 corresponds to main processing.

Further, 20 corresponds to standby routine processing in the slave processor.

21 corresponds to a process of receiving parallel operation instruction communication.

22 corresponds to initial setting processing. 23 corresponds to parallel operation execution start processing.

24 corresponds to processing end instruction communication processing.

25 corresponds to the process of branching to the standby state.

In the illustrated case, processors such as 7-1 to 7-3, which become slave processors when executing the corresponding processes, are shown as being in a standby state by the illustrated process 20, respectively.

For example, when the mask processor 7-0 assigns the above-described parallel operation execution to each slave processor 7-1 or 7-2, the mask processor 7-0 stores information on the communication information storage unit 14 by the process 15 described above. Start sequentially
Switch information ssi.

SS2. Store SS3.

Then, in step 16, initial settings are performed.

On the other hand, each slave processor 7-1 that was in a standby state
In steps 7-3, since the start switch information SS1 to SS3 are set on the communication information storage section 14, the process moves to the process 21 and the start switch information SS set for itself is erased.

Then, in step 22, initial settings are performed.

Each processor jumps to the program 13 for vector sum operation by the illustrated process 17.23,
tL, A(i) = B(i) + C(i) is the element number assigned to itself rOJ j r4J...
rlJ, r5J..., r2J, r6J
,......

It is executed as follows: r3J r7J...

Then, the mask processor 7-0 knows by itself that the processing has ended, and each of the slave processors 7-1 to 7-3 sends a reverse signal indicating the end of processing through processing 24, respectively.

That is, end switch information E is stored on the communication information storage section 14.
SI, ES2. Set up ES3.

The mask processor 7-0 stores the end switch information ESI, ES2 . When checking whether the ES3 is set as husband or not, if all the information is set, the above information ESI is
, ES2. ES3 is erased, and after process 19, it starts its own process.

On the other hand, the slave processors 7-1, 7-2 and 7-3 respectively receive information ESI, ES2. Immediately after setting ES3, the illustrated process 25 causes a transition to a standby state according to the illustrated process 20.

Note that slave processors 7-1, 7-
2.

7-3 may enter its own processing.

As explained above, according to the present invention, in a multiprocessor system, it is possible to handle individual processing such as matrix calculation without using any complicated processing such as task switching processing by the operation system. , each processor can easily share the processing.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram illustrating an example of processing to which the processing method of the present invention is applied, FIG. 2 is a configuration of one embodiment for carrying out the present invention, and FIG. 3 is a diagram showing the configuration of another embodiment. show. In the figure, 5 is a main storage device, 6 is a storage control device, 7-0 to 7-3 are respective processors, 9 is an inter-processor communication line,
10 is a communication information transmitting/receiving circuit section, 14 is a communication information storage section,
15 is parallel operation instruction communication processing, 16 is initial installation processing, 1
7 is a parallel operation execution start process, 18 is a process end instruction confirmation process, 19 is a main process, 20 is a standby routine process, 21
2 is a parallel operation instruction communication reception process, 22 is an initial setting process, 2
3 represents a parallel operation execution start process, and 24 represents a process end instruction communication process.

Claims (1)

[Scope of Claims] 1. In a multiprocessor system in which a plurality of central processing units each perform processing according to a given program, a slave processor that is already in a standby state becomes a master for the processing. Parallel operation instruction communication means in which only the master processor issues a parallel operation instruction and the slave processor that receives the instruction only cancels the instruction; Initial setting means for monitoring the processor in the standby state and initializing each processor including the slave processor or the mask processor to execute the parallel operation based on the parallel operation instruction; Parallel operation execution starting means for each processor including the slave processor or the mask processor to start executing the parallel operation; each slave processor instructs the mask processor to finish the parallel operation processing given to it processing end instruction communication means for notifying the processing end instruction communication from each of the slave processors; processing means for the mask processor to detect and confirm the processing end instruction communication from each of the slave processors; The main processing execution means confirms all process termination instruction communication from the mask processor and executes the process being executed by itself, and each of the slave processors is placed in a standby state or self-operated upon confirmation of the process termination instruction communication by the mask processor. A slave processor processing execution means is provided for transitioning to a state in which processing is executed, and when a parallel operation instruction from the mask processor is detected, each of the slave processors or the mask processors in a standby state Execution of a parallel operation by a multiprocessor, characterized in that a processor executes the parallel operation and communicates to the mask processor the completion of the parallel operation by each processor including the slave processor or the mask processor. Processing method. 2. The parallel operation instruction communication means by which the mask processor issues parallel operation instructions to the slave processors includes an inter-processor communication line provided between the respective processors and communication information sent and received via the inter-processor communication line. 2. A multiprocessor parallel operation execution processing method according to claim 1, characterized in that the method comprises a transmitting/receiving circuit unit. 3. The parallel operation instruction communication means by which the mask processor issues parallel operation instructions to the slave processors includes a communication information storage section provided on the main memory and each processor checks the contents of the communication information storage section. 2. The multiprocessor parallel operation execution processing method according to claim 1, further comprising: a check process for executing a parallel operation in a multiprocessor. 4. The slave processor, upon completion of the parallel operation processing, enters a standby state in which it monitors the next parallel operation instruction communication. A method for executing parallel operations on multiprocessors. 5. Claims 1 to 4, characterized in that the parallel operation execution starting means is configured by means for executing an instruction at a leading address of the parallel operation processing program by a branch instruction or an interrupt instruction. A multiprocessor parallel operation execution processing method according to any one of the above. 6. The multiprocessor according to any one of claims 1 to 5, wherein the parallel operation process is a parallel operation process in which each of the processors shares a given matrix operation. Parallel operation execution processing method.